[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-s5p6440 / gpio.c

/* arch/arm/mach-s5p6440/gpio.c
 *
 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
 * 		http://www.samsung.com/
 *
 * S5P6440 - GPIOlib support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/map.h>
#include <mach/gpio.h>
#include <mach/regs-gpio.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>

/* GPIO bank summary:
*
* Bank	GPIOs	Style	SlpCon	ExtInt Group
* A	6	4Bit	Yes	1
* B	7	4Bit	Yes	1
* C	8	4Bit	Yes	2
* F	2	2Bit	Yes	4 [1]
* G	7	4Bit	Yes	5
* H	10	4Bit[2]	Yes	6
* I	16	2Bit	Yes	None
* J	12	2Bit	Yes	None
* N	16	2Bit	No	IRQ_EINT
* P	8	2Bit	Yes	8
* R	15	4Bit[2]	Yes	8
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/

static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
					     unsigned int offset)
{
	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
	void __iomem *base = ourchip->base;
	void __iomem *regcon = base;
	unsigned long con;
	unsigned long flags;

	switch (offset) {
	case 6:
		offset += 1;
	case 0:
	case 1:
	case 2:
	case 3:
	case 4:
	case 5:
		regcon -= 4;
		break;
	default:
		offset -= 7;
		break;
	}

	s3c_gpio_lock(ourchip, flags);

	con = __raw_readl(regcon);
	con &= ~(0xf << con_4bit_shift(offset));
	__raw_writel(con, regcon);

	s3c_gpio_unlock(ourchip, flags);

	return 0;
}

static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
					      unsigned int offset, int value)
{
	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
	void __iomem *base = ourchip->base;
	void __iomem *regcon = base;
	unsigned long con;
	unsigned long dat;
	unsigned long flags;
	unsigned con_offset  = offset;

	switch (con_offset) {
	case 6:
		con_offset += 1;
	case 0:
	case 1:
	case 2:
	case 3:
	case 4:
	case 5:
		regcon -= 4;
		break;
	default:
		con_offset -= 7;
		break;
	}

	s3c_gpio_lock(ourchip, flags);

	con = __raw_readl(regcon);
	con &= ~(0xf << con_4bit_shift(con_offset));
	con |= 0x1 << con_4bit_shift(con_offset);

	dat = __raw_readl(base + GPIODAT_OFF);
	if (value)
		dat |= 1 << offset;
	else
		dat &= ~(1 << offset);

	__raw_writel(con, regcon);
	__raw_writel(dat, base + GPIODAT_OFF);

	s3c_gpio_unlock(ourchip, flags);

	return 0;
}

int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
				   unsigned int off, unsigned int cfg)
{
	void __iomem *reg = chip->base;
	unsigned int shift;
	unsigned long flags;
	u32 con;

	switch (off) {
	case 0:
	case 1:
	case 2:
	case 3:
	case 4:
	case 5:
		shift = (off & 7) * 4;
		reg -= 4;
		break;
	case 6:
		shift = ((off + 1) & 7) * 4;
		reg -= 4;
	default:
		shift = ((off + 1) & 7) * 4;
		break;
	}

	if (s3c_gpio_is_cfg_special(cfg)) {
		cfg &= 0xf;
		cfg <<= shift;
	}

	s3c_gpio_lock(chip, flags);

	con = __raw_readl(reg);
	con &= ~(0xf << shift);
	con |= cfg;
	__raw_writel(con, reg);

	s3c_gpio_unlock(chip, flags);

	return 0;
}

static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
	{
		.cfg_eint	= 0,
	}, {
		.cfg_eint	= 7,
	}, {
		.cfg_eint	= 3,
		.set_config	= s5p6440_gpio_setcfg_4bit_rbank,
	}, {
		.cfg_eint	= 0,
		.set_config	= s3c_gpio_setcfg_s3c24xx,
		.get_config	= s3c_gpio_getcfg_s3c24xx,
	}, {
		.cfg_eint	= 2,
		.set_config	= s3c_gpio_setcfg_s3c24xx,
		.get_config	= s3c_gpio_getcfg_s3c24xx,
	}, {
		.cfg_eint	= 3,
		.set_config	= s3c_gpio_setcfg_s3c24xx,
		.get_config	= s3c_gpio_getcfg_s3c24xx,
	},
};

static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
	{
		.base	= S5P6440_GPA_BASE,
		.config	= &s5p6440_gpio_cfgs[1],
		.chip	= {
			.base	= S5P6440_GPA(0),
			.ngpio	= S5P6440_GPIO_A_NR,
			.label	= "GPA",
		},
	}, {
		.base	= S5P6440_GPB_BASE,
		.config	= &s5p6440_gpio_cfgs[1],
		.chip	= {
			.base	= S5P6440_GPB(0),
			.ngpio	= S5P6440_GPIO_B_NR,
			.label	= "GPB",
		},
	}, {
		.base	= S5P6440_GPC_BASE,
		.config	= &s5p6440_gpio_cfgs[1],
		.chip	= {
			.base	= S5P6440_GPC(0),
			.ngpio	= S5P6440_GPIO_C_NR,
			.label	= "GPC",
		},
	}, {
		.base	= S5P6440_GPG_BASE,
		.config	= &s5p6440_gpio_cfgs[1],
		.chip	= {
			.base	= S5P6440_GPG(0),
			.ngpio	= S5P6440_GPIO_G_NR,
			.label	= "GPG",
		},
	},
};

static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
	{
		.base	= S5P6440_GPH_BASE + 0x4,
		.config	= &s5p6440_gpio_cfgs[1],
		.chip	= {
			.base	= S5P6440_GPH(0),
			.ngpio	= S5P6440_GPIO_H_NR,
			.label	= "GPH",
		},
	},
};

static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
	{
		.base	= S5P6440_GPR_BASE + 0x4,
		.config	= &s5p6440_gpio_cfgs[2],
		.chip	= {
			.base	= S5P6440_GPR(0),
			.ngpio	= S5P6440_GPIO_R_NR,
			.label	= "GPR",
		},
	},
};

static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
	{
		.base	= S5P6440_GPF_BASE,
		.config	= &s5p6440_gpio_cfgs[5],
		.chip	= {
			.base	= S5P6440_GPF(0),
			.ngpio	= S5P6440_GPIO_F_NR,
			.label	= "GPF",
		},
	}, {
		.base	= S5P6440_GPI_BASE,
		.config	= &s5p6440_gpio_cfgs[3],
		.chip	= {
			.base	= S5P6440_GPI(0),
			.ngpio	= S5P6440_GPIO_I_NR,
			.label	= "GPI",
		},
	}, {
		.base	= S5P6440_GPJ_BASE,
		.config	= &s5p6440_gpio_cfgs[3],
		.chip	= {
			.base	= S5P6440_GPJ(0),
			.ngpio	= S5P6440_GPIO_J_NR,
			.label	= "GPJ",
		},
	}, {
		.base	= S5P6440_GPN_BASE,
		.config	= &s5p6440_gpio_cfgs[4],
		.chip	= {
			.base	= S5P6440_GPN(0),
			.ngpio	= S5P6440_GPIO_N_NR,
			.label	= "GPN",
		},
	}, {
		.base	= S5P6440_GPP_BASE,
		.config	= &s5p6440_gpio_cfgs[5],
		.chip	= {
			.base	= S5P6440_GPP(0),
			.ngpio	= S5P6440_GPIO_P_NR,
			.label	= "GPP",
		},
	},
};

void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
{
	for (; nr_chips > 0; nr_chips--, chipcfg++) {
		if (!chipcfg->set_config)
			chipcfg->set_config	= s3c_gpio_setcfg_s3c64xx_4bit;
		if (!chipcfg->get_config)
			chipcfg->get_config	= s3c_gpio_getcfg_s3c64xx_4bit;
		if (!chipcfg->set_pull)
			chipcfg->set_pull	= s3c_gpio_setpull_updown;
		if (!chipcfg->get_pull)
			chipcfg->get_pull	= s3c_gpio_getpull_updown;
	}
}

static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
						int nr_chips)
{
	for (; nr_chips > 0; nr_chips--, chip++) {
		chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input;
		chip->chip.direction_output =
					s5p6440_gpiolib_rbank_4bit2_output;
		s3c_gpiolib_add(chip);
	}
}

static int __init s5p6440_gpiolib_init(void)
{
	struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
	int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);

	s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs,
				ARRAY_SIZE(s5p6440_gpio_cfgs));

	for (; nr_chips > 0; nr_chips--, chips++)
		s3c_gpiolib_add(chips);

	samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
				ARRAY_SIZE(s5p6440_gpio_4bit));

	samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
				ARRAY_SIZE(s5p6440_gpio_4bit2));

	s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2,
				ARRAY_SIZE(gpio_rbank_4bit2));

	return 0;
}
arch_initcall(s5p6440_gpiolib_init);
Commit	Line	Data
e96b234b	1	/* arch/arm/mach-s5p6440/gpio.c
42d828d4 KK	2	*
	3	* Copyright (c) 2009 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com/
	5	*
	6	* S5P6440 - GPIOlib support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/irq.h>
	15	#include <linux/io.h>
	16	#include <mach/map.h>
	17	#include <mach/gpio.h>
	18	#include <mach/regs-gpio.h>
	19	#include <plat/gpio-core.h>
	20	#include <plat/gpio-cfg.h>
	21	#include <plat/gpio-cfg-helpers.h>
	22
	23	/* GPIO bank summary:
	24	*
	25	* Bank GPIOs Style SlpCon ExtInt Group
	26	* A 6 4Bit Yes 1
	27	* B 7 4Bit Yes 1
	28	* C 8 4Bit Yes 2
	29	* F 2 2Bit Yes 4 [1]
	30	* G 7 4Bit Yes 5
	31	* H 10 4Bit[2] Yes 6
	32	* I 16 2Bit Yes None
	33	* J 12 2Bit Yes None
	34	* N 16 2Bit No IRQ_EINT
	35	* P 8 2Bit Yes 8
	36	* R 15 4Bit[2] Yes 8
	37	*
	38	* [1] BANKF pins 14,15 do not form part of the external interrupt sources
	39	* [2] BANK has two control registers, GPxCON0 and GPxCON1
	40	*/
	41
	42	static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
	43	unsigned int offset)
	44	{
	45	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
	46	void __iomem *base = ourchip->base;
	47	void __iomem *regcon = base;
	48	unsigned long con;
6a399547	49	unsigned long flags;
42d828d4 KK	50
	51	switch (offset) {
	52	case 6:
	53	offset += 1;
	54	case 0:
	55	case 1:
	56	case 2:
	57	case 3:
	58	case 4:
	59	case 5:
	60	regcon -= 4;
	61	break;
	62	default:
	63	offset -= 7;
	64	break;
	65	}
	66
6a399547 BD	67	s3c_gpio_lock(ourchip, flags);
6a399547 BD	68
42d828d4 KK	69	con = __raw_readl(regcon);
	70	con &= ~(0xf << con_4bit_shift(offset));
	71	__raw_writel(con, regcon);
	72
6a399547 BD	73	s3c_gpio_unlock(ourchip, flags);
6a399547 BD	74
42d828d4 KK	75	return 0;
	76	}
	77
	78	static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
	79	unsigned int offset, int value)
	80	{
	81	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
	82	void __iomem *base = ourchip->base;
	83	void __iomem *regcon = base;
	84	unsigned long con;
	85	unsigned long dat;
6a399547	86	unsigned long flags;
42d828d4 KK	87	unsigned con_offset = offset;
	88
	89	switch (con_offset) {
	90	case 6:
	91	con_offset += 1;
	92	case 0:
	93	case 1:
	94	case 2:
	95	case 3:
	96	case 4:
	97	case 5:
	98	regcon -= 4;
	99	break;
	100	default:
	101	con_offset -= 7;
	102	break;
	103	}
	104
6a399547 BD	105	s3c_gpio_lock(ourchip, flags);
6a399547 BD	106
42d828d4 KK	107	con = __raw_readl(regcon);
	108	con &= ~(0xf << con_4bit_shift(con_offset));
	109	con \|= 0x1 << con_4bit_shift(con_offset);
	110
	111	dat = __raw_readl(base + GPIODAT_OFF);
	112	if (value)
	113	dat \|= 1 << offset;
	114	else
	115	dat &= ~(1 << offset);
	116
	117	__raw_writel(con, regcon);
	118	__raw_writel(dat, base + GPIODAT_OFF);
	119
6a399547 BD	120	s3c_gpio_unlock(ourchip, flags);
6a399547 BD	121
42d828d4 KK	122	return 0;
	123	}
	124
	125	int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
	126	unsigned int off, unsigned int cfg)
	127	{
	128	void __iomem *reg = chip->base;
	129	unsigned int shift;
6a399547	130	unsigned long flags;
42d828d4 KK	131	u32 con;
	132
	133	switch (off) {
	134	case 0:
	135	case 1:
	136	case 2:
	137	case 3:
	138	case 4:
	139	case 5:
	140	shift = (off & 7) * 4;
	141	reg -= 4;
	142	break;
	143	case 6:
	144	shift = ((off + 1) & 7) * 4;
	145	reg -= 4;
	146	default:
	147	shift = ((off + 1) & 7) * 4;
	148	break;
	149	}
	150
	151	if (s3c_gpio_is_cfg_special(cfg)) {
	152	cfg &= 0xf;
	153	cfg <<= shift;
	154	}
	155
6a399547 BD	156	s3c_gpio_lock(chip, flags);
6a399547 BD	157
42d828d4 KK	158	con = __raw_readl(reg);
	159	con &= ~(0xf << shift);
	160	con \|= cfg;
	161	__raw_writel(con, reg);
	162
6a399547 BD	163	s3c_gpio_unlock(chip, flags);
6a399547 BD	164
42d828d4 KK	165	return 0;
	166	}
	167
	168	static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
	169	{
	170	.cfg_eint = 0,
	171	}, {
	172	.cfg_eint = 7,
	173	}, {
	174	.cfg_eint = 3,
	175	.set_config = s5p6440_gpio_setcfg_4bit_rbank,
	176	}, {
	177	.cfg_eint = 0,
	178	.set_config = s3c_gpio_setcfg_s3c24xx,
97a33999	179	.get_config = s3c_gpio_getcfg_s3c24xx,
42d828d4 KK	180	}, {
	181	.cfg_eint = 2,
	182	.set_config = s3c_gpio_setcfg_s3c24xx,
97a33999	183	.get_config = s3c_gpio_getcfg_s3c24xx,
42d828d4 KK	184	}, {
	185	.cfg_eint = 3,
	186	.set_config = s3c_gpio_setcfg_s3c24xx,
97a33999	187	.get_config = s3c_gpio_getcfg_s3c24xx,
42d828d4 KK	188	},
	189	};
	190
	191	static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
	192	{
	193	.base = S5P6440_GPA_BASE,
	194	.config = &s5p6440_gpio_cfgs[1],
	195	.chip = {
	196	.base = S5P6440_GPA(0),
	197	.ngpio = S5P6440_GPIO_A_NR,
	198	.label = "GPA",
	199	},
	200	}, {
	201	.base = S5P6440_GPB_BASE,
	202	.config = &s5p6440_gpio_cfgs[1],
	203	.chip = {
	204	.base = S5P6440_GPB(0),
	205	.ngpio = S5P6440_GPIO_B_NR,
	206	.label = "GPB",
	207	},
	208	}, {
	209	.base = S5P6440_GPC_BASE,
	210	.config = &s5p6440_gpio_cfgs[1],
	211	.chip = {
	212	.base = S5P6440_GPC(0),
	213	.ngpio = S5P6440_GPIO_C_NR,
	214	.label = "GPC",
	215	},
	216	}, {
	217	.base = S5P6440_GPG_BASE,
	218	.config = &s5p6440_gpio_cfgs[1],
	219	.chip = {
	220	.base = S5P6440_GPG(0),
	221	.ngpio = S5P6440_GPIO_G_NR,
	222	.label = "GPG",
	223	},
	224	},
	225	};
	226
	227	static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
	228	{
	229	.base = S5P6440_GPH_BASE + 0x4,
	230	.config = &s5p6440_gpio_cfgs[1],
	231	.chip = {
	232	.base = S5P6440_GPH(0),
	233	.ngpio = S5P6440_GPIO_H_NR,
	234	.label = "GPH",
	235	},
	236	},
	237	};
	238
	239	static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
	240	{
	241	.base = S5P6440_GPR_BASE + 0x4,
	242	.config = &s5p6440_gpio_cfgs[2],
	243	.chip = {
	244	.base = S5P6440_GPR(0),
	245	.ngpio = S5P6440_GPIO_R_NR,
	246	.label = "GPR",
	247	},
	248	},
	249	};
	250
	251	static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
252	{
253	.base = S5P6440_GPF_BASE,
254	.config = &s5p6440_gpio_cfgs[5],
255	.chip = {
256	.base = S5P6440_GPF(0),
257	.ngpio = S5P6440_GPIO_F_NR,
258	.label = "GPF",
259	},
260	}, {
261	.base = S5P6440_GPI_BASE,
262	.config = &s5p6440_gpio_cfgs[3],
263	.chip = {
264	.base = S5P6440_GPI(0),
265	.ngpio = S5P6440_GPIO_I_NR,
266	.label = "GPI",
267	},
268	}, {
269	.base = S5P6440_GPJ_BASE,
270	.config = &s5p6440_gpio_cfgs[3],
271	.chip = {
272	.base = S5P6440_GPJ(0),
273	.ngpio = S5P6440_GPIO_J_NR,
274	.label = "GPJ",
275	},
276	}, {
277	.base = S5P6440_GPN_BASE,
278	.config = &s5p6440_gpio_cfgs[4],
279	.chip = {
280	.base = S5P6440_GPN(0),
281	.ngpio = S5P6440_GPIO_N_NR,
282	.label = "GPN",
283	},
284	}, {
285	.base = S5P6440_GPP_BASE,
286	.config = &s5p6440_gpio_cfgs[5],
287	.chip = {
288	.base = S5P6440_GPP(0),
289	.ngpio = S5P6440_GPIO_P_NR,
290	.label = "GPP",
291	},
292	},
293	};
294
295	void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
296	{
297	for (; nr_chips > 0; nr_chips--, chipcfg++) {
298	if (!chipcfg->set_config)
299	chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
97a33999 BD	300	if (!chipcfg->get_config)
97a33999 BD	301	chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
42d828d4 KK	302	if (!chipcfg->set_pull)
	303	chipcfg->set_pull = s3c_gpio_setpull_updown;
	304	if (!chipcfg->get_pull)
	305	chipcfg->get_pull = s3c_gpio_getpull_updown;
	306	}
	307	}
	308
	309	static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
	310	int nr_chips)
	311	{
	312	for (; nr_chips > 0; nr_chips--, chip++) {
	313	chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input;
	314	chip->chip.direction_output =
	315	s5p6440_gpiolib_rbank_4bit2_output;
	316	s3c_gpiolib_add(chip);
	317	}
	318	}
	319
	320	static int __init s5p6440_gpiolib_init(void)
	321	{
	322	struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
	323	int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
	324
	325	s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs,
	326	ARRAY_SIZE(s5p6440_gpio_cfgs));
	327
	328	for (; nr_chips > 0; nr_chips--, chips++)
	329	s3c_gpiolib_add(chips);
	330
	331	samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
	332	ARRAY_SIZE(s5p6440_gpio_4bit));
	333
	334	samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
	335	ARRAY_SIZE(s5p6440_gpio_4bit2));
	336
	337	s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2,
	338	ARRAY_SIZE(gpio_rbank_4bit2));
	339
	340	return 0;
	341	}
	342	arch_initcall(s5p6440_gpiolib_init);