[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-s5pc100 / include / mach / map.h

/* linux/arch/arm/mach-s5pc100/include/mach/map.h
 *
 * Copyright 2009 Samsung Electronics Co.
 *	Byungho Min <bhmin@samsung.com>
 *
 * S5PC100 - Memory map definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__

#include <plat/map-base.h>
#include <plat/map-s5p.h>

/*
 * map-base.h has already defined virtual memory address
 * S3C_VA_IRQ		S3C_ADDR(0x00000000)	irq controller(s)
 * S3C_VA_SYS		S3C_ADDR(0x00100000)	system control
 * S3C_VA_MEM		S3C_ADDR(0x00200000)	system control (not used)
 * S3C_VA_TIMER		S3C_ADDR(0x00300000)	timer block
 * S3C_VA_WATCHDOG	S3C_ADDR(0x00400000)	watchdog
 * S3C_VA_UART		S3C_ADDR(0x01000000)	UART
 *
 * S5PC100 specific virtual memory address can be defined here
 * S5PC1XX_VA_GPIO	S3C_ADDR(0x00500000)	GPIO
 *
 */

#define S5PC100_PA_ONENAND_BUF	(0xB0000000)
#define S5PC100_SZ_ONENAND_BUF	(SZ_256M - SZ_32M)

/* Chip ID */

#define S5PC100_PA_CHIPID	(0xE0000000)
#define S5P_PA_CHIPID		S5PC100_PA_CHIPID

#define S5PC100_PA_SYSCON	(0xE0100000)
#define S5P_PA_SYSCON		S5PC100_PA_SYSCON

#define S5PC100_PA_OTHERS	(0xE0200000)
#define S5PC100_VA_OTHERS	(S3C_VA_SYS + 0x10000)

#define S5P_PA_GPIO		(0xE0300000)
#define S5PC1XX_VA_GPIO		S3C_ADDR(0x00500000)

/* Interrupt */
#define S5PC100_PA_VIC		(0xE4000000)
#define S5PC100_VA_VIC		S3C_VA_IRQ
#define S5PC100_PA_VIC_OFFSET	0x100000
#define S5PC100_VA_VIC_OFFSET	0x10000
#define S5PC1XX_PA_VIC(x)	(S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
#define S5PC1XX_VA_VIC(x)	(S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
#define S5P_PA_VIC0		S5PC1XX_PA_VIC(0)
#define S5P_PA_VIC1		S5PC1XX_PA_VIC(1)
#define S5P_PA_VIC2		S5PC1XX_PA_VIC(2)


#define S5PC100_PA_ONENAND	(0xE7100000)

/* DMA */
#define S5PC100_PA_MDMA		(0xE8100000)
#define S5PC100_PA_PDMA0	(0xE9000000)
#define S5PC100_PA_PDMA1	(0xE9200000)

/* Timer */
#define S5PC100_PA_TIMER	(0xEA000000)
#define S5P_PA_TIMER		S5PC100_PA_TIMER

#define S5PC100_PA_SYSTIMER	(0xEA100000)

#define S5PC100_PA_UART		(0xEC000000)

#define S5P_PA_UART0		(S5PC100_PA_UART + 0x0)
#define S5P_PA_UART1		(S5PC100_PA_UART + 0x400)
#define S5P_PA_UART2		(S5PC100_PA_UART + 0x800)
#define S5P_PA_UART3		(S5PC100_PA_UART + 0xC00)
#define S5P_SZ_UART		SZ_256

#define S5PC100_PA_IIC0		(0xEC100000)
#define S5PC100_PA_IIC1		(0xEC200000)

/* SPI */
#define S5PC100_PA_SPI0		0xEC300000
#define S5PC100_PA_SPI1		0xEC400000
#define S5PC100_PA_SPI2		0xEC500000

/* USB HS OTG */
#define S5PC100_PA_USB_HSOTG	(0xED200000)
#define S5PC100_PA_USB_HSPHY	(0xED300000)

#define S5PC100_PA_FB		(0xEE000000)

#define S5PC100_PA_FIMC0	(0xEE200000)
#define S5PC100_PA_FIMC1	(0xEE300000)
#define S5PC100_PA_FIMC2	(0xEE400000)

#define S5PC100_PA_I2S0		(0xF2000000)
#define S5PC100_PA_I2S1		(0xF2100000)
#define S5PC100_PA_I2S2		(0xF2200000)

#define S5PC100_PA_AC97		0xF2300000

/* PCM */
#define S5PC100_PA_PCM0		0xF2400000
#define S5PC100_PA_PCM1		0xF2500000

/* KEYPAD */
#define S5PC100_PA_KEYPAD	(0xF3100000)

#define S5PC100_PA_HSMMC(x)	(0xED800000 + ((x) * 0x100000))

#define S5PC100_PA_SDRAM	(0x20000000)
#define S5P_PA_SDRAM		S5PC100_PA_SDRAM

/* compatibiltiy defines. */
#define S3C_PA_UART		S5PC100_PA_UART
#define S3C_PA_IIC		S5PC100_PA_IIC0
#define S3C_PA_IIC1		S5PC100_PA_IIC1
#define S3C_PA_FB		S5PC100_PA_FB
#define S3C_PA_G2D		S5PC100_PA_G2D
#define S3C_PA_G3D		S5PC100_PA_G3D
#define S3C_PA_JPEG		S5PC100_PA_JPEG
#define S3C_PA_ROTATOR		S5PC100_PA_ROTATOR
#define S5P_VA_VIC0		S5PC1XX_VA_VIC(0)
#define S5P_VA_VIC1		S5PC1XX_VA_VIC(1)
#define S5P_VA_VIC2		S5PC1XX_VA_VIC(2)
#define S3C_PA_USB_HSOTG	S5PC100_PA_USB_HSOTG
#define S3C_PA_USB_HSPHY	S5PC100_PA_USB_HSPHY
#define S3C_PA_HSMMC0		S5PC100_PA_HSMMC(0)
#define S3C_PA_HSMMC1		S5PC100_PA_HSMMC(1)
#define S3C_PA_HSMMC2		S5PC100_PA_HSMMC(2)
#define S3C_PA_KEYPAD		S5PC100_PA_KEYPAD
#define S3C_PA_TSADC		S5PC100_PA_TSADC
#define S3C_PA_ONENAND		S5PC100_PA_ONENAND
#define S3C_PA_ONENAND_BUF	S5PC100_PA_ONENAND_BUF
#define S3C_SZ_ONENAND_BUF	S5PC100_SZ_ONENAND_BUF

#define S5P_PA_FIMC0		S5PC100_PA_FIMC0
#define S5P_PA_FIMC1		S5PC100_PA_FIMC1
#define S5P_PA_FIMC2		S5PC100_PA_FIMC2

#endif /* __ASM_ARCH_C100_MAP_H */
Commit	Line	Data
ff54b457 BM	1	/* linux/arch/arm/mach-s5pc100/include/mach/map.h
	2	*
	3	* Copyright 2009 Samsung Electronics Co.
	4	* Byungho Min <bhmin@samsung.com>
	5	*
acc84707	6	* S5PC100 - Memory map definitions
ff54b457 BM	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __ASM_ARCH_MAP_H
	14	#define __ASM_ARCH_MAP_H __FILE__
	15
	16	#include <plat/map-base.h>
acc84707	17	#include <plat/map-s5p.h>
ff54b457	18
b0cc3031 KP	19	/*
	20	* map-base.h has already defined virtual memory address
	21	* S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s)
	22	* S3C_VA_SYS S3C_ADDR(0x00100000) system control
	23	* S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used)
	24	* S3C_VA_TIMER S3C_ADDR(0x00300000) timer block
	25	* S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
	26	* S3C_VA_UART S3C_ADDR(0x01000000) UART
	27	*
	28	* S5PC100 specific virtual memory address can be defined here
	29	* S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
	30	*
	31	*/
ff54b457	32
999304be MS	33	#define S5PC100_PA_ONENAND_BUF (0xB0000000)
	34	#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
	35
ff54b457	36	/* Chip ID */
206a1a82	37
ff54b457	38	#define S5PC100_PA_CHIPID (0xE0000000)
acc84707 MS	39	#define S5P_PA_CHIPID S5PC100_PA_CHIPID
	40
	41	#define S5PC100_PA_SYSCON (0xE0100000)
	42	#define S5P_PA_SYSCON S5PC100_PA_SYSCON
	43
	44	#define S5PC100_PA_OTHERS (0xE0200000)
	45	#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
	46
45c79433	47	#define S5P_PA_GPIO (0xE0300000)
b0cc3031	48	#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
ff54b457 BM	49
	50	/* Interrupt */
	51	#define S5PC100_PA_VIC (0xE4000000)
	52	#define S5PC100_VA_VIC S3C_VA_IRQ
	53	#define S5PC100_PA_VIC_OFFSET 0x100000
	54	#define S5PC100_VA_VIC_OFFSET 0x10000
	55	#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
	56	#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
45c79433 BD	57	#define S5P_PA_VIC0 S5PC1XX_PA_VIC(0)
	58	#define S5P_PA_VIC1 S5PC1XX_PA_VIC(1)
	59	#define S5P_PA_VIC2 S5PC1XX_PA_VIC(2)
	60
b0cc3031	61
999304be	62	#define S5PC100_PA_ONENAND (0xE7100000)
ff54b457	63
b0cc3031 KP	64	/* DMA */
	65	#define S5PC100_PA_MDMA (0xE8100000)
	66	#define S5PC100_PA_PDMA0 (0xE9000000)
	67	#define S5PC100_PA_PDMA1 (0xE9200000)
b0cc3031	68
ff54b457	69	/* Timer */
acc84707 MS	70	#define S5PC100_PA_TIMER (0xEA000000)
acc84707 MS	71	#define S5P_PA_TIMER S5PC100_PA_TIMER
b0cc3031	72
acc84707	73	#define S5PC100_PA_SYSTIMER (0xEA100000)
b0cc3031	74
acc84707	75	#define S5PC100_PA_UART (0xEC000000)
b0cc3031	76
acc84707 MS	77	#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0)
	78	#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400)
	79	#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800)
	80	#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
	81	#define S5P_SZ_UART SZ_256
b0cc3031	82
acc84707 MS	83	#define S5PC100_PA_IIC0 (0xEC100000)
acc84707 MS	84	#define S5PC100_PA_IIC1 (0xEC200000)
b0cc3031	85
7c3943f6 JB	86	/* SPI */
	87	#define S5PC100_PA_SPI0 0xEC300000
	88	#define S5PC100_PA_SPI1 0xEC400000
	89	#define S5PC100_PA_SPI2 0xEC500000
	90
b0cc3031 KP	91	/* USB HS OTG */
	92	#define S5PC100_PA_USB_HSOTG (0xED200000)
	93	#define S5PC100_PA_USB_HSPHY (0xED300000)
	94
acc84707	95	#define S5PC100_PA_FB (0xEE000000)
b0cc3031	96
33c14ff8 SN	97	#define S5PC100_PA_FIMC0 (0xEE200000)
	98	#define S5PC100_PA_FIMC1 (0xEE300000)
	99	#define S5PC100_PA_FIMC2 (0xEE400000)
	100
45c79433 BD	101	#define S5PC100_PA_I2S0 (0xF2000000)
	102	#define S5PC100_PA_I2S1 (0xF2100000)
	103	#define S5PC100_PA_I2S2 (0xF2200000)
	104
9e4ed5c3 JB	105	#define S5PC100_PA_AC97 0xF2300000
	106
	107	/* PCM */
	108	#define S5PC100_PA_PCM0 0xF2400000
	109	#define S5PC100_PA_PCM1 0xF2500000
	110
b0cc3031 KP	111	/* KEYPAD */
	112	#define S5PC100_PA_KEYPAD (0xF3100000)
	113
acc84707	114	#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
ff54b457	115
ff54b457	116	#define S5PC100_PA_SDRAM (0x20000000)
acc84707	117	#define S5P_PA_SDRAM S5PC100_PA_SDRAM
ff54b457	118
acc84707	119	/* compatibiltiy defines. */
ff54b457	120	#define S3C_PA_UART S5PC100_PA_UART
acc84707 MS	121	#define S3C_PA_IIC S5PC100_PA_IIC0
acc84707 MS	122	#define S3C_PA_IIC1 S5PC100_PA_IIC1
b0cc3031 KP	123	#define S3C_PA_FB S5PC100_PA_FB
	124	#define S3C_PA_G2D S5PC100_PA_G2D
	125	#define S3C_PA_G3D S5PC100_PA_G3D
	126	#define S3C_PA_JPEG S5PC100_PA_JPEG
	127	#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
45c79433 BD	128	#define S5P_VA_VIC0 S5PC1XX_VA_VIC(0)
	129	#define S5P_VA_VIC1 S5PC1XX_VA_VIC(1)
	130	#define S5P_VA_VIC2 S5PC1XX_VA_VIC(2)
b0cc3031 KP	131	#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
b0cc3031 KP	132	#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
45c79433 BD	133	#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
	134	#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
	135	#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
b0cc3031 KP	136	#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
b0cc3031 KP	137	#define S3C_PA_TSADC S5PC100_PA_TSADC
999304be MS	138	#define S3C_PA_ONENAND S5PC100_PA_ONENAND
	139	#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
	140	#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
ff54b457	141
33c14ff8 SN	142	#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
	143	#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
	144	#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
	145
ff54b457	146	#endif /* __ASM_ARCH_C100_MAP_H */