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1 | /* arch/arm/mach-s5pc100/include/mach/regs-fb.h |
2 | * | |
3 | * Copyright 2009 Samsung Electronics Co. | |
4 | * Pawel Osciak <p.osciak@samsung.com> | |
5 | * | |
6 | * Framebuffer register definitions for Samsung S5PC100. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARCH_REGS_FB_H | |
14 | #define __ASM_ARCH_REGS_FB_H __FILE__ | |
15 | ||
16 | #include <plat/regs-fb-v4.h> | |
17 | ||
18 | /* VP1 interface timing control */ | |
19 | #define VP1CON0 (0x118) | |
20 | #define VP1_RATECON_EN (1 << 31) | |
21 | #define VP1_CLKRATE_MASK (0xff) | |
22 | ||
23 | #define VP1CON1 (0x11c) | |
24 | #define VP1_VTREGCON_EN (1 << 31) | |
25 | #define VP1_VBPD_MASK (0xfff) | |
26 | #define VP1_VBPD_SHIFT (16) | |
27 | ||
28 | ||
29 | #define WPALCON_H (0x19c) | |
30 | #define WPALCON_L (0x1a0) | |
31 | ||
25985edc | 32 | /* Palette control for WPAL0 and WPAL1 is the same as in S3C64xx, but |
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33 | * different for WPAL2-4 |
34 | */ | |
35 | /* In WPALCON_L (aka WPALCON) */ | |
36 | #define WPALCON_W1PAL_32BPP_A888 (0x7 << 3) | |
37 | #define WPALCON_W0PAL_32BPP_A888 (0x7 << 0) | |
38 | ||
39 | /* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H, | |
40 | * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]). | |
41 | */ | |
42 | #define WPALCON_L_WxPAL_L_MASK (0x1) | |
43 | #define WPALCON_L_W2PAL_L_SHIFT (6) | |
44 | #define WPALCON_L_W3PAL_L_SHIFT (7) | |
45 | #define WPALCON_L_W4PAL_L_SHIFT (8) | |
46 | ||
47 | #define WPALCON_L_WxPAL_H_MASK (0x3) | |
48 | #define WPALCON_H_W2PAL_H_SHIFT (9) | |
49 | #define WPALCON_H_W3PAL_H_SHIFT (13) | |
50 | #define WPALCON_H_W4PAL_H_SHIFT (17) | |
51 | ||
52 | /* Per-window alpha value registers */ | |
53 | /* For window 0 8-bit alpha values are in VIDW0ALPHAx, | |
54 | * for windows 1-4 alpha values consist of two parts, the 4 low bits are | |
55 | * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC, | |
56 | * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0]) | |
57 | */ | |
58 | #define VIDWxALPHA0(_win) (0x200 + (_win * 8)) | |
59 | #define VIDWxALPHA1(_win) (0x204 + (_win * 8)) | |
60 | ||
61 | /* Only for window 0 in VIDW0ALPHAx. */ | |
62 | #define VIDW0ALPHAx_R(_x) ((_x) << 16) | |
63 | #define VIDW0ALPHAx_R_MASK (0xff << 16) | |
64 | #define VIDW0ALPHAx_R_SHIFT (16) | |
65 | #define VIDW0ALPHAx_G(_x) ((_x) << 8) | |
66 | #define VIDW0ALPHAx_G_MASK (0xff << 8) | |
67 | #define VIDW0ALPHAx_G_SHIFT (8) | |
68 | #define VIDW0ALPHAx_B(_x) ((_x) << 0) | |
69 | #define VIDW0ALPHAx_B_MASK (0xff << 0) | |
70 | #define VIDW0ALPHAx_B_SHIFT (0) | |
71 | ||
72 | /* Low 4 bits of alpha0-1 for windows 1-4 */ | |
73 | #define VIDW14ALPHAx_R_L(_x) ((_x) << 16) | |
74 | #define VIDW14ALPHAx_R_L_MASK (0xf << 16) | |
75 | #define VIDW14ALPHAx_R_L_SHIFT (16) | |
76 | #define VIDW14ALPHAx_G_L(_x) ((_x) << 8) | |
77 | #define VIDW14ALPHAx_G_L_MASK (0xf << 8) | |
78 | #define VIDW14ALPHAx_G_L_SHIFT (8) | |
79 | #define VIDW14ALPHAx_B_L(_x) ((_x) << 0) | |
80 | #define VIDW14ALPHAx_B_L_MASK (0xf << 0) | |
81 | #define VIDW14ALPHAx_B_L_SHIFT (0) | |
82 | ||
83 | ||
84 | /* Per-window blending equation control registers */ | |
85 | #define BLENDEQx(_win) (0x244 + ((_win) * 4)) | |
86 | #define BLENDEQ1 (0x244) | |
87 | #define BLENDEQ2 (0x248) | |
88 | #define BLENDEQ3 (0x24c) | |
89 | #define BLENDEQ4 (0x250) | |
90 | ||
91 | #define BLENDEQx_Q_FUNC(_x) ((_x) << 18) | |
92 | #define BLENDEQx_Q_FUNC_MASK (0xf << 18) | |
93 | #define BLENDEQx_P_FUNC(_x) ((_x) << 12) | |
94 | #define BLENDEQx_P_FUNC_MASK (0xf << 12) | |
95 | #define BLENDEQx_B_FUNC(_x) ((_x) << 6) | |
96 | #define BLENDEQx_B_FUNC_MASK (0xf << 6) | |
97 | #define BLENDEQx_A_FUNC(_x) ((_x) << 0) | |
98 | #define BLENDEQx_A_FUNC_MASK (0xf << 0) | |
99 | ||
100 | #define BLENDCON (0x260) | |
101 | #define BLENDCON_8BIT_ALPHA (1 << 0) | |
102 | ||
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103 | |
104 | #endif /* __ASM_ARCH_REGS_FB_H */ | |
105 |