projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 9740bdd9 | 1 | /* |
| 0c1945d3 KK |
2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
| 3 | * http://www.samsung.com/ | |
| 4 | * | |
| 5 | * S5PV210 - Clock register definitions | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __ASM_ARCH_REGS_CLOCK_H | |
| 13 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ | |
| 14 | ||
| d78c16cc | 15 | #include <plat/map-base.h> |
| 0c1945d3 KK |
16 | |
| 17 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) | |
| 18 | ||
| 19 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) | |
| 20 | #define S5P_MPLL_LOCK S5P_CLKREG(0x08) | |
| 21 | #define S5P_EPLL_LOCK S5P_CLKREG(0x10) | |
| 22 | #define S5P_VPLL_LOCK S5P_CLKREG(0x20) | |
| 23 | ||
| 24 | #define S5P_APLL_CON S5P_CLKREG(0x100) | |
| 25 | #define S5P_MPLL_CON S5P_CLKREG(0x108) | |
| 26 | #define S5P_EPLL_CON S5P_CLKREG(0x110) | |
| 42a6e20e | 27 | #define S5P_EPLL_CON1 S5P_CLKREG(0x114) |
| 0c1945d3 KK |
28 | #define S5P_VPLL_CON S5P_CLKREG(0x120) |
| 29 | ||
| 30 | #define S5P_CLK_SRC0 S5P_CLKREG(0x200) | |
| 31 | #define S5P_CLK_SRC1 S5P_CLKREG(0x204) | |
| 32 | #define S5P_CLK_SRC2 S5P_CLKREG(0x208) | |
| 33 | #define S5P_CLK_SRC3 S5P_CLKREG(0x20C) | |
| 34 | #define S5P_CLK_SRC4 S5P_CLKREG(0x210) | |
| 35 | #define S5P_CLK_SRC5 S5P_CLKREG(0x214) | |
| 36 | #define S5P_CLK_SRC6 S5P_CLKREG(0x218) | |
| 37 | ||
| 38 | #define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280) | |
| 39 | #define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284) | |
| 40 | ||
| 41 | #define S5P_CLK_DIV0 S5P_CLKREG(0x300) | |
| 42 | #define S5P_CLK_DIV1 S5P_CLKREG(0x304) | |
| 43 | #define S5P_CLK_DIV2 S5P_CLKREG(0x308) | |
| 44 | #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) | |
| 45 | #define S5P_CLK_DIV4 S5P_CLKREG(0x310) | |
| 46 | #define S5P_CLK_DIV5 S5P_CLKREG(0x314) | |
| 47 | #define S5P_CLK_DIV6 S5P_CLKREG(0x318) | |
| 48 | #define S5P_CLK_DIV7 S5P_CLKREG(0x31C) | |
| 49 | ||
| 50 | #define S5P_CLKGATE_MAIN0 S5P_CLKREG(0x400) | |
| 51 | #define S5P_CLKGATE_MAIN1 S5P_CLKREG(0x404) | |
| 52 | #define S5P_CLKGATE_MAIN2 S5P_CLKREG(0x408) | |
| 53 | ||
| 54 | #define S5P_CLKGATE_PERI0 S5P_CLKREG(0x420) | |
| 55 | #define S5P_CLKGATE_PERI1 S5P_CLKREG(0x424) | |
| 56 | ||
| 57 | #define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x440) | |
| 58 | #define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x444) | |
| 59 | #define S5P_CLKGATE_IP0 S5P_CLKREG(0x460) | |
| 60 | #define S5P_CLKGATE_IP1 S5P_CLKREG(0x464) | |
| 61 | #define S5P_CLKGATE_IP2 S5P_CLKREG(0x468) | |
| 62 | #define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) | |
| 63 | #define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) | |
| 64 | ||
| 65 | #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) | |
| 66 | #define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) | |
| 67 | #define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) | |
| 68 | #define S5P_CLK_OUT S5P_CLKREG(0x500) | |
| 69 | ||
| 3c599216 JL |
70 | /* DIV/MUX STATUS */ |
| 71 | #define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000) | |
| 72 | #define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004) | |
| 73 | #define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100) | |
| 74 | #define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104) | |
| 75 | ||
| 0c1945d3 | 76 | /* CLKSRC0 */ |
| 3c599216 JL |
77 | #define S5P_CLKSRC0_MUX200_SHIFT (16) |
| 78 | #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) | |
| 0c1945d3 KK |
79 | #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) |
| 80 | #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) | |
| 81 | ||
| 3c599216 JL |
82 | /* CLKSRC2 */ |
| 83 | #define S5P_CLKSRC2_G3D_SHIFT (0) | |
| 84 | #define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT) | |
| 85 | #define S5P_CLKSRC2_MFC_SHIFT (4) | |
| 86 | #define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT) | |
| 87 | ||
| 88 | /* CLKSRC6*/ | |
| 89 | #define S5P_CLKSRC6_ONEDRAM_SHIFT (24) | |
| 90 | #define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT) | |
| 91 | ||
| 0c1945d3 KK |
92 | /* CLKDIV0 */ |
| 93 | #define S5P_CLKDIV0_APLL_SHIFT (0) | |
| 94 | #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) | |
| 95 | #define S5P_CLKDIV0_A2M_SHIFT (4) | |
| 96 | #define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) | |
| 97 | #define S5P_CLKDIV0_HCLK200_SHIFT (8) | |
| 98 | #define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT) | |
| 99 | #define S5P_CLKDIV0_PCLK100_SHIFT (12) | |
| 100 | #define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT) | |
| 101 | #define S5P_CLKDIV0_HCLK166_SHIFT (16) | |
| 102 | #define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT) | |
| 103 | #define S5P_CLKDIV0_PCLK83_SHIFT (20) | |
| 104 | #define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT) | |
| 105 | #define S5P_CLKDIV0_HCLK133_SHIFT (24) | |
| 106 | #define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT) | |
| 107 | #define S5P_CLKDIV0_PCLK66_SHIFT (28) | |
| 108 | #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) | |
| 109 | ||
| 3c599216 JL |
110 | /* CLKDIV2 */ |
| 111 | #define S5P_CLKDIV2_G3D_SHIFT (0) | |
| 112 | #define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT) | |
| 113 | #define S5P_CLKDIV2_MFC_SHIFT (4) | |
| 114 | #define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT) | |
| 115 | ||
| 116 | /* CLKDIV6 */ | |
| 117 | #define S5P_CLKDIV6_ONEDRAM_SHIFT (28) | |
| 118 | #define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT) | |
| 119 | ||
| 4550ee20 JL |
120 | #define S5P_SWRESET S5P_CLKREG(0x2000) |
| 121 | ||
| 3c599216 JL |
122 | #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) |
| 123 | ||
| 0c1945d3 KK |
124 | /* Registers related to power management */ |
| 125 | #define S5P_PWR_CFG S5P_CLKREG(0xC000) | |
| 126 | #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) | |
| ea31fd43 | 127 | #define S5P_WAKEUP_MASK S5P_CLKREG(0xC008) |
| 0c1945d3 KK |
128 | #define S5P_PWR_MODE S5P_CLKREG(0xC00C) |
| 129 | #define S5P_NORMAL_CFG S5P_CLKREG(0xC010) | |
| 130 | #define S5P_IDLE_CFG S5P_CLKREG(0xC020) | |
| 131 | #define S5P_STOP_CFG S5P_CLKREG(0xC030) | |
| 132 | #define S5P_STOP_MEM_CFG S5P_CLKREG(0xC034) | |
| 133 | #define S5P_SLEEP_CFG S5P_CLKREG(0xC040) | |
| 134 | ||
| 135 | #define S5P_OSC_FREQ S5P_CLKREG(0xC100) | |
| 136 | #define S5P_OSC_STABLE S5P_CLKREG(0xC104) | |
| 137 | #define S5P_PWR_STABLE S5P_CLKREG(0xC108) | |
| 138 | #define S5P_MTC_STABLE S5P_CLKREG(0xC110) | |
| 139 | #define S5P_CLAMP_STABLE S5P_CLKREG(0xC114) | |
| 140 | ||
| 141 | #define S5P_WAKEUP_STAT S5P_CLKREG(0xC200) | |
| 142 | #define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204) | |
| 143 | ||
| 144 | #define S5P_OTHERS S5P_CLKREG(0xE000) | |
| 145 | #define S5P_OM_STAT S5P_CLKREG(0xE100) | |
| fbf05563 | 146 | #define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) |
| 0c1945d3 | 147 | #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) |
| fbf05563 | 148 | #define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810) |
| 0c1945d3 KK |
149 | |
| 150 | #define S5P_INFORM0 S5P_CLKREG(0xF000) | |
| 151 | #define S5P_INFORM1 S5P_CLKREG(0xF004) | |
| 152 | #define S5P_INFORM2 S5P_CLKREG(0xF008) | |
| 153 | #define S5P_INFORM3 S5P_CLKREG(0xF00C) | |
| 154 | #define S5P_INFORM4 S5P_CLKREG(0xF010) | |
| 155 | #define S5P_INFORM5 S5P_CLKREG(0xF014) | |
| 156 | #define S5P_INFORM6 S5P_CLKREG(0xF018) | |
| 157 | #define S5P_INFORM7 S5P_CLKREG(0xF01C) | |
| 158 | ||
| 159 | #define S5P_RST_STAT S5P_CLKREG(0xA000) | |
| 160 | #define S5P_OSC_CON S5P_CLKREG(0x8000) | |
| 5b696a67 | 161 | #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) |
| 0c1945d3 KK |
162 | #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) |
| 163 | #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) | |
| 0c1945d3 KK |
164 | |
| 165 | #define S5P_IDLE_CFG_TL_MASK (3 << 30) | |
| 166 | #define S5P_IDLE_CFG_TM_MASK (3 << 28) | |
| 167 | #define S5P_IDLE_CFG_TL_ON (2 << 30) | |
| 168 | #define S5P_IDLE_CFG_TM_ON (2 << 28) | |
| 169 | #define S5P_IDLE_CFG_DIDLE (1 << 0) | |
| 170 | ||
| 171 | #define S5P_CFG_WFI_CLEAN (~(3 << 8)) | |
| 172 | #define S5P_CFG_WFI_IDLE (1 << 8) | |
| 173 | #define S5P_CFG_WFI_STOP (2 << 8) | |
| 174 | #define S5P_CFG_WFI_SLEEP (3 << 8) | |
| 175 | ||
| 176 | #define S5P_OTHER_SYS_INT 24 | |
| 177 | #define S5P_OTHER_STA_TYPE 23 | |
| 178 | #define S5P_OTHER_SYSC_INTOFF (1 << 0) | |
| 179 | #define STA_TYPE_EXPON 0 | |
| 180 | #define STA_TYPE_SFR 1 | |
| 181 | ||
| 182 | #define S5P_PWR_STA_EXP_SCALE 0 | |
| 183 | #define S5P_PWR_STA_CNT 4 | |
| 184 | ||
| 185 | #define S5P_PWR_STABLE_COUNT 85500 | |
| 186 | ||
| 187 | #define S5P_SLEEP_CFG_OSC_EN (1 << 0) | |
| 188 | #define S5P_SLEEP_CFG_USBOSC_EN (1 << 1) | |
| 189 | ||
| 190 | /* OTHERS Resgister */ | |
| 191 | #define S5P_OTHERS_USB_SIG_MASK (1 << 16) | |
| 0c1945d3 | 192 | |
| 0c1945d3 KK |
193 | /* S5P_DAC_CONTROL */ |
| 194 | #define S5P_DAC_ENABLE (1) | |
| 195 | #define S5P_DAC_DISABLE (0) | |
| 196 | ||
| 197 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |