[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-sa1100 / generic.c

/*
 * linux/arch/arm/mach-sa1100/generic.c
 *
 * Author: Nicolas Pitre
 *
 * Code common to all SA11x0 machines.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/sched.h>	/* just for sched_clock() - funny that */
#include <linux/platform_device.h>

#include <asm/div64.h>
#include <asm/hardware.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/irq.h>

#include "generic.h"

#define NR_FREQS	16

/*
 * This table is setup for a 3.6864MHz Crystal.
 */
static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
	 590,	/*  59.0 MHz */
	 737,	/*  73.7 MHz */
	 885, 	/*  88.5 MHz */
	1032,	/* 103.2 MHz */
	1180,	/* 118.0 MHz */
	1327,	/* 132.7 MHz */
	1475,	/* 147.5 MHz */
	1622,	/* 162.2 MHz */
	1769,	/* 176.9 MHz */
	1917,	/* 191.7 MHz */
	2064,	/* 206.4 MHz */
	2212,	/* 221.2 MHz */
	2359,   /* 235.9 MHz */
	2507,   /* 250.7 MHz */
	2654,   /* 265.4 MHz */
	2802    /* 280.2 MHz */
};

#if defined(CONFIG_CPU_FREQ_SA1100) || defined(CONFIG_CPU_FREQ_SA1110)
/* rounds up(!)  */
unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
{
	int i;

	khz /= 100;

	for (i = 0; i < NR_FREQS; i++)
		if (cclk_frequency_100khz[i] >= khz)
			break;

	return i;
}

unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
{
	unsigned int freq = 0;
	if (idx < NR_FREQS)
		freq = cclk_frequency_100khz[idx] * 100;
	return freq;
}


/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
 * this platform, anyway.
 */
int sa11x0_verify_speed(struct cpufreq_policy *policy)
{
	unsigned int tmp;
	if (policy->cpu)
		return -EINVAL;

	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);

	/* make sure that at least one frequency is within the policy */
	tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
	if (tmp > policy->max)
		policy->max = tmp;

	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);

	return 0;
}

unsigned int sa11x0_getspeed(unsigned int cpu)
{
	if (cpu)
		return 0;
	return cclk_frequency_100khz[PPCR & 0xf] * 100;
}

#else
/*
 * We still need to provide this so building without cpufreq works.
 */ 
unsigned int cpufreq_get(unsigned int cpu)
{
	return cclk_frequency_100khz[PPCR & 0xf] * 100;
}
EXPORT_SYMBOL(cpufreq_get);
#endif

/*
 * This is the SA11x0 sched_clock implementation.  This has
 * a resolution of 271ns, and a maximum value of 1165s.
 *  ( * 1E9 / 3686400 => * 78125 / 288)
 */
unsigned long long sched_clock(void)
{
	unsigned long long v;

	v = (unsigned long long)OSCR * 78125;
	do_div(v, 288);

	return v;
}

/*
 * Default power-off for SA1100
 */
static void sa1100_power_off(void)
{
	mdelay(100);
	local_irq_disable();
	/* disable internal oscillator, float CS lines */
	PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
	/* enable wake-up on GPIO0 (Assabet...) */
	PWER = GFER = GRER = 1;
	/*
	 * set scratchpad to zero, just in case it is used as a
	 * restart address by the bootloader.
	 */
	PSPR = 0;
	/* enter sleep mode */
	PMCR = PMCR_SF;
}

static struct resource sa11x0udc_resources[] = {
	[0] = {
		.start	= 0x80000000,
		.end	= 0x8000ffff,
		.flags	= IORESOURCE_MEM,
	},
};

static u64 sa11x0udc_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0udc_device = {
	.name		= "sa11x0-udc",
	.id		= -1,
	.dev		= {
		.dma_mask = &sa11x0udc_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0udc_resources),
	.resource	= sa11x0udc_resources,
};

static struct resource sa11x0uart1_resources[] = {
	[0] = {
		.start	= 0x80010000,
		.end	= 0x8001ffff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device sa11x0uart1_device = {
	.name		= "sa11x0-uart",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(sa11x0uart1_resources),
	.resource	= sa11x0uart1_resources,
};

static struct resource sa11x0uart3_resources[] = {
	[0] = {
		.start	= 0x80050000,
		.end	= 0x8005ffff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device sa11x0uart3_device = {
	.name		= "sa11x0-uart",
	.id		= 3,
	.num_resources	= ARRAY_SIZE(sa11x0uart3_resources),
	.resource	= sa11x0uart3_resources,
};

static struct resource sa11x0mcp_resources[] = {
	[0] = {
		.start	= 0x80060000,
		.end	= 0x8006ffff,
		.flags	= IORESOURCE_MEM,
	},
};

static u64 sa11x0mcp_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0mcp_device = {
	.name		= "sa11x0-mcp",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0mcp_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0mcp_resources),
	.resource	= sa11x0mcp_resources,
};

void sa11x0_set_mcp_data(struct mcp_plat_data *data)
{
	sa11x0mcp_device.dev.platform_data = data;
}

static struct resource sa11x0ssp_resources[] = {
	[0] = {
		.start	= 0x80070000,
		.end	= 0x8007ffff,
		.flags	= IORESOURCE_MEM,
	},
};

static u64 sa11x0ssp_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0ssp_device = {
	.name		= "sa11x0-ssp",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0ssp_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0ssp_resources),
	.resource	= sa11x0ssp_resources,
};

static struct resource sa11x0fb_resources[] = {
	[0] = {
		.start	= 0xb0100000,
		.end	= 0xb010ffff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_LCD,
		.end	= IRQ_LCD,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device sa11x0fb_device = {
	.name		= "sa11x0-fb",
	.id		= -1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0fb_resources),
	.resource	= sa11x0fb_resources,
};

static struct platform_device sa11x0pcmcia_device = {
	.name		= "sa11x0-pcmcia",
	.id		= -1,
};

static struct platform_device sa11x0mtd_device = {
	.name		= "flash",
	.id		= -1,
};

void sa11x0_set_flash_data(struct flash_platform_data *flash,
			   struct resource *res, int nr)
{
	flash->name = "sa1100";
	sa11x0mtd_device.dev.platform_data = flash;
	sa11x0mtd_device.resource = res;
	sa11x0mtd_device.num_resources = nr;
}

static struct resource sa11x0ir_resources[] = {
	{
		.start	= __PREG(Ser2UTCR0),
		.end	= __PREG(Ser2UTCR0) + 0x24 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= __PREG(Ser2HSCR0),
		.end	= __PREG(Ser2HSCR0) + 0x1c - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= __PREG(Ser2HSCR2),
		.end	= __PREG(Ser2HSCR2) + 0x04 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_Ser2ICP,
		.end	= IRQ_Ser2ICP,
		.flags	= IORESOURCE_IRQ,
	}
};

static struct platform_device sa11x0ir_device = {
	.name		= "sa11x0-ir",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sa11x0ir_resources),
	.resource	= sa11x0ir_resources,
};

void sa11x0_set_irda_data(struct irda_platform_data *irda)
{
	sa11x0ir_device.dev.platform_data = irda;
}

static struct platform_device sa11x0rtc_device = {
	.name		= "sa1100-rtc",
	.id		= -1,
};

static struct platform_device *sa11x0_devices[] __initdata = {
	&sa11x0udc_device,
	&sa11x0uart1_device,
	&sa11x0uart3_device,
	&sa11x0mcp_device,
	&sa11x0ssp_device,
	&sa11x0pcmcia_device,
	&sa11x0fb_device,
	&sa11x0mtd_device,
	&sa11x0rtc_device,
};

static int __init sa1100_init(void)
{
	pm_power_off = sa1100_power_off;

	if (sa11x0ir_device.dev.platform_data)
		platform_device_register(&sa11x0ir_device);

	return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
}

arch_initcall(sa1100_init);

void (*sa1100fb_backlight_power)(int on);
void (*sa1100fb_lcd_power)(int on);

EXPORT_SYMBOL(sa1100fb_backlight_power);
EXPORT_SYMBOL(sa1100fb_lcd_power);


/*
 * Common I/O mapping:
 *
 * Typically, static virtual address mappings are as follow:
 *
 * 0xf0000000-0xf3ffffff:	miscellaneous stuff (CPLDs, etc.)
 * 0xf4000000-0xf4ffffff:	SA-1111
 * 0xf5000000-0xf5ffffff:	reserved (used by cache flushing area)
 * 0xf6000000-0xfffeffff:	reserved (internal SA1100 IO defined above)
 * 0xffff0000-0xffff0fff:	SA1100 exception vectors
 * 0xffff2000-0xffff2fff:	Minicache copy_user_page area
 *
 * Below 0xe8000000 is reserved for vm allocation.
 *
 * The machine specific code must provide the extra mapping beside the
 * default mapping provided here.
 */

static struct map_desc standard_io_desc[] __initdata = {
  	{	/* PCM */
		.virtual	=  0xf8000000,
		.pfn		= __phys_to_pfn(0x80000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* SCM */
		.virtual	=  0xfa000000,
		.pfn		= __phys_to_pfn(0x90000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* MER */
		.virtual	=  0xfc000000,
		.pfn		= __phys_to_pfn(0xa0000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* LCD + DMA */
		.virtual	=  0xfe000000,
		.pfn		= __phys_to_pfn(0xb0000000),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	},
};

void __init sa1100_map_io(void)
{
	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
}

/*
 * Disable the memory bus request/grant signals on the SA1110 to
 * ensure that we don't receive spurious memory requests.  We set
 * the MBGNT signal false to ensure the SA1111 doesn't own the
 * SDRAM bus.
 */
void __init sa1110_mb_disable(void)
{
	unsigned long flags;

	local_irq_save(flags);
	
	PGSR &= ~GPIO_MBGNT;
	GPCR = GPIO_MBGNT;
	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;

	GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);

	local_irq_restore(flags);
}

/*
 * If the system is going to use the SA-1111 DMA engines, set up
 * the memory bus request/grant pins.
 */
void __init sa1110_mb_enable(void)
{
	unsigned long flags;

	local_irq_save(flags);

	PGSR &= ~GPIO_MBGNT;
	GPCR = GPIO_MBGNT;
	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;

	GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
	TUCR |= TUCR_MR;

	local_irq_restore(flags);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/generic.c
	3	*
	4	* Author: Nicolas Pitre
	5	*
	6	* Code common to all SA11x0 machines.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
1da177e4 LT	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/delay.h>
	16	#include <linux/pm.h>
	17	#include <linux/cpufreq.h>
	18	#include <linux/ioport.h>
4e57b681	19	#include <linux/sched.h> /* just for sched_clock() - funny that */
d052d1be	20	#include <linux/platform_device.h>
1da177e4 LT	21
	22	#include <asm/div64.h>
	23	#include <asm/hardware.h>
	24	#include <asm/system.h>
	25	#include <asm/pgtable.h>
	26	#include <asm/mach/map.h>
14e66f76	27	#include <asm/mach/flash.h>
1da177e4 LT	28	#include <asm/irq.h>
	29
	30	#include "generic.h"
	31
	32	#define NR_FREQS 16
	33
	34	/*
	35	* This table is setup for a 3.6864MHz Crystal.
	36	*/
	37	static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
	38	590, /* 59.0 MHz */
	39	737, /* 73.7 MHz */
	40	885, /* 88.5 MHz */
	41	1032, /* 103.2 MHz */
	42	1180, /* 118.0 MHz */
	43	1327, /* 132.7 MHz */
	44	1475, /* 147.5 MHz */
	45	1622, /* 162.2 MHz */
	46	1769, /* 176.9 MHz */
	47	1917, /* 191.7 MHz */
	48	2064, /* 206.4 MHz */
	49	2212, /* 221.2 MHz */
	50	2359, /* 235.9 MHz */
	51	2507, /* 250.7 MHz */
	52	2654, /* 265.4 MHz */
	53	2802 /* 280.2 MHz */
	54	};
	55
	56	#if defined(CONFIG_CPU_FREQ_SA1100) \|\| defined(CONFIG_CPU_FREQ_SA1110)
	57	/* rounds up(!) */
	58	unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
	59	{
	60	int i;
	61
	62	khz /= 100;
	63
	64	for (i = 0; i < NR_FREQS; i++)
	65	if (cclk_frequency_100khz[i] >= khz)
	66	break;
	67
	68	return i;
	69	}
	70
	71	unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
	72	{
	73	unsigned int freq = 0;
	74	if (idx < NR_FREQS)
	75	freq = cclk_frequency_100khz[idx] * 100;
	76	return freq;
	77	}
	78
	79
	80	/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
	81	* this platform, anyway.
	82	*/
	83	int sa11x0_verify_speed(struct cpufreq_policy *policy)
	84	{
	85	unsigned int tmp;
	86	if (policy->cpu)
	87	return -EINVAL;
	88
	89	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
	90
	91	/* make sure that at least one frequency is within the policy */
92	tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
93	if (tmp > policy->max)
94	policy->max = tmp;
95
96	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
97
98	return 0;
99	}
100
101	unsigned int sa11x0_getspeed(unsigned int cpu)
102	{
103	if (cpu)
104	return 0;
105	return cclk_frequency_100khz[PPCR & 0xf] * 100;
106	}
107
108	#else
109	/*
110	* We still need to provide this so building without cpufreq works.
111	*/
112	unsigned int cpufreq_get(unsigned int cpu)
113	{
114	return cclk_frequency_100khz[PPCR & 0xf] * 100;
115	}
116	EXPORT_SYMBOL(cpufreq_get);
117	#endif
118
119	/*
120	* This is the SA11x0 sched_clock implementation. This has
121	* a resolution of 271ns, and a maximum value of 1165s.
122	* ( * 1E9 / 3686400 => * 78125 / 288)
123	*/
124	unsigned long long sched_clock(void)
125	{
126	unsigned long long v;
127
128	v = (unsigned long long)OSCR * 78125;
129	do_div(v, 288);
130
131	return v;
132	}
133
134	/*
135	* Default power-off for SA1100
136	*/
137	static void sa1100_power_off(void)
138	{
139	mdelay(100);
140	local_irq_disable();
141	/* disable internal oscillator, float CS lines */
142	PCFR = (PCFR_OPDE \| PCFR_FP \| PCFR_FS);
143	/* enable wake-up on GPIO0 (Assabet...) */
144	PWER = GFER = GRER = 1;
145	/*
146	* set scratchpad to zero, just in case it is used as a
147	* restart address by the bootloader.
148	*/
149	PSPR = 0;
150	/* enter sleep mode */
151	PMCR = PMCR_SF;
152	}
153
154	static struct resource sa11x0udc_resources[] = {
155	[0] = {
156	.start = 0x80000000,
157	.end = 0x8000ffff,
158	.flags = IORESOURCE_MEM,
159	},
160	};
161
162	static u64 sa11x0udc_dma_mask = 0xffffffffUL;
163
164	static struct platform_device sa11x0udc_device = {
165	.name = "sa11x0-udc",
166	.id = -1,
167	.dev = {
168	.dma_mask = &sa11x0udc_dma_mask,
169	.coherent_dma_mask = 0xffffffff,
170	},
171	.num_resources = ARRAY_SIZE(sa11x0udc_resources),
172	.resource = sa11x0udc_resources,
173	};
174
175	static struct resource sa11x0uart1_resources[] = {
176	[0] = {
177	.start = 0x80010000,
178	.end = 0x8001ffff,
179	.flags = IORESOURCE_MEM,
180	},
181	};
182
183	static struct platform_device sa11x0uart1_device = {
184	.name = "sa11x0-uart",
185	.id = 1,
186	.num_resources = ARRAY_SIZE(sa11x0uart1_resources),
187	.resource = sa11x0uart1_resources,
188	};
189
190	static struct resource sa11x0uart3_resources[] = {
191	[0] = {
192	.start = 0x80050000,
193	.end = 0x8005ffff,
194	.flags = IORESOURCE_MEM,
195	},
196	};
197
198	static struct platform_device sa11x0uart3_device = {
199	.name = "sa11x0-uart",
200	.id = 3,
201	.num_resources = ARRAY_SIZE(sa11x0uart3_resources),
202	.resource = sa11x0uart3_resources,
203	};
204
205	static struct resource sa11x0mcp_resources[] = {
206	[0] = {
207	.start = 0x80060000,
208	.end = 0x8006ffff,
209	.flags = IORESOURCE_MEM,
210	},
211	};
212
213	static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
214
215	static struct platform_device sa11x0mcp_device = {
216	.name = "sa11x0-mcp",
217	.id = -1,
218	.dev = {
219	.dma_mask = &sa11x0mcp_dma_mask,
220	.coherent_dma_mask = 0xffffffff,
221	},
222	.num_resources = ARRAY_SIZE(sa11x0mcp_resources),
223	.resource = sa11x0mcp_resources,
224	};
225
323cdfc1 RK	226	void sa11x0_set_mcp_data(struct mcp_plat_data *data)
	227	{
	228	sa11x0mcp_device.dev.platform_data = data;
	229	}
	230
1da177e4 LT	231	static struct resource sa11x0ssp_resources[] = {
	232	[0] = {
	233	.start = 0x80070000,
	234	.end = 0x8007ffff,
	235	.flags = IORESOURCE_MEM,
	236	},
	237	};
	238
	239	static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
	240
	241	static struct platform_device sa11x0ssp_device = {
	242	.name = "sa11x0-ssp",
	243	.id = -1,
	244	.dev = {
	245	.dma_mask = &sa11x0ssp_dma_mask,
	246	.coherent_dma_mask = 0xffffffff,
	247	},
	248	.num_resources = ARRAY_SIZE(sa11x0ssp_resources),
	249	.resource = sa11x0ssp_resources,
	250	};
	251
	252	static struct resource sa11x0fb_resources[] = {
	253	[0] = {
	254	.start = 0xb0100000,
	255	.end = 0xb010ffff,
	256	.flags = IORESOURCE_MEM,
	257	},
	258	[1] = {
	259	.start = IRQ_LCD,
	260	.end = IRQ_LCD,
	261	.flags = IORESOURCE_IRQ,
	262	},
	263	};
	264
	265	static struct platform_device sa11x0fb_device = {
	266	.name = "sa11x0-fb",
	267	.id = -1,
	268	.dev = {
	269	.coherent_dma_mask = 0xffffffff,
	270	},
	271	.num_resources = ARRAY_SIZE(sa11x0fb_resources),
	272	.resource = sa11x0fb_resources,
	273	};
	274
	275	static struct platform_device sa11x0pcmcia_device = {
	276	.name = "sa11x0-pcmcia",
	277	.id = -1,
	278	};
	279
	280	static struct platform_device sa11x0mtd_device = {
	281	.name = "flash",
	282	.id = -1,
	283	};
	284
	285	void sa11x0_set_flash_data(struct flash_platform_data *flash,
	286	struct resource *res, int nr)
	287	{
14e66f76	288	flash->name = "sa1100";
1da177e4 LT	289	sa11x0mtd_device.dev.platform_data = flash;
	290	sa11x0mtd_device.resource = res;
	291	sa11x0mtd_device.num_resources = nr;
	292	}
	293
	294	static struct resource sa11x0ir_resources[] = {
	295	{
	296	.start = __PREG(Ser2UTCR0),
	297	.end = __PREG(Ser2UTCR0) + 0x24 - 1,
	298	.flags = IORESOURCE_MEM,
	299	}, {
	300	.start = __PREG(Ser2HSCR0),
	301	.end = __PREG(Ser2HSCR0) + 0x1c - 1,
	302	.flags = IORESOURCE_MEM,
	303	}, {
	304	.start = __PREG(Ser2HSCR2),
	305	.end = __PREG(Ser2HSCR2) + 0x04 - 1,
	306	.flags = IORESOURCE_MEM,
	307	}, {
	308	.start = IRQ_Ser2ICP,
	309	.end = IRQ_Ser2ICP,
	310	.flags = IORESOURCE_IRQ,
	311	}
	312	};
	313
	314	static struct platform_device sa11x0ir_device = {
	315	.name = "sa11x0-ir",
	316	.id = -1,
	317	.num_resources = ARRAY_SIZE(sa11x0ir_resources),
	318	.resource = sa11x0ir_resources,
	319	};
	320
	321	void sa11x0_set_irda_data(struct irda_platform_data *irda)
	322	{
	323	sa11x0ir_device.dev.platform_data = irda;
	324	}
	325
e842f1c8 RP	326	static struct platform_device sa11x0rtc_device = {
	327	.name = "sa1100-rtc",
	328	.id = -1,
	329	};
	330
1da177e4 LT	331	static struct platform_device *sa11x0_devices[] __initdata = {
	332	&sa11x0udc_device,
	333	&sa11x0uart1_device,
	334	&sa11x0uart3_device,
	335	&sa11x0mcp_device,
	336	&sa11x0ssp_device,
	337	&sa11x0pcmcia_device,
	338	&sa11x0fb_device,
	339	&sa11x0mtd_device,
e842f1c8	340	&sa11x0rtc_device,
1da177e4 LT	341	};
	342
	343	static int __init sa1100_init(void)
	344	{
	345	pm_power_off = sa1100_power_off;
	346
	347	if (sa11x0ir_device.dev.platform_data)
	348	platform_device_register(&sa11x0ir_device);
	349
	350	return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
	351	}
	352
	353	arch_initcall(sa1100_init);
	354
	355	void (*sa1100fb_backlight_power)(int on);
	356	void (*sa1100fb_lcd_power)(int on);
	357
	358	EXPORT_SYMBOL(sa1100fb_backlight_power);
	359	EXPORT_SYMBOL(sa1100fb_lcd_power);
	360
	361
	362	/*
	363	* Common I/O mapping:
	364	*
	365	* Typically, static virtual address mappings are as follow:
	366	*
	367	* 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
	368	* 0xf4000000-0xf4ffffff: SA-1111
	369	* 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
	370	* 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
	371	* 0xffff0000-0xffff0fff: SA1100 exception vectors
	372	* 0xffff2000-0xffff2fff: Minicache copy_user_page area
	373	*
	374	* Below 0xe8000000 is reserved for vm allocation.
	375	*
	376	* The machine specific code must provide the extra mapping beside the
	377	* default mapping provided here.
	378	*/
	379
	380	static struct map_desc standard_io_desc[] __initdata = {
92519d82 DS	381	{ /* PCM */
	382	.virtual = 0xf8000000,
	383	.pfn = __phys_to_pfn(0x80000000),
	384	.length = 0x00100000,
	385	.type = MT_DEVICE
	386	}, { /* SCM */
	387	.virtual = 0xfa000000,
	388	.pfn = __phys_to_pfn(0x90000000),
	389	.length = 0x00100000,
	390	.type = MT_DEVICE
	391	}, { /* MER */
	392	.virtual = 0xfc000000,
	393	.pfn = __phys_to_pfn(0xa0000000),
	394	.length = 0x00100000,
	395	.type = MT_DEVICE
	396	}, { /* LCD + DMA */
	397	.virtual = 0xfe000000,
	398	.pfn = __phys_to_pfn(0xb0000000),
	399	.length = 0x00200000,
	400	.type = MT_DEVICE
	401	},
1da177e4 LT	402	};
	403
	404	void __init sa1100_map_io(void)
	405	{
	406	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
	407	}
	408
	409	/*
	410	* Disable the memory bus request/grant signals on the SA1110 to
	411	* ensure that we don't receive spurious memory requests. We set
	412	* the MBGNT signal false to ensure the SA1111 doesn't own the
	413	* SDRAM bus.
	414	*/
	415	void __init sa1110_mb_disable(void)
	416	{
	417	unsigned long flags;
	418
	419	local_irq_save(flags);
	420
	421	PGSR &= ~GPIO_MBGNT;
	422	GPCR = GPIO_MBGNT;
	423	GPDR = (GPDR & ~GPIO_MBREQ) \| GPIO_MBGNT;
	424
	425	GAFR &= ~(GPIO_MBGNT \| GPIO_MBREQ);
	426
	427	local_irq_restore(flags);
	428	}
	429
	430	/*
	431	* If the system is going to use the SA-1111 DMA engines, set up
	432	* the memory bus request/grant pins.
	433	*/
	434	void __init sa1110_mb_enable(void)
	435	{
	436	unsigned long flags;
	437
	438	local_irq_save(flags);
	439
	440	PGSR &= ~GPIO_MBGNT;
	441	GPCR = GPIO_MBGNT;
	442	GPDR = (GPDR & ~GPIO_MBREQ) \| GPIO_MBGNT;
	443
	444	GAFR \|= (GPIO_MBGNT \| GPIO_MBREQ);
	445	TUCR \|= TUCR_MR;
	446
	447	local_irq_restore(flags);
	448	}
	449