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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-sa1100/irq.c | |
3 | * | |
4 | * Copyright (C) 1999-2001 Nicolas Pitre | |
5 | * | |
6 | * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
119c641c | 14 | #include <linux/interrupt.h> |
3169663a | 15 | #include <linux/io.h> |
119c641c | 16 | #include <linux/irq.h> |
1eca42b4 | 17 | #include <linux/irqdomain.h> |
1da177e4 | 18 | #include <linux/ioport.h> |
90533980 | 19 | #include <linux/syscore_ops.h> |
1da177e4 | 20 | |
a657d7f6 DES |
21 | #include <soc/sa1100/pwer.h> |
22 | ||
f314f33b | 23 | #include <mach/irqs.h> |
affcab32 | 24 | #include <asm/exception.h> |
1da177e4 LT |
25 | |
26 | #include "generic.h" | |
27 | ||
60c06c4c DES |
28 | #define ICIP 0x00 /* IC IRQ Pending reg. */ |
29 | #define ICMR 0x04 /* IC Mask Reg. */ | |
30 | #define ICLR 0x08 /* IC Level Reg. */ | |
31 | #define ICCR 0x0C /* IC Control Reg. */ | |
32 | #define ICFP 0x10 /* IC FIQ Pending reg. */ | |
33 | #define ICPR 0x20 /* IC Pending Reg. */ | |
34 | ||
35 | static void __iomem *iobase; | |
1da177e4 | 36 | |
ab71f99f DES |
37 | /* |
38 | * We don't need to ACK IRQs on the SA1100 unless they're GPIOs | |
39 | * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm. | |
40 | */ | |
41 | static void sa1100_mask_irq(struct irq_data *d) | |
42 | { | |
60c06c4c DES |
43 | u32 reg; |
44 | ||
45 | reg = readl_relaxed(iobase + ICMR); | |
46 | reg &= ~BIT(d->hwirq); | |
47 | writel_relaxed(reg, iobase + ICMR); | |
ab71f99f DES |
48 | } |
49 | ||
50 | static void sa1100_unmask_irq(struct irq_data *d) | |
51 | { | |
60c06c4c DES |
52 | u32 reg; |
53 | ||
54 | reg = readl_relaxed(iobase + ICMR); | |
55 | reg |= BIT(d->hwirq); | |
56 | writel_relaxed(reg, iobase + ICMR); | |
ab71f99f DES |
57 | } |
58 | ||
ab71f99f DES |
59 | static int sa1100_set_wake(struct irq_data *d, unsigned int on) |
60 | { | |
a657d7f6 | 61 | return sa11x0_sc_set_wake(d->hwirq, on); |
ab71f99f DES |
62 | } |
63 | ||
64 | static struct irq_chip sa1100_normal_chip = { | |
65 | .name = "SC", | |
66 | .irq_ack = sa1100_mask_irq, | |
67 | .irq_mask = sa1100_mask_irq, | |
68 | .irq_unmask = sa1100_unmask_irq, | |
69 | .irq_set_wake = sa1100_set_wake, | |
70 | }; | |
71 | ||
72 | static int sa1100_normal_irqdomain_map(struct irq_domain *d, | |
73 | unsigned int irq, irq_hw_number_t hwirq) | |
74 | { | |
75 | irq_set_chip_and_handler(irq, &sa1100_normal_chip, | |
76 | handle_level_irq); | |
77 | set_irq_flags(irq, IRQF_VALID); | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
82 | static struct irq_domain_ops sa1100_normal_irqdomain_ops = { | |
83 | .map = sa1100_normal_irqdomain_map, | |
84 | .xlate = irq_domain_xlate_onetwocell, | |
85 | }; | |
86 | ||
87 | static struct irq_domain *sa1100_normal_irqdomain; | |
88 | ||
a181099e RK |
89 | static struct resource irq_resource = |
90 | DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); | |
1da177e4 LT |
91 | |
92 | static struct sa1100irq_state { | |
93 | unsigned int saved; | |
94 | unsigned int icmr; | |
95 | unsigned int iclr; | |
96 | unsigned int iccr; | |
97 | } sa1100irq_state; | |
98 | ||
90533980 | 99 | static int sa1100irq_suspend(void) |
1da177e4 LT |
100 | { |
101 | struct sa1100irq_state *st = &sa1100irq_state; | |
102 | ||
103 | st->saved = 1; | |
60c06c4c DES |
104 | st->icmr = readl_relaxed(iobase + ICMR); |
105 | st->iclr = readl_relaxed(iobase + ICLR); | |
106 | st->iccr = readl_relaxed(iobase + ICCR); | |
1da177e4 LT |
107 | |
108 | /* | |
109 | * Disable all GPIO-based interrupts. | |
110 | */ | |
60c06c4c | 111 | writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); |
1da177e4 | 112 | |
1da177e4 LT |
113 | return 0; |
114 | } | |
115 | ||
90533980 | 116 | static void sa1100irq_resume(void) |
1da177e4 LT |
117 | { |
118 | struct sa1100irq_state *st = &sa1100irq_state; | |
119 | ||
120 | if (st->saved) { | |
60c06c4c DES |
121 | writel_relaxed(st->iccr, iobase + ICCR); |
122 | writel_relaxed(st->iclr, iobase + ICLR); | |
1da177e4 | 123 | |
60c06c4c | 124 | writel_relaxed(st->icmr, iobase + ICMR); |
1da177e4 | 125 | } |
1da177e4 LT |
126 | } |
127 | ||
90533980 | 128 | static struct syscore_ops sa1100irq_syscore_ops = { |
1da177e4 LT |
129 | .suspend = sa1100irq_suspend, |
130 | .resume = sa1100irq_resume, | |
131 | }; | |
132 | ||
1da177e4 LT |
133 | static int __init sa1100irq_init_devicefs(void) |
134 | { | |
90533980 RW |
135 | register_syscore_ops(&sa1100irq_syscore_ops); |
136 | return 0; | |
1da177e4 LT |
137 | } |
138 | ||
139 | device_initcall(sa1100irq_init_devicefs); | |
140 | ||
affcab32 DES |
141 | static asmlinkage void __exception_irq_entry |
142 | sa1100_handle_irq(struct pt_regs *regs) | |
143 | { | |
144 | uint32_t icip, icmr, mask; | |
145 | ||
146 | do { | |
60c06c4c DES |
147 | icip = readl_relaxed(iobase + ICIP); |
148 | icmr = readl_relaxed(iobase + ICMR); | |
affcab32 DES |
149 | mask = icip & icmr; |
150 | ||
151 | if (mask == 0) | |
152 | break; | |
153 | ||
364e3869 DES |
154 | handle_domain_irq(sa1100_normal_irqdomain, |
155 | ffs(mask) - 1, regs); | |
affcab32 DES |
156 | } while (1); |
157 | } | |
158 | ||
1da177e4 LT |
159 | void __init sa1100_init_irq(void) |
160 | { | |
1da177e4 LT |
161 | request_resource(&iomem_resource, &irq_resource); |
162 | ||
60c06c4c DES |
163 | iobase = ioremap(irq_resource.start, SZ_64K); |
164 | if (WARN_ON(!iobase)) | |
165 | return; | |
166 | ||
1da177e4 | 167 | /* disable all IRQs */ |
60c06c4c | 168 | writel_relaxed(0, iobase + ICMR); |
1da177e4 LT |
169 | |
170 | /* all IRQs are IRQ, not FIQ */ | |
60c06c4c | 171 | writel_relaxed(0, iobase + ICLR); |
1da177e4 | 172 | |
1da177e4 LT |
173 | /* |
174 | * Whatever the doc says, this has to be set for the wait-on-irq | |
175 | * instruction to work... on a SA1100 rev 9 at least. | |
176 | */ | |
60c06c4c | 177 | writel_relaxed(1, iobase + ICCR); |
1da177e4 | 178 | |
a82be3f0 DES |
179 | sa1100_normal_irqdomain = irq_domain_add_simple(NULL, |
180 | 32, IRQ_GPIO0_SC, | |
83508093 DES |
181 | &sa1100_normal_irqdomain_ops, NULL); |
182 | ||
affcab32 DES |
183 | set_handle_irq(sa1100_handle_irq); |
184 | ||
45528e38 | 185 | sa1100_init_gpio(); |
1da177e4 | 186 | } |