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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-sa1100/irq.c | |
3 | * | |
4 | * Copyright (C) 1999-2001 Nicolas Pitre | |
5 | * | |
6 | * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
119c641c TG |
14 | #include <linux/interrupt.h> |
15 | #include <linux/irq.h> | |
1da177e4 LT |
16 | #include <linux/ioport.h> |
17 | #include <linux/ptrace.h> | |
18 | #include <linux/sysdev.h> | |
19 | ||
20 | #include <asm/hardware.h> | |
1da177e4 LT |
21 | #include <asm/mach/irq.h> |
22 | ||
23 | #include "generic.h" | |
24 | ||
25 | ||
26 | /* | |
27 | * SA1100 GPIO edge detection for IRQs: | |
28 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | |
29 | * Use this instead of directly setting GRER/GFER. | |
30 | */ | |
31 | static int GPIO_IRQ_rising_edge; | |
32 | static int GPIO_IRQ_falling_edge; | |
33 | static int GPIO_IRQ_mask = (1 << 11) - 1; | |
34 | ||
35 | /* | |
36 | * To get the GPIO number from an IRQ number | |
37 | */ | |
38 | #define GPIO_11_27_IRQ(i) ((i) - 21) | |
39 | #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq)) | |
40 | ||
41 | static int sa1100_gpio_type(unsigned int irq, unsigned int type) | |
42 | { | |
43 | unsigned int mask; | |
44 | ||
45 | if (irq <= 10) | |
46 | mask = 1 << irq; | |
47 | else | |
48 | mask = GPIO11_27_MASK(irq); | |
49 | ||
50 | if (type == IRQT_PROBE) { | |
51 | if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) | |
52 | return 0; | |
53 | type = __IRQT_RISEDGE | __IRQT_FALEDGE; | |
54 | } | |
55 | ||
56 | if (type & __IRQT_RISEDGE) { | |
57 | GPIO_IRQ_rising_edge |= mask; | |
58 | } else | |
59 | GPIO_IRQ_rising_edge &= ~mask; | |
60 | if (type & __IRQT_FALEDGE) { | |
61 | GPIO_IRQ_falling_edge |= mask; | |
62 | } else | |
63 | GPIO_IRQ_falling_edge &= ~mask; | |
64 | ||
65 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
66 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
71 | /* | |
72 | * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10. | |
73 | */ | |
74 | static void sa1100_low_gpio_ack(unsigned int irq) | |
75 | { | |
76 | GEDR = (1 << irq); | |
77 | } | |
78 | ||
79 | static void sa1100_low_gpio_mask(unsigned int irq) | |
80 | { | |
81 | ICMR &= ~(1 << irq); | |
82 | } | |
83 | ||
84 | static void sa1100_low_gpio_unmask(unsigned int irq) | |
85 | { | |
86 | ICMR |= 1 << irq; | |
87 | } | |
88 | ||
89 | static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on) | |
90 | { | |
91 | if (on) | |
92 | PWER |= 1 << irq; | |
93 | else | |
94 | PWER &= ~(1 << irq); | |
95 | return 0; | |
96 | } | |
97 | ||
38c677cb DB |
98 | static struct irq_chip sa1100_low_gpio_chip = { |
99 | .name = "GPIO-l", | |
1da177e4 LT |
100 | .ack = sa1100_low_gpio_ack, |
101 | .mask = sa1100_low_gpio_mask, | |
102 | .unmask = sa1100_low_gpio_unmask, | |
7801907b RK |
103 | .set_type = sa1100_gpio_type, |
104 | .set_wake = sa1100_low_gpio_wake, | |
1da177e4 LT |
105 | }; |
106 | ||
107 | /* | |
108 | * IRQ11 (GPIO11 through 27) handler. We enter here with the | |
109 | * irq_controller_lock held, and IRQs disabled. Decode the IRQ | |
110 | * and call the handler. | |
111 | */ | |
112 | static void | |
113 | sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc, | |
114 | struct pt_regs *regs) | |
115 | { | |
116 | unsigned int mask; | |
117 | ||
118 | mask = GEDR & 0xfffff800; | |
119 | do { | |
120 | /* | |
121 | * clear down all currently active IRQ sources. | |
122 | * We will be processing them all. | |
123 | */ | |
124 | GEDR = mask; | |
125 | ||
126 | irq = IRQ_GPIO11; | |
127 | desc = irq_desc + irq; | |
128 | mask >>= 11; | |
129 | do { | |
130 | if (mask & 1) | |
664399e1 | 131 | desc_handle_irq(irq, desc, regs); |
1da177e4 LT |
132 | mask >>= 1; |
133 | irq++; | |
134 | desc++; | |
135 | } while (mask); | |
136 | ||
137 | mask = GEDR & 0xfffff800; | |
138 | } while (mask); | |
139 | } | |
140 | ||
141 | /* | |
142 | * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially. | |
143 | * In addition, the IRQs are all collected up into one bit in the | |
144 | * interrupt controller registers. | |
145 | */ | |
146 | static void sa1100_high_gpio_ack(unsigned int irq) | |
147 | { | |
148 | unsigned int mask = GPIO11_27_MASK(irq); | |
149 | ||
150 | GEDR = mask; | |
151 | } | |
152 | ||
153 | static void sa1100_high_gpio_mask(unsigned int irq) | |
154 | { | |
155 | unsigned int mask = GPIO11_27_MASK(irq); | |
156 | ||
157 | GPIO_IRQ_mask &= ~mask; | |
158 | ||
159 | GRER &= ~mask; | |
160 | GFER &= ~mask; | |
161 | } | |
162 | ||
163 | static void sa1100_high_gpio_unmask(unsigned int irq) | |
164 | { | |
165 | unsigned int mask = GPIO11_27_MASK(irq); | |
166 | ||
167 | GPIO_IRQ_mask |= mask; | |
168 | ||
169 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
170 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
171 | } | |
172 | ||
173 | static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on) | |
174 | { | |
175 | if (on) | |
176 | PWER |= GPIO11_27_MASK(irq); | |
177 | else | |
178 | PWER &= ~GPIO11_27_MASK(irq); | |
179 | return 0; | |
180 | } | |
181 | ||
38c677cb DB |
182 | static struct irq_chip sa1100_high_gpio_chip = { |
183 | .name = "GPIO-h", | |
1da177e4 LT |
184 | .ack = sa1100_high_gpio_ack, |
185 | .mask = sa1100_high_gpio_mask, | |
186 | .unmask = sa1100_high_gpio_unmask, | |
7801907b RK |
187 | .set_type = sa1100_gpio_type, |
188 | .set_wake = sa1100_high_gpio_wake, | |
1da177e4 LT |
189 | }; |
190 | ||
191 | /* | |
192 | * We don't need to ACK IRQs on the SA1100 unless they're GPIOs | |
193 | * this is for internal IRQs i.e. from 11 to 31. | |
194 | */ | |
195 | static void sa1100_mask_irq(unsigned int irq) | |
196 | { | |
197 | ICMR &= ~(1 << irq); | |
198 | } | |
199 | ||
200 | static void sa1100_unmask_irq(unsigned int irq) | |
201 | { | |
202 | ICMR |= (1 << irq); | |
203 | } | |
204 | ||
19ca5d27 RK |
205 | /* |
206 | * Apart form GPIOs, only the RTC alarm can be a wakeup event. | |
207 | */ | |
208 | static int sa1100_set_wake(unsigned int irq, unsigned int on) | |
209 | { | |
210 | if (irq == IRQ_RTCAlrm) { | |
211 | if (on) | |
212 | PWER |= PWER_RTC; | |
213 | else | |
214 | PWER &= ~PWER_RTC; | |
215 | return 0; | |
216 | } | |
217 | return -EINVAL; | |
218 | } | |
219 | ||
38c677cb DB |
220 | static struct irq_chip sa1100_normal_chip = { |
221 | .name = "SC", | |
1da177e4 LT |
222 | .ack = sa1100_mask_irq, |
223 | .mask = sa1100_mask_irq, | |
224 | .unmask = sa1100_unmask_irq, | |
19ca5d27 | 225 | .set_wake = sa1100_set_wake, |
1da177e4 LT |
226 | }; |
227 | ||
228 | static struct resource irq_resource = { | |
229 | .name = "irqs", | |
230 | .start = 0x90050000, | |
231 | .end = 0x9005ffff, | |
232 | }; | |
233 | ||
234 | static struct sa1100irq_state { | |
235 | unsigned int saved; | |
236 | unsigned int icmr; | |
237 | unsigned int iclr; | |
238 | unsigned int iccr; | |
239 | } sa1100irq_state; | |
240 | ||
241 | static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state) | |
242 | { | |
243 | struct sa1100irq_state *st = &sa1100irq_state; | |
244 | ||
245 | st->saved = 1; | |
246 | st->icmr = ICMR; | |
247 | st->iclr = ICLR; | |
248 | st->iccr = ICCR; | |
249 | ||
250 | /* | |
251 | * Disable all GPIO-based interrupts. | |
252 | */ | |
253 | ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7| | |
254 | IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2| | |
255 | IC_GPIO1|IC_GPIO0); | |
256 | ||
257 | /* | |
258 | * Set the appropriate edges for wakeup. | |
259 | */ | |
260 | GRER = PWER & GPIO_IRQ_rising_edge; | |
261 | GFER = PWER & GPIO_IRQ_falling_edge; | |
262 | ||
263 | /* | |
264 | * Clear any pending GPIO interrupts. | |
265 | */ | |
266 | GEDR = GEDR; | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static int sa1100irq_resume(struct sys_device *dev) | |
272 | { | |
273 | struct sa1100irq_state *st = &sa1100irq_state; | |
274 | ||
275 | if (st->saved) { | |
276 | ICCR = st->iccr; | |
277 | ICLR = st->iclr; | |
278 | ||
279 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
280 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
281 | ||
282 | ICMR = st->icmr; | |
283 | } | |
284 | return 0; | |
285 | } | |
286 | ||
287 | static struct sysdev_class sa1100irq_sysclass = { | |
288 | set_kset_name("sa11x0-irq"), | |
289 | .suspend = sa1100irq_suspend, | |
290 | .resume = sa1100irq_resume, | |
291 | }; | |
292 | ||
293 | static struct sys_device sa1100irq_device = { | |
294 | .id = 0, | |
295 | .cls = &sa1100irq_sysclass, | |
296 | }; | |
297 | ||
298 | static int __init sa1100irq_init_devicefs(void) | |
299 | { | |
300 | sysdev_class_register(&sa1100irq_sysclass); | |
301 | return sysdev_register(&sa1100irq_device); | |
302 | } | |
303 | ||
304 | device_initcall(sa1100irq_init_devicefs); | |
305 | ||
306 | void __init sa1100_init_irq(void) | |
307 | { | |
308 | unsigned int irq; | |
309 | ||
310 | request_resource(&iomem_resource, &irq_resource); | |
311 | ||
312 | /* disable all IRQs */ | |
313 | ICMR = 0; | |
314 | ||
315 | /* all IRQs are IRQ, not FIQ */ | |
316 | ICLR = 0; | |
317 | ||
318 | /* clear all GPIO edge detects */ | |
319 | GFER = 0; | |
320 | GRER = 0; | |
321 | GEDR = -1; | |
322 | ||
323 | /* | |
324 | * Whatever the doc says, this has to be set for the wait-on-irq | |
325 | * instruction to work... on a SA1100 rev 9 at least. | |
326 | */ | |
327 | ICCR = 1; | |
328 | ||
329 | for (irq = 0; irq <= 10; irq++) { | |
330 | set_irq_chip(irq, &sa1100_low_gpio_chip); | |
331 | set_irq_handler(irq, do_edge_IRQ); | |
332 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
333 | } | |
334 | ||
335 | for (irq = 12; irq <= 31; irq++) { | |
336 | set_irq_chip(irq, &sa1100_normal_chip); | |
337 | set_irq_handler(irq, do_level_IRQ); | |
338 | set_irq_flags(irq, IRQF_VALID); | |
339 | } | |
340 | ||
341 | for (irq = 32; irq <= 48; irq++) { | |
342 | set_irq_chip(irq, &sa1100_high_gpio_chip); | |
343 | set_irq_handler(irq, do_edge_IRQ); | |
344 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
345 | } | |
346 | ||
347 | /* | |
348 | * Install handler for GPIO 11-27 edge detect interrupts | |
349 | */ | |
350 | set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); | |
351 | set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); | |
352 | } |