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2b7eda63
MD		 1/*
2 * AP4EVB board support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
8eda2f21 20#include <linux/clk.h>
2b7eda63
MD		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
410d878b 27#include <linux/mfd/tmio.h>
341291a6 28#include <linux/mmc/host.h>
17e75d82 29#include <linux/mmc/sh_mobile_sdhi.h>
2b7eda63
MD		 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/physmap.h>
c8ee3d4b 33#include <linux/mmc/sh_mmcif.h>
91cf5082
KM		 34#include <linux/i2c.h>
35#include <linux/i2c/tsc2007.h>
2b7eda63 36#include <linux/io.h>
8778b8f4
GL		 37#include <linux/regulator/fixed.h>
38#include <linux/regulator/machine.h>
1b7e0677 39#include <linux/smsc911x.h>
cb9215e1
KM		 40#include <linux/sh_intc.h>
41#include <linux/sh_clk.h>
1b7e0677 42#include <linux/gpio.h>
17ccb834 43#include <linux/input.h>
2863e935 44#include <linux/leds.h>
17ccb834 45#include <linux/input/sh_keysc.h>
fb54d268 46#include <linux/usb/r8a66597.h>
b5e8d269 47#include <linux/pm_clock.h>
9b742024 48#include <linux/dma-mapping.h>
8eda2f21 49
1a0b1eac
GL		 50#include <media/sh_mobile_ceu.h>
51#include <media/sh_mobile_csi2.h>
52#include <media/soc_camera.h>
53
cb9215e1 54#include <sound/sh_fsi.h>
af8a2fe1 55#include <sound/simple_card.h>
cb9215e1 56
dfbcdf64 57#include <video/sh_mobile_hdmi.h>
8eda2f21
GL		 58#include <video/sh_mobile_lcdc.h>
59#include <video/sh_mipi_dsi.h>
60
2b7eda63 61#include <mach/common.h>
8eda2f21 62#include <mach/irqs.h>
1b7e0677 63#include <mach/sh7372.h>
8eda2f21 64
2b7eda63
MD		 65#include <asm/mach-types.h>
66#include <asm/mach/arch.h>
3d09fbcd 67#include <asm/setup.h>
2b7eda63 68
66791859
RH		 69#include "sh-gpio.h"
70
02624a17
KM		 71/*
72 * Address Interface BusWidth note
73 * ------------------------------------------------------------------
74 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
75 * 0x0800_0000 user area -
76 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
77 * 0x1400_0000 Ether (LAN9220) 16bit
78 * 0x1600_0000 user area - cannot use with NAND
79 * 0x1800_0000 user area -
80 * 0x1A00_0000 -
81 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
82 */
83
84/*
85 * NOR Flash ROM
86 *
87 * SW1 | SW2 | SW7 | NOR Flash ROM
88 * bit1 | bit1 bit2 | bit1 | Memory allocation
89 * ------+------------+------+------------------
90 * OFF | ON OFF | ON | Area 0
91 * OFF | ON OFF | OFF | Area 4
92 */
93
94/*
95 * NAND Flash ROM
96 *
97 * SW1 | SW2 | SW7 | NAND Flash ROM
98 * bit1 | bit1 bit2 | bit2 | Memory allocation
99 * ------+------------+------+------------------
100 * OFF | ON OFF | ON | FCE 0
101 * OFF | ON OFF | OFF | FCE 1
102 */
103
104/*
105 * SMSC 9220
106 *
107 * SW1 SMSC 9220
108 * -----------------------
109 * ON access disable
110 * OFF access enable
111 */
112
17ccb834 113/*
dda128dc 114 * LCD / IRQ / KEYSC / IrDA
17ccb834 115 *
9fa1b7fe
KM		 116 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
117 * LCD = 2nd LCDC (WVGA)
dda128dc
KM		 118 *
119 * | SW43 |
120 * SW3 | ON | OFF |
121 * -------------+-----------------------+---------------+
122 * ON | KEY / IrDA | LCD |
123 * OFF | KEY / IrDA / IRQ | IRQ |
9fa1b7fe
KM		 124 *
125 *
126 * QHD / WVGA display
127 *
128 * You can choice display type on menuconfig.
129 * Then, check above dip-switch.
17ccb834
KM		 130 */
131
fb54d268
KM		 132/*
133 * USB
134 *
135 * J7 : 1-2 MAX3355E VBUS
136 * 2-3 DC 5.0V
137 *
138 * S39: bit2: off
139 */
140
cb9215e1
KM		 141/*
142 * FSI/FSMI
143 *
144 * SW41 : ON : SH-Mobile AP4 Audio Mode
145 * : OFF : Bluetooth Audio Mode
146 */
147
c8ee3d4b 148/*
d3d03e48 149 * MMC0/SDHI1 (CN7)
c8ee3d4b 150 *
d3d03e48
KM		 151 * J22 : select card voltage
152 * 1-2 pin : 1.8v
153 * 2-3 pin : 3.3v
154 *
155 * SW1 | SW33
156 * | bit1 | bit2 | bit3 | bit4
157 * ------------+------+------+------+-------
158 * MMC0 OFF | OFF | ON | ON | X
159 * SDHI1 OFF | ON | X | OFF | ON
160 *
161 * voltage lebel
162 * CN7 : 1.8v
163 * CN12: 3.3v
c8ee3d4b
KM		 164 */
165
8778b8f4
GL		 166/* Dummy supplies, where voltage doesn't matter */
167static struct regulator_consumer_supply fixed1v8_power_consumers[] =
168{
169 /* J22 default position: 1.8V */
170 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
171 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
172 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
173 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
174};
175
176static struct regulator_consumer_supply fixed3v3_power_consumers[] =
177{
178 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
179 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
180};
181
182static struct regulator_consumer_supply dummy_supplies[] = {
183 REGULATOR_SUPPLY("vddvario", "smsc911x"),
184 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
185};
186
1b7e0677 187/* MTD */
2b7eda63
MD		 188static struct mtd_partition nor_flash_partitions[] = {
189 {
190 .name = "loader",
191 .offset = 0x00000000,
192 .size = 512 * 1024,
2e351ec6 193 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 194 },
195 {
196 .name = "bootenv",
197 .offset = MTDPART_OFS_APPEND,
198 .size = 512 * 1024,
2e351ec6 199 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 200 },
201 {
202 .name = "kernel_ro",
203 .offset = MTDPART_OFS_APPEND,
204 .size = 8 * 1024 * 1024,
205 .mask_flags = MTD_WRITEABLE,
206 },
207 {
208 .name = "kernel",
209 .offset = MTDPART_OFS_APPEND,
210 .size = 8 * 1024 * 1024,
211 },
212 {
213 .name = "data",
214 .offset = MTDPART_OFS_APPEND,
215 .size = MTDPART_SIZ_FULL,
216 },
217};
218
219static struct physmap_flash_data nor_flash_data = {
220 .width = 2,
221 .parts = nor_flash_partitions,
222 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
223};
224
225static struct resource nor_flash_resources[] = {
226 [0] = {
832217da 227 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
8e6a4675 228 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
2b7eda63
MD		 229 .flags = IORESOURCE_MEM,
230 }
231};
232
233static struct platform_device nor_flash_device = {
234 .name = "physmap-flash",
235 .dev = {
236 .platform_data = &nor_flash_data,
237 },
238 .num_resources = ARRAY_SIZE(nor_flash_resources),
239 .resource = nor_flash_resources,
240};
241
1b7e0677
KM		 242/* SMSC 9220 */
243static struct resource smc911x_resources[] = {
244 {
245 .start = 0x14000000,
246 .end = 0x16000000 - 1,
247 .flags = IORESOURCE_MEM,
248 }, {
33c9607a 249 .start = evt2irq(0x02c0) /* IRQ6A */,
1b7e0677
KM		 250 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
251 },
252};
253
254static struct smsc911x_platform_config smsc911x_info = {
255 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
256 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
257 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
258};
259
260static struct platform_device smc911x_device = {
261 .name = "smsc911x",
262 .id = -1,
263 .num_resources = ARRAY_SIZE(smc911x_resources),
264 .resource = smc911x_resources,
265 .dev = {
266 .platform_data = &smsc911x_info,
267 },
268};
2b7eda63 269
68accd73
AH		 270/*
271 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
272 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
273 */
274static int slot_cn7_get_cd(struct platform_device *pdev)
275{
ceb50f33 276 return !gpio_get_value(GPIO_PORT41);
68accd73 277}
1c7fcbed
DHG		 278/* MERAM */
279static struct sh_mobile_meram_info meram_info = {
280 .addr_mode = SH_MOBILE_MERAM_MODE1,
281};
282
283static struct resource meram_resources[] = {
284 [0] = {
e71504d5
LP		 285 .name = "regs",
286 .start = 0xe8000000,
287 .end = 0xe807ffff,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .name = "meram",
292 .start = 0xe8080000,
293 .end = 0xe81fffff,
294 .flags = IORESOURCE_MEM,
1c7fcbed
DHG		 295 },
296};
297
298static struct platform_device meram_device = {
299 .name = "sh_mobile_meram",
300 .id = 0,
301 .num_resources = ARRAY_SIZE(meram_resources),
302 .resource = meram_resources,
303 .dev = {
304 .platform_data = &meram_info,
305 },
306};
68accd73 307
c8ee3d4b
KM		 308/* SH_MMCIF */
309static struct resource sh_mmcif_resources[] = {
310 [0] = {
0fb0834b 311 .name = "MMCIF",
c8ee3d4b
KM		 312 .start = 0xE6BD0000,
313 .end = 0xE6BD00FF,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
317 /* MMC ERR */
8d569341 318 .start = evt2irq(0x1ac0),
c8ee3d4b
KM		 319 .flags = IORESOURCE_IRQ,
320 },
321 [2] = {
322 /* MMC NOR */
8d569341 323 .start = evt2irq(0x1ae0),
c8ee3d4b
KM		 324 .flags = IORESOURCE_IRQ,
325 },
326};
327
bb04e197 328static struct sh_mmcif_plat_data sh_mmcif_plat = {
c8ee3d4b
KM		 329 .sup_pclk = 0,
330 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
331 .caps = MMC_CAP_4_BIT_DATA |
332 MMC_CAP_8_BIT_DATA |
333 MMC_CAP_NEEDS_POLL,
68accd73 334 .get_cd = slot_cn7_get_cd,
d5bb386d
GL		 335 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
336 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
c8ee3d4b
KM		 337};
338
339static struct platform_device sh_mmcif_device = {
340 .name = "sh_mmcif",
341 .id = 0,
342 .dev = {
343 .dma_mask = NULL,
344 .coherent_dma_mask = 0xffffffff,
345 .platform_data = &sh_mmcif_plat,
346 },
347 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
348 .resource = sh_mmcif_resources,
349};
350
3a14d039 351/* SDHI0 */
69bf6f45 352static struct sh_mobile_sdhi_info sdhi0_info = {
341291a6
GL		 353 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
354 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
330e4e71 355 .tmio_caps = MMC_CAP_SDIO_IRQ,
69bf6f45
GL		 356};
357
3a14d039
MD		 358static struct resource sdhi0_resources[] = {
359 [0] = {
360 .name = "SDHI0",
361 .start = 0xe6850000,
31d31fe7 362 .end = 0xe68500ff,
3a14d039
MD		 363 .flags = IORESOURCE_MEM,
364 },
365 [1] = {
2007aea1
SH		 366 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
367 .flags = IORESOURCE_IRQ,
368 },
369 [2] = {
370 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
371 .flags = IORESOURCE_IRQ,
372 },
373 [3] = {
374 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
375 .flags = IORESOURCE_IRQ,
3a14d039
MD		 376 },
377};
378
379static struct platform_device sdhi0_device = {
380 .name = "sh_mobile_sdhi",
381 .num_resources = ARRAY_SIZE(sdhi0_resources),
382 .resource = sdhi0_resources,
383 .id = 0,
69bf6f45
GL		 384 .dev = {
385 .platform_data = &sdhi0_info,
386 },
3a14d039
MD		 387};
388
341291a6
GL		 389/* SDHI1 */
390static struct sh_mobile_sdhi_info sdhi1_info = {
391 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
392 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
393 .tmio_ocr_mask = MMC_VDD_165_195,
410d878b 394 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
330e4e71 395 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
68accd73 396 .get_cd = slot_cn7_get_cd,
341291a6
GL		 397};
398
399static struct resource sdhi1_resources[] = {
400 [0] = {
401 .name = "SDHI1",
402 .start = 0xe6860000,
31d31fe7 403 .end = 0xe68600ff,
341291a6
GL		 404 .flags = IORESOURCE_MEM,
405 },
406 [1] = {
2007aea1
SH		 407 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
408 .flags = IORESOURCE_IRQ,
409 },
410 [2] = {
411 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
412 .flags = IORESOURCE_IRQ,
413 },
414 [3] = {
415 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
416 .flags = IORESOURCE_IRQ,
341291a6
GL		 417 },
418};
419
420static struct platform_device sdhi1_device = {
421 .name = "sh_mobile_sdhi",
422 .num_resources = ARRAY_SIZE(sdhi1_resources),
423 .resource = sdhi1_resources,
424 .id = 1,
425 .dev = {
426 .platform_data = &sdhi1_info,
427 },
428};
429
fb54d268 430/* USB1 */
bb04e197 431static void usb1_host_port_power(int port, int power)
fb54d268
KM		 432{
433 if (!power) /* only power-on supported for now */
434 return;
435
436 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
0a4b04dc 437 __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
fb54d268
KM		 438}
439
440static struct r8a66597_platdata usb1_host_data = {
441 .on_chip = 1,
442 .port_power = usb1_host_port_power,
443};
444
445static struct resource usb1_host_resources[] = {
446 [0] = {
447 .name = "USBHS",
448 .start = 0xE68B0000,
449 .end = 0xE68B00E6 - 1,
450 .flags = IORESOURCE_MEM,
451 },
452 [1] = {
33c9607a 453 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
fb54d268
KM		 454 .flags = IORESOURCE_IRQ,
455 },
456};
457
458static struct platform_device usb1_host_device = {
459 .name = "r8a66597_hcd",
460 .id = 1,
461 .dev = {
462 .dma_mask = NULL, /* not use dma */
463 .coherent_dma_mask = 0xffffffff,
464 .platform_data = &usb1_host_data,
465 },
466 .num_resources = ARRAY_SIZE(usb1_host_resources),
467 .resource = usb1_host_resources,
468};
469
9fa1b7fe
KM		 470/*
471 * QHD display
472 */
473#ifdef CONFIG_AP4EVB_QHD
474
475/* KEYSC (Needs SW43 set to ON) */
476static struct sh_keysc_info keysc_info = {
477 .mode = SH_KEYSC_MODE_1,
478 .scan_timing = 3,
479 .delay = 2500,
480 .keycodes = {
481 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
482 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
483 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
484 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
485 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
486 },
487};
488
489static struct resource keysc_resources[] = {
490 [0] = {
491 .name = "KEYSC",
492 .start = 0xe61b0000,
493 .end = 0xe61b0063,
494 .flags = IORESOURCE_MEM,
495 },
496 [1] = {
497 .start = evt2irq(0x0be0), /* KEYSC_KEY */
498 .flags = IORESOURCE_IRQ,
499 },
500};
501
502static struct platform_device keysc_device = {
503 .name = "sh_keysc",
504 .id = 0, /* "keysc0" clock */
505 .num_resources = ARRAY_SIZE(keysc_resources),
506 .resource = keysc_resources,
507 .dev = {
508 .platform_data = &keysc_info,
509 },
510};
511
512/* MIPI-DSI */
5e47431a
KM		 513static int sh_mipi_set_dot_clock(struct platform_device *pdev,
514 void __iomem *base,
515 int enable)
516{
517 struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
5e47431a
KM		 518
519 if (IS_ERR(pck))
520 return PTR_ERR(pck);
521
522 if (enable) {
8f9c60f2
KM		 523 /*
524 * DSIPCLK = 24MHz
525 * D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
526 * HsByteCLK = D-PHY/8 = 39MHz
527 *
528 * X * Y * FPS =
529 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
530 */
5e47431a 531 clk_set_rate(pck, clk_round_rate(pck, 24000000));
5e47431a
KM		 532 clk_enable(pck);
533 } else {
534 clk_disable(pck);
535 }
536
537 clk_put(pck);
538
539 return 0;
540}
541
8eda2f21
GL		 542static struct resource mipidsi0_resources[] = {
543 [0] = {
544 .start = 0xffc60000,
5958d58a
MD		 545 .end = 0xffc63073,
546 .flags = IORESOURCE_MEM,
547 },
548 [1] = {
549 .start = 0xffc68000,
550 .end = 0xffc680ef,
8eda2f21
GL		 551 .flags = IORESOURCE_MEM,
552 },
553};
554
555static struct sh_mipi_dsi_info mipidsi0_info = {
556 .data_format = MIPI_RGB888,
772f5d1b 557 .channel = LCDC_CHAN_MAINLCD,
26c3d7ac 558 .lane = 2,
6fd46595 559 .vsynw_offset = 17,
8f9c60f2 560 .phyctrl = 0x6 << 8,
a2e62971
KM		 561 .flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
562 SH_MIPI_DSI_HSbyteCLK,
5e47431a 563 .set_dot_clock = sh_mipi_set_dot_clock,
8eda2f21
GL		 564};
565
566static struct platform_device mipidsi0_device = {
567 .name = "sh-mipi-dsi",
568 .num_resources = ARRAY_SIZE(mipidsi0_resources),
569 .resource = mipidsi0_resources,
570 .id = 0,
571 .dev = {
572 .platform_data = &mipidsi0_info,
573 },
574};
575
9fa1b7fe
KM		 576static struct platform_device *qhd_devices[] __initdata = {
577 &mipidsi0_device,
578 &keysc_device,
579};
580#endif /* CONFIG_AP4EVB_QHD */
581
a1022adb
LP		 582/* LCDC0 */
583static const struct fb_videomode ap4evb_lcdc_modes[] = {
584 {
585#ifdef CONFIG_AP4EVB_QHD
586 .name = "R63302(QHD)",
587 .xres = 544,
588 .yres = 961,
589 .left_margin = 72,
590 .right_margin = 600,
591 .hsync_len = 16,
592 .upper_margin = 8,
593 .lower_margin = 8,
594 .vsync_len = 2,
595 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
596#else
597 .name = "WVGA Panel",
598 .xres = 800,
599 .yres = 480,
600 .left_margin = 220,
601 .right_margin = 110,
602 .hsync_len = 70,
603 .upper_margin = 20,
604 .lower_margin = 5,
605 .vsync_len = 5,
606 .sync = 0,
607#endif
608 },
609};
c241a0e0
LP		 610
611static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
a1022adb 612 .icb[0] = {
a1022adb
LP		 613 .meram_size = 0x40,
614 },
615 .icb[1] = {
a1022adb
LP		 616 .meram_size = 0x40,
617 },
618};
619
620static struct sh_mobile_lcdc_info lcdc_info = {
621 .meram_dev = &meram_info,
622 .ch[0] = {
623 .chan = LCDC_CHAN_MAINLCD,
624 .fourcc = V4L2_PIX_FMT_RGB565,
93ff2598
LP		 625 .lcd_modes = ap4evb_lcdc_modes,
626 .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
a1022adb
LP		 627 .meram_cfg = &lcd_meram_cfg,
628#ifdef CONFIG_AP4EVB_QHD
629 .tx_dev = &mipidsi0_device,
630#endif
631 }
632};
633
634static struct resource lcdc_resources[] = {
635 [0] = {
636 .name = "LCDC",
637 .start = 0xfe940000, /* P4-only space */
638 .end = 0xfe943fff,
639 .flags = IORESOURCE_MEM,
640 },
641 [1] = {
642 .start = intcs_evt2irq(0x580),
643 .flags = IORESOURCE_IRQ,
644 },
645};
646
647static struct platform_device lcdc_device = {
648 .name = "sh_mobile_lcdc_fb",
649 .num_resources = ARRAY_SIZE(lcdc_resources),
650 .resource = lcdc_resources,
651 .dev = {
652 .platform_data = &lcdc_info,
653 .coherent_dma_mask = ~0,
654 },
655};
656
cb9215e1
KM		 657/* FSI */
658#define IRQ_FSI evt2irq(0x1840)
bb04e197 659static struct sh_fsi_platform_info fsi_info = {
fec691e7
KM		 660 .port_a = {
661 .flags = SH_FSI_BRS_INV,
fec691e7
KM		 662 },
663 .port_b = {
664 .flags = SH_FSI_BRS_INV |
665 SH_FSI_BRM_INV |
666 SH_FSI_LRS_INV |
12818d82 667 SH_FSI_CLK_CPG |
fec691e7 668 SH_FSI_FMT_SPDIF,
fec691e7 669 },
cb9215e1
KM		 670};
671
672static struct resource fsi_resources[] = {
673 [0] = {
674 .name = "FSI",
675 .start = 0xFE3C0000,
676 .end = 0xFE3C0400 - 1,
677 .flags = IORESOURCE_MEM,
678 },
679 [1] = {
680 .start = IRQ_FSI,
681 .flags = IORESOURCE_IRQ,
682 },
683};
684
685static struct platform_device fsi_device = {
686 .name = "sh_fsi2",
9f6f11b6 687 .id = -1,
cb9215e1
KM		 688 .num_resources = ARRAY_SIZE(fsi_resources),
689 .resource = fsi_resources,
690 .dev = {
691 .platform_data = &fsi_info,
692 },
693};
694
af8a2fe1
KM		 695static struct asoc_simple_dai_init_info fsi2_ak4643_init_info = {
696 .fmt = SND_SOC_DAIFMT_LEFT_J,
697 .codec_daifmt = SND_SOC_DAIFMT_CBM_CFM,
698 .cpu_daifmt = SND_SOC_DAIFMT_CBS_CFS,
699 .sysclk = 11289600,
700};
701
702static struct asoc_simple_card_info fsi2_ak4643_info = {
45f31216
KM		 703 .name = "AK4643",
704 .card = "FSI2A-AK4643",
705 .cpu_dai = "fsia-dai",
706 .codec = "ak4642-codec.0-0013",
707 .platform = "sh_fsi2",
af8a2fe1
KM		 708 .codec_dai = "ak4642-hifi",
709 .init = &fsi2_ak4643_init_info,
45f31216
KM		 710};
711
c8d6bf9a 712static struct platform_device fsi_ak4643_device = {
af8a2fe1 713 .name = "asoc-simple-card",
45f31216 714 .dev = {
e49d603c 715 .platform_data = &fsi2_ak4643_info,
45f31216 716 },
c8d6bf9a 717};
45f31216 718
a1022adb 719/* LCDC1 */
640dcfa0
GL		 720static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
721 unsigned long *parent_freq);
722
dfbcdf64 723static struct sh_mobile_hdmi_info hdmi_info = {
2669efec 724 .flags = HDMI_SND_SRC_SPDIF,
640dcfa0 725 .clk_optimize_parent = ap4evb_clk_optimize,
dfbcdf64
GL		 726};
727
728static struct resource hdmi_resources[] = {
729 [0] = {
730 .name = "HDMI",
731 .start = 0xe6be0000,
732 .end = 0xe6be00ff,
733 .flags = IORESOURCE_MEM,
734 },
735 [1] = {
736 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
737 .start = evt2irq(0x17e0),
738 .flags = IORESOURCE_IRQ,
739 },
740};
741
742static struct platform_device hdmi_device = {
743 .name = "sh-mobile-hdmi",
744 .num_resources = ARRAY_SIZE(hdmi_resources),
745 .resource = hdmi_resources,
746 .id = -1,
747 .dev = {
748 .platform_data = &hdmi_info,
749 },
750};
751
640dcfa0
GL		 752static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
753 unsigned long *parent_freq)
754{
755 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
756 long error;
757
758 if (IS_ERR(hdmi_ick)) {
759 int ret = PTR_ERR(hdmi_ick);
760 pr_err("Cannot get HDMI ICK: %d\n", ret);
761 return ret;
762 }
763
764 error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
765
766 clk_put(hdmi_ick);
767
768 return error;
769}
770
c241a0e0 771static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
1c7fcbed 772 .icb[0] = {
1c7fcbed
DHG		 773 .meram_size = 0x100,
774 },
775 .icb[1] = {
1c7fcbed
DHG		 776 .meram_size = 0x100,
777 },
778};
c8d6bf9a 779
dfbcdf64
GL		 780static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
781 .clock_source = LCDC_CLK_EXTERNAL,
1c7fcbed 782 .meram_dev = &meram_info,
dfbcdf64
GL		 783 .ch[0] = {
784 .chan = LCDC_CHAN_MAINLCD,
edd153a3 785 .fourcc = V4L2_PIX_FMT_RGB565,
dfbcdf64
GL		 786 .interface_type = RGB24,
787 .clock_divider = 1,
788 .flags = LCDC_FLAGS_DWPOL,
1c7fcbed 789 .meram_cfg = &hdmi_meram_cfg,
a1022adb 790 .tx_dev = &hdmi_device,
dfbcdf64
GL		 791 }
792};
793
794static struct resource lcdc1_resources[] = {
795 [0] = {
796 .name = "LCDC1",
797 .start = 0xfe944000,
798 .end = 0xfe947fff,
799 .flags = IORESOURCE_MEM,
800 },
801 [1] = {
88c759a2 802 .start = intcs_evt2irq(0x1780),
dfbcdf64
GL		 803 .flags = IORESOURCE_IRQ,
804 },
805};
806
807static struct platform_device lcdc1_device = {
808 .name = "sh_mobile_lcdc_fb",
809 .num_resources = ARRAY_SIZE(lcdc1_resources),
810 .resource = lcdc1_resources,
811 .id = 1,
812 .dev = {
813 .platform_data = &sh_mobile_lcdc1_info,
814 .coherent_dma_mask = ~0,
815 },
816};
817
fa063b48
KM		 818static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
819 .cpu_daifmt = SND_SOC_DAIFMT_CBM_CFM,
820};
821
822static struct asoc_simple_card_info fsi2_hdmi_info = {
823 .name = "HDMI",
824 .card = "FSI2B-HDMI",
825 .cpu_dai = "fsib-dai",
826 .codec = "sh-mobile-hdmi",
827 .platform = "sh_fsi2",
828 .codec_dai = "sh_mobile_hdmi-hifi",
829 .init = &fsi2_hdmi_init_info,
830};
831
3f25c9cc 832static struct platform_device fsi_hdmi_device = {
fa063b48
KM		 833 .name = "asoc-simple-card",
834 .id = 1,
835 .dev = {
836 .platform_data = &fsi2_hdmi_info,
837 },
3f25c9cc
KM		 838};
839
2863e935
AH		 840static struct gpio_led ap4evb_leds[] = {
841 {
842 .name = "led4",
843 .gpio = GPIO_PORT185,
844 .default_state = LEDS_GPIO_DEFSTATE_ON,
845 },
846 {
847 .name = "led2",
848 .gpio = GPIO_PORT186,
849 .default_state = LEDS_GPIO_DEFSTATE_ON,
850 },
851 {
852 .name = "led3",
853 .gpio = GPIO_PORT187,
854 .default_state = LEDS_GPIO_DEFSTATE_ON,
855 },
856 {
857 .name = "led1",
858 .gpio = GPIO_PORT188,
859 .default_state = LEDS_GPIO_DEFSTATE_ON,
860 }
861};
862
863static struct gpio_led_platform_data ap4evb_leds_pdata = {
864 .num_leds = ARRAY_SIZE(ap4evb_leds),
8050fbf2 865 .leds = ap4evb_leds,
2863e935
AH		 866};
867
868static struct platform_device leds_device = {
869 .name = "leds-gpio",
870 .id = 0,
871 .dev = {
872 .platform_data = &ap4evb_leds_pdata,
873 },
874};
875
1a0b1eac
GL		 876static struct i2c_board_info imx074_info = {
877 I2C_BOARD_INFO("imx074", 0x1a),
878};
879
4d4d6fbb 880static struct soc_camera_link imx074_link = {
1a0b1eac
GL		 881 .bus_id = 0,
882 .board_info = &imx074_info,
883 .i2c_adapter_id = 0,
884 .module_name = "imx074",
885};
886
887static struct platform_device ap4evb_camera = {
888 .name = "soc-camera-pdrv",
889 .id = 0,
890 .dev = {
891 .platform_data = &imx074_link,
892 },
893};
894
895static struct sh_csi2_client_config csi2_clients[] = {
896 {
897 .phy = SH_CSI2_PHY_MAIN,
19a1780b 898 .lanes = 0, /* default: 2 lanes */
1a0b1eac
GL		 899 .channel = 0,
900 .pdev = &ap4evb_camera,
901 },
902};
903
904static struct sh_csi2_pdata csi2_info = {
905 .type = SH_CSI2C,
906 .clients = csi2_clients,
907 .num_clients = ARRAY_SIZE(csi2_clients),
908 .flags = SH_CSI2_ECC | SH_CSI2_CRC,
909};
910
911static struct resource csi2_resources[] = {
912 [0] = {
913 .name = "CSI2",
914 .start = 0xffc90000,
915 .end = 0xffc90fff,
916 .flags = IORESOURCE_MEM,
917 },
918 [1] = {
919 .start = intcs_evt2irq(0x17a0),
920 .flags = IORESOURCE_IRQ,
921 },
922};
923
6b526fed
GL		 924static struct sh_mobile_ceu_companion csi2 = {
925 .id = 0,
1a0b1eac
GL		 926 .num_resources = ARRAY_SIZE(csi2_resources),
927 .resource = csi2_resources,
6b526fed 928 .platform_data = &csi2_info,
1a0b1eac
GL		 929};
930
931static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
932 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
ef8f41ff
GL		 933 .max_width = 8188,
934 .max_height = 8188,
6b526fed 935 .csi2 = &csi2,
1a0b1eac
GL		 936};
937
938static struct resource ceu_resources[] = {
939 [0] = {
940 .name = "CEU",
941 .start = 0xfe910000,
942 .end = 0xfe91009f,
943 .flags = IORESOURCE_MEM,
944 },
945 [1] = {
946 .start = intcs_evt2irq(0x880),
947 .flags = IORESOURCE_IRQ,
948 },
949 [2] = {
950 /* place holder for contiguous memory */
951 },
952};
953
954static struct platform_device ceu_device = {
955 .name = "sh_mobile_ceu",
956 .id = 0, /* "ceu0" clock */
957 .num_resources = ARRAY_SIZE(ceu_resources),
958 .resource = ceu_resources,
959 .dev = {
05a5f01c
GL		 960 .platform_data = &sh_mobile_ceu_info,
961 .coherent_dma_mask = 0xffffffff,
1a0b1eac
GL		 962 },
963};
964
2b7eda63 965static struct platform_device *ap4evb_devices[] __initdata = {
2863e935 966 &leds_device,
2b7eda63 967 &nor_flash_device,
1b7e0677 968 &smc911x_device,
3a14d039 969 &sdhi0_device,
341291a6 970 &sdhi1_device,
fb54d268 971 &usb1_host_device,
cb9215e1 972 &fsi_device,
c8d6bf9a 973 &fsi_ak4643_device,
3f25c9cc 974 &fsi_hdmi_device,
beccb12f 975 &sh_mmcif_device,
dfbcdf64 976 &hdmi_device,
a1022adb
LP		 977 &lcdc_device,
978 &lcdc1_device,
1a0b1eac
GL		 979 &ceu_device,
980 &ap4evb_camera,
1c7fcbed 981 &meram_device,
2b7eda63
MD		 982};
983
2ce51f8b 984static void __init hdmi_init_pm_clock(void)
dfbcdf64
GL		 985{
986 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
987 int ret;
988 long rate;
989
990 if (IS_ERR(hdmi_ick)) {
991 ret = PTR_ERR(hdmi_ick);
992 pr_err("Cannot get HDMI ICK: %d\n", ret);
993 goto out;
994 }
995
685e4080 996 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
dfbcdf64 997 if (ret < 0) {
685e4080 998 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
dfbcdf64
GL		 999 goto out;
1000 }
1001
685e4080 1002 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
dfbcdf64 1003
685e4080 1004 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
dfbcdf64
GL		 1005 if (rate < 0) {
1006 pr_err("Cannot get suitable rate: %ld\n", rate);
1007 ret = rate;
1008 goto out;
1009 }
1010
685e4080 1011 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
dfbcdf64
GL		 1012 if (ret < 0) {
1013 pr_err("Cannot set rate %ld: %d\n", rate, ret);
1014 goto out;
1015 }
1016
1017 pr_debug("PLLC2 set frequency %lu\n", rate);
1018
685e4080 1019 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
2ce51f8b 1020 if (ret < 0)
dfbcdf64 1021 pr_err("Cannot set HDMI parent: %d\n", ret);
dfbcdf64
GL		 1022
1023out:
1024 if (!IS_ERR(hdmi_ick))
1025 clk_put(hdmi_ick);
dfbcdf64
GL		 1026}
1027
9fa1b7fe 1028/* TouchScreen */
52d5ac00
KM		 1029#ifdef CONFIG_AP4EVB_QHD
1030# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
1031# define GPIO_TSC_PORT GPIO_PORT123
1032#else /* WVGA */
1033# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
1034# define GPIO_TSC_PORT GPIO_PORT40
1035#endif
1036
33c9607a 1037#define IRQ28 evt2irq(0x3380) /* IRQ28A */
9fa1b7fe 1038#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
71c3ba9a
KM		 1039static int ts_get_pendown_state(void)
1040{
52d5ac00 1041 int val;
71c3ba9a 1042
52d5ac00 1043 gpio_free(GPIO_TSC_IRQ);
71c3ba9a 1044
52d5ac00 1045 gpio_request(GPIO_TSC_PORT, NULL);
71c3ba9a 1046
52d5ac00 1047 gpio_direction_input(GPIO_TSC_PORT);
71c3ba9a 1048
52d5ac00 1049 val = gpio_get_value(GPIO_TSC_PORT);
71c3ba9a 1050
52d5ac00 1051 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a 1052
52d5ac00 1053 return !val;
71c3ba9a
KM		 1054}
1055
71c3ba9a
KM		 1056static int ts_init(void)
1057{
52d5ac00 1058 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a
KM		 1059
1060 return 0;
1061}
1062
bb04e197 1063static struct tsc2007_platform_data tsc2007_info = {
91cf5082
KM		 1064 .model = 2007,
1065 .x_plate_ohms = 180,
71c3ba9a
KM		 1066 .get_pendown_state = ts_get_pendown_state,
1067 .init_platform_hw = ts_init,
91cf5082
KM		 1068};
1069
9fa1b7fe
KM		 1070static struct i2c_board_info tsc_device = {
1071 I2C_BOARD_INFO("tsc2007", 0x48),
1072 .type = "tsc2007",
1073 .platform_data = &tsc2007_info,
1074 /*.irq is selected on ap4evb_init */
1075};
1076
91cf5082 1077/* I2C */
cb9215e1
KM		 1078static struct i2c_board_info i2c0_devices[] = {
1079 {
1080 I2C_BOARD_INFO("ak4643", 0x13),
1081 },
1082};
1083
91cf5082 1084static struct i2c_board_info i2c1_devices[] = {
8fc883c2
KM		 1085 {
1086 I2C_BOARD_INFO("r2025sd", 0x32),
1087 },
91cf5082
KM		 1088};
1089
2b7eda63 1090
0a4b04dc
AB		 1091#define GPIO_PORT9CR IOMEM(0xE6051009)
1092#define GPIO_PORT10CR IOMEM(0xE605100A)
1093#define USCCR1 IOMEM(0xE6058144)
2b7eda63
MD		 1094static void __init ap4evb_init(void)
1095{
201dbd81
RW		 1096 struct pm_domain_device domain_devices[] = {
1097 { "A4LC", &lcdc1_device, },
1098 { "A4LC", &lcdc_device, },
1099 { "A4MP", &fsi_device, },
1100 { "A3SP", &sh_mmcif_device, },
1101 { "A3SP", &sdhi0_device, },
1102 { "A3SP", &sdhi1_device, },
1103 { "A4R", &ceu_device, },
1104 };
dfbcdf64 1105 u32 srcr4;
cb9215e1
KM		 1106 struct clk *clk;
1107
8778b8f4
GL		 1108 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
1109 ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
1110 regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
1111 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
1112 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
1113
e3b0161b
MD		 1114 /* External clock source */
1115 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1116
1b7e0677
KM		 1117 sh7372_pinmux_init();
1118
b228b48e
KM		 1119 /* enable SCIFA0 */
1120 gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
1121 gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
1122
1b7e0677
KM		 1123 /* enable SMSC911X */
1124 gpio_request(GPIO_FN_CS5A, NULL);
1125 gpio_request(GPIO_FN_IRQ6_39, NULL);
1126
8cb3a2eb
KM		 1127 /* enable Debug switch (S6) */
1128 gpio_request(GPIO_PORT32, NULL);
1129 gpio_request(GPIO_PORT33, NULL);
1130 gpio_request(GPIO_PORT34, NULL);
1131 gpio_request(GPIO_PORT35, NULL);
1132 gpio_direction_input(GPIO_PORT32);
1133 gpio_direction_input(GPIO_PORT33);
1134 gpio_direction_input(GPIO_PORT34);
1135 gpio_direction_input(GPIO_PORT35);
1136 gpio_export(GPIO_PORT32, 0);
1137 gpio_export(GPIO_PORT33, 0);
1138 gpio_export(GPIO_PORT34, 0);
1139 gpio_export(GPIO_PORT35, 0);
1140
3a14d039
MD		 1141 /* SDHI0 */
1142 gpio_request(GPIO_FN_SDHICD0, NULL);
1143 gpio_request(GPIO_FN_SDHIWP0, NULL);
1144 gpio_request(GPIO_FN_SDHICMD0, NULL);
1145 gpio_request(GPIO_FN_SDHICLK0, NULL);
1146 gpio_request(GPIO_FN_SDHID0_3, NULL);
1147 gpio_request(GPIO_FN_SDHID0_2, NULL);
1148 gpio_request(GPIO_FN_SDHID0_1, NULL);
1149 gpio_request(GPIO_FN_SDHID0_0, NULL);
1150
9fa1b7fe
KM		 1151 /* SDHI1 */
1152 gpio_request(GPIO_FN_SDHICMD1, NULL);
1153 gpio_request(GPIO_FN_SDHICLK1, NULL);
1154 gpio_request(GPIO_FN_SDHID1_3, NULL);
1155 gpio_request(GPIO_FN_SDHID1_2, NULL);
1156 gpio_request(GPIO_FN_SDHID1_1, NULL);
1157 gpio_request(GPIO_FN_SDHID1_0, NULL);
91cf5082 1158
c8ee3d4b
KM		 1159 /* MMCIF */
1160 gpio_request(GPIO_FN_MMCD0_0, NULL);
1161 gpio_request(GPIO_FN_MMCD0_1, NULL);
1162 gpio_request(GPIO_FN_MMCD0_2, NULL);
1163 gpio_request(GPIO_FN_MMCD0_3, NULL);
1164 gpio_request(GPIO_FN_MMCD0_4, NULL);
1165 gpio_request(GPIO_FN_MMCD0_5, NULL);
1166 gpio_request(GPIO_FN_MMCD0_6, NULL);
1167 gpio_request(GPIO_FN_MMCD0_7, NULL);
1168 gpio_request(GPIO_FN_MMCCMD0, NULL);
1169 gpio_request(GPIO_FN_MMCCLK0, NULL);
1170
fb54d268
KM		 1171 /* USB enable */
1172 gpio_request(GPIO_FN_VBUS0_1, NULL);
1173 gpio_request(GPIO_FN_IDIN_1_18, NULL);
1174 gpio_request(GPIO_FN_PWEN_1_115, NULL);
1175 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1176 gpio_request(GPIO_FN_EXTLP_1, NULL);
1177 gpio_request(GPIO_FN_OVCN2_1, NULL);
1178
1179 /* setup USB phy */
0a4b04dc 1180 __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */
fb54d268 1181
2669efec 1182 /* enable FSI2 port A (ak4643) */
cb9215e1
KM		 1183 gpio_request(GPIO_FN_FSIAIBT, NULL);
1184 gpio_request(GPIO_FN_FSIAILR, NULL);
1185 gpio_request(GPIO_FN_FSIAISLD, NULL);
1186 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1187 gpio_request(GPIO_PORT161, NULL);
1188 gpio_direction_output(GPIO_PORT161, 0); /* slave */
1189
1190 gpio_request(GPIO_PORT9, NULL);
1191 gpio_request(GPIO_PORT10, NULL);
6a6196af
KM		 1192 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1193 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
cb9215e1 1194
68accd73
AH		 1195 /* card detect pin for MMC slot (CN7) */
1196 gpio_request(GPIO_PORT41, NULL);
1197 gpio_direction_input(GPIO_PORT41);
1198
2669efec
KM		 1199 /* setup FSI2 port B (HDMI) */
1200 gpio_request(GPIO_FN_FSIBCK, NULL);
1201 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1202
cb9215e1
KM		 1203 /* set SPU2 clock to 119.6 MHz */
1204 clk = clk_get(NULL, "spu_clk");
2ae2b766 1205 if (!IS_ERR(clk)) {
cb9215e1
KM		 1206 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1207 clk_put(clk);
1208 }
1209
cb9215e1
KM		 1210 /*
1211 * set irq priority, to avoid sound chopping
1212 * when NFS rootfs is used
1213 * FSI(3) > SMSC911X(2)
1214 */
1215 intc_set_priority(IRQ_FSI, 3);
1216
1217 i2c_register_board_info(0, i2c0_devices,
1218 ARRAY_SIZE(i2c0_devices));
1219
1220 i2c_register_board_info(1, i2c1_devices,
1221 ARRAY_SIZE(i2c1_devices));
1222
9fa1b7fe 1223#ifdef CONFIG_AP4EVB_QHD
dd8a61a7 1224
9fa1b7fe 1225 /*
dd8a61a7
MD		 1226 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
1227 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
9fa1b7fe
KM		 1228 */
1229
1230 /* enable KEYSC */
1231 gpio_request(GPIO_FN_KEYOUT0, NULL);
1232 gpio_request(GPIO_FN_KEYOUT1, NULL);
1233 gpio_request(GPIO_FN_KEYOUT2, NULL);
1234 gpio_request(GPIO_FN_KEYOUT3, NULL);
1235 gpio_request(GPIO_FN_KEYOUT4, NULL);
1236 gpio_request(GPIO_FN_KEYIN0_136, NULL);
1237 gpio_request(GPIO_FN_KEYIN1_135, NULL);
1238 gpio_request(GPIO_FN_KEYIN2_134, NULL);
1239 gpio_request(GPIO_FN_KEYIN3_133, NULL);
1240 gpio_request(GPIO_FN_KEYIN4, NULL);
1241
1242 /* enable TouchScreen */
6845664a 1243 irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1244
1245 tsc_device.irq = IRQ28;
1246 i2c_register_board_info(1, &tsc_device, 1);
1247
1248 /* LCDC0 */
1249 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1250 lcdc_info.ch[0].interface_type = RGB24;
1251 lcdc_info.ch[0].clock_divider = 1;
1252 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
afaad83b
LP		 1253 lcdc_info.ch[0].panel_cfg.width = 44;
1254 lcdc_info.ch[0].panel_cfg.height = 79;
9fa1b7fe
KM		 1255
1256 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
1257
1258#else
1259 /*
dd8a61a7
MD		 1260 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
1261 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
9fa1b7fe 1262 */
dd8a61a7 1263
9fa1b7fe
KM		 1264 gpio_request(GPIO_FN_LCDD17, NULL);
1265 gpio_request(GPIO_FN_LCDD16, NULL);
1266 gpio_request(GPIO_FN_LCDD15, NULL);
1267 gpio_request(GPIO_FN_LCDD14, NULL);
1268 gpio_request(GPIO_FN_LCDD13, NULL);
1269 gpio_request(GPIO_FN_LCDD12, NULL);
1270 gpio_request(GPIO_FN_LCDD11, NULL);
1271 gpio_request(GPIO_FN_LCDD10, NULL);
1272 gpio_request(GPIO_FN_LCDD9, NULL);
1273 gpio_request(GPIO_FN_LCDD8, NULL);
1274 gpio_request(GPIO_FN_LCDD7, NULL);
1275 gpio_request(GPIO_FN_LCDD6, NULL);
1276 gpio_request(GPIO_FN_LCDD5, NULL);
1277 gpio_request(GPIO_FN_LCDD4, NULL);
1278 gpio_request(GPIO_FN_LCDD3, NULL);
1279 gpio_request(GPIO_FN_LCDD2, NULL);
1280 gpio_request(GPIO_FN_LCDD1, NULL);
1281 gpio_request(GPIO_FN_LCDD0, NULL);
1282 gpio_request(GPIO_FN_LCDDISP, NULL);
1283 gpio_request(GPIO_FN_LCDDCK, NULL);
1284
1285 gpio_request(GPIO_PORT189, NULL); /* backlight */
1286 gpio_direction_output(GPIO_PORT189, 1);
1287
1288 gpio_request(GPIO_PORT151, NULL); /* LCDDON */
1289 gpio_direction_output(GPIO_PORT151, 1);
1290
1291 lcdc_info.clock_source = LCDC_CLK_BUS;
1292 lcdc_info.ch[0].interface_type = RGB18;
f60cb470 1293 lcdc_info.ch[0].clock_divider = 3;
9fa1b7fe 1294 lcdc_info.ch[0].flags = 0;
afaad83b
LP		 1295 lcdc_info.ch[0].panel_cfg.width = 152;
1296 lcdc_info.ch[0].panel_cfg.height = 91;
9fa1b7fe
KM		 1297
1298 /* enable TouchScreen */
6845664a 1299 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1300
1301 tsc_device.irq = IRQ7;
1302 i2c_register_board_info(0, &tsc_device, 1);
1303#endif /* CONFIG_AP4EVB_QHD */
341291a6 1304
1a0b1eac
GL		 1305 /* CEU */
1306
1307 /*
1308 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
1309 * becomes available
1310 */
1311
1312 /* MIPI-CSI stuff */
1313 gpio_request(GPIO_FN_VIO_CKO, NULL);
1314
1315 clk = clk_get(NULL, "vck1_clk");
1316 if (!IS_ERR(clk)) {
1317 clk_set_rate(clk, clk_round_rate(clk, 13000000));
1318 clk_enable(clk);
1319 clk_put(clk);
1320 }
1321
2b7eda63
MD		 1322 sh7372_add_standard_devices();
1323
dfbcdf64
GL		 1324 /* HDMI */
1325 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1326 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1327
1328 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
0a4b04dc 1329#define SRCR4 IOMEM(0xe61580bc)
dfbcdf64
GL		 1330 srcr4 = __raw_readl(SRCR4);
1331 __raw_writel(srcr4 | (1 << 13), SRCR4);
1332 udelay(50);
1333 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1334
2b7eda63 1335 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
2ce51f8b 1336
201dbd81
RW		 1337 rmobile_add_devices_to_domains(domain_devices,
1338 ARRAY_SIZE(domain_devices));
d93f5cde 1339
2ce51f8b 1340 hdmi_init_pm_clock();
97991657 1341 sh7372_pm_init();
a41b6466 1342 pm_clk_add(&fsi_device.dev, "spu2");
d0168fdc 1343 pm_clk_add(&lcdc1_device.dev, "hdmi");
2b7eda63
MD		 1344}
1345
1346MACHINE_START(AP4EVB, "ap4evb")
5d7220ec
MD		 1347 .map_io = sh7372_map_io,
1348 .init_early = sh7372_add_early_devices,
2b7eda63 1349 .init_irq = sh7372_init_irq,
863b1719 1350 .handle_irq = shmobile_handle_irq_intc,
2b7eda63 1351 .init_machine = ap4evb_init,
caaca999 1352 .init_late = sh7372_pm_init_late,
6bb27d73 1353 .init_time = sh7372_earlytimer_init,
2b7eda63 1354MACHINE_END
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