[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-shmobile / clock-r7s72100.c

/*
 * r7a72100 clock framework support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2012  Phil Edworthy
 * Copyright (C) 2011  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <mach/common.h>
#include <mach/r7s72100.h>

/* Frequency Control Registers */
#define FRQCR		0xfcfe0010
#define FRQCR2		0xfcfe0014
/* Standby Control Registers */
#define STBCR3		0xfcfe0420
#define STBCR4		0xfcfe0424
#define STBCR7		0xfcfe0430
#define STBCR9		0xfcfe0438
#define STBCR10		0xfcfe043c

#define PLL_RATE 30

static struct clk_mapping cpg_mapping = {
	.phys	= 0xfcfe0000,
	.len	= 0x1000,
};

/* Fixed 32 KHz root clock for RTC */
static struct clk r_clk = {
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
static struct clk extal_clk = {
	.rate		= 13330000,
	.mapping	= &cpg_mapping,
};

static unsigned long pll_recalc(struct clk *clk)
{
	return clk->parent->rate * PLL_RATE;
}

static struct sh_clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.ops		= &pll_clk_ops,
	.parent		= &extal_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long bus_recalc(struct clk *clk)
{
	return clk->parent->rate / 3;
}

static struct sh_clk_ops bus_clk_ops = {
	.recalc		= bus_recalc,
};

static struct clk bus_clk = {
	.ops		= &bus_clk_ops,
	.parent		= &pll_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long peripheral0_recalc(struct clk *clk)
{
	return clk->parent->rate / 12;
}

static struct sh_clk_ops peripheral0_clk_ops = {
	.recalc		= peripheral0_recalc,
};

static struct clk peripheral0_clk = {
	.ops		= &peripheral0_clk_ops,
	.parent		= &pll_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long peripheral1_recalc(struct clk *clk)
{
	return clk->parent->rate / 6;
}

static struct sh_clk_ops peripheral1_clk_ops = {
	.recalc		= peripheral1_recalc,
};

static struct clk peripheral1_clk = {
	.ops		= &peripheral1_clk_ops,
	.parent		= &pll_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&pll_clk,
	&bus_clk,
	&peripheral0_clk,
	&peripheral1_clk,
};

static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
static int multipliers[] = { 1, 2, 1, 1 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = div2,
	.nr_divisors = ARRAY_SIZE(div2),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I,
	DIV4_NR };

#define DIV4(_reg, _bit, _mask, _flags) \
	SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

/* The mask field specifies the div2 entries that are valid */
struct clk div4_clks[DIV4_NR] = {
	[DIV4_I]  = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
					| CLK_ENABLE_ON_INIT),
};

enum {
	MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
	MSTP97, MSTP96, MSTP95, MSTP94,
	MSTP74,
	MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
	MSTP33,	MSTP_NR
};

static struct clk mstp_clks[MSTP_NR] = {
	[MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
	[MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
	[MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
	[MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
	[MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
	[MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
	[MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
	[MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
	[MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
	[MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
	[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
	[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
	[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
	[MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
	[MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
	[MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
	[MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
	[MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
	[MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
};

static struct clk_lookup lookups[] = {
	/* main clocks */
	CLKDEV_CON_ID("rclk", &r_clk),
	CLKDEV_CON_ID("extal", &extal_clk),
	CLKDEV_CON_ID("pll_clk", &pll_clk),
	CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),

	/* DIV4 clocks */
	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

	/* MSTP clocks */
	CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
	CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
	CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
	CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
	CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
	CLKDEV_DEV_ID("e800c800.spi", &mstp_clks[MSTP107]),
	CLKDEV_DEV_ID("e800d000.spi", &mstp_clks[MSTP106]),
	CLKDEV_DEV_ID("e800d800.spi", &mstp_clks[MSTP105]),
	CLKDEV_DEV_ID("e800e000.spi", &mstp_clks[MSTP104]),
	CLKDEV_DEV_ID("e800e800.spi", &mstp_clks[MSTP103]),
	CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),

	/* ICK */
	CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
	CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
	CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
	CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
	CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
	CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
	CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
	CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
	CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP33]),
};

void __init r7s72100_clock_init(void)
{
	int k, ret = 0;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);

	if (!ret)
		shmobile_clk_init();
	else
		panic("failed to setup rza1 clocks\n");
}
Commit	Line	Data
e3da5b36 MD	1	/*
	2	* r7a72100 clock framework support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2012 Phil Edworthy
	6	* Copyright (C) 2011 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17	#include <linux/init.h>
	18	#include <linux/kernel.h>
	19	#include <linux/io.h>
	20	#include <linux/sh_clk.h>
	21	#include <linux/clkdev.h>
	22	#include <mach/common.h>
	23	#include <mach/r7s72100.h>
	24
d9409fb8	25	/* Frequency Control Registers */
e3da5b36 MD	26	#define FRQCR 0xfcfe0010
e3da5b36 MD	27	#define FRQCR2 0xfcfe0014
d9409fb8	28	/* Standby Control Registers */
e3da5b36 MD	29	#define STBCR3 0xfcfe0420
e3da5b36 MD	30	#define STBCR4 0xfcfe0424
0e7ed0c1	31	#define STBCR7 0xfcfe0430
d85bcfa9	32	#define STBCR9 0xfcfe0438
d9409fb8	33	#define STBCR10 0xfcfe043c
e3da5b36 MD	34
	35	#define PLL_RATE 30
	36
	37	static struct clk_mapping cpg_mapping = {
	38	.phys = 0xfcfe0000,
	39	.len = 0x1000,
	40	};
	41
	42	/* Fixed 32 KHz root clock for RTC */
	43	static struct clk r_clk = {
	44	.rate = 32768,
	45	};
	46
	47	/*
	48	* Default rate for the root input clock, reset this with clk_set_rate()
	49	* from the platform code.
	50	*/
	51	static struct clk extal_clk = {
	52	.rate = 13330000,
	53	.mapping = &cpg_mapping,
	54	};
	55
	56	static unsigned long pll_recalc(struct clk *clk)
	57	{
	58	return clk->parent->rate * PLL_RATE;
	59	}
	60
	61	static struct sh_clk_ops pll_clk_ops = {
	62	.recalc = pll_recalc,
	63	};
	64
	65	static struct clk pll_clk = {
	66	.ops = &pll_clk_ops,
	67	.parent = &extal_clk,
	68	.flags = CLK_ENABLE_ON_INIT,
	69	};
	70
	71	static unsigned long bus_recalc(struct clk *clk)
	72	{
d93023f8	73	return clk->parent->rate / 3;
e3da5b36 MD	74	}
	75
	76	static struct sh_clk_ops bus_clk_ops = {
	77	.recalc = bus_recalc,
	78	};
	79
	80	static struct clk bus_clk = {
	81	.ops = &bus_clk_ops,
	82	.parent = &pll_clk,
	83	.flags = CLK_ENABLE_ON_INIT,
	84	};
	85
	86	static unsigned long peripheral0_recalc(struct clk *clk)
	87	{
	88	return clk->parent->rate / 12;
	89	}
	90
	91	static struct sh_clk_ops peripheral0_clk_ops = {
	92	.recalc = peripheral0_recalc,
	93	};
	94
	95	static struct clk peripheral0_clk = {
	96	.ops = &peripheral0_clk_ops,
	97	.parent = &pll_clk,
	98	.flags = CLK_ENABLE_ON_INIT,
	99	};
	100
	101	static unsigned long peripheral1_recalc(struct clk *clk)
	102	{
	103	return clk->parent->rate / 6;
	104	}
	105
	106	static struct sh_clk_ops peripheral1_clk_ops = {
	107	.recalc = peripheral1_recalc,
	108	};
	109
	110	static struct clk peripheral1_clk = {
	111	.ops = &peripheral1_clk_ops,
	112	.parent = &pll_clk,
	113	.flags = CLK_ENABLE_ON_INIT,
	114	};
	115
	116	struct clk *main_clks[] = {
	117	&r_clk,
	118	&extal_clk,
	119	&pll_clk,
	120	&bus_clk,
	121	&peripheral0_clk,
	122	&peripheral1_clk,
	123	};
	124
	125	static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
	126	static int multipliers[] = { 1, 2, 1, 1 };
	127
	128	static struct clk_div_mult_table div4_div_mult_table = {
	129	.divisors = div2,
	130	.nr_divisors = ARRAY_SIZE(div2),
	131	.multipliers = multipliers,
	132	.nr_multipliers = ARRAY_SIZE(multipliers),
	133	};
	134
	135	static struct clk_div4_table div4_table = {
	136	.div_mult_table = &div4_div_mult_table,
	137	};
138
139	enum { DIV4_I,
140	DIV4_NR };
141
142	#define DIV4(_reg, _bit, _mask, _flags) \
143	SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
144
145	/* The mask field specifies the div2 entries that are valid */
146	struct clk div4_clks[DIV4_NR] = {
147	[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
148	\| CLK_ENABLE_ON_INIT),
149	};
150
d9409fb8 GU	151	enum {
	152	MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
	153	MSTP97, MSTP96, MSTP95, MSTP94,
0e7ed0c1	154	MSTP74,
d85bcfa9	155	MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
d9409fb8 GU	156	MSTP33, MSTP_NR
d9409fb8 GU	157	};
e3da5b36 MD	158
e3da5b36 MD	159	static struct clk mstp_clks[MSTP_NR] = {
d9409fb8 GU	160	[MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
	161	[MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
	162	[MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
	163	[MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
	164	[MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
d85bcfa9 WS	165	[MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
	166	[MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
	167	[MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
	168	[MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
0e7ed0c1	169	[MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
e3da5b36 MD	170	[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
	171	[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
	172	[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
	173	[MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
	174	[MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
	175	[MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
	176	[MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
	177	[MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
	178	[MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
	179	};
	180
	181	static struct clk_lookup lookups[] = {
	182	/* main clocks */
	183	CLKDEV_CON_ID("rclk", &r_clk),
	184	CLKDEV_CON_ID("extal", &extal_clk),
	185	CLKDEV_CON_ID("pll_clk", &pll_clk),
	186	CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
	187
	188	/* DIV4 clocks */
	189	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	190
	191	/* MSTP clocks */
d9409fb8 GU	192	CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
	193	CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
	194	CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
	195	CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
	196	CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
3fc3e908 GU	197	CLKDEV_DEV_ID("e800c800.spi", &mstp_clks[MSTP107]),
	198	CLKDEV_DEV_ID("e800d000.spi", &mstp_clks[MSTP106]),
	199	CLKDEV_DEV_ID("e800d800.spi", &mstp_clks[MSTP105]),
	200	CLKDEV_DEV_ID("e800e000.spi", &mstp_clks[MSTP104]),
	201	CLKDEV_DEV_ID("e800e800.spi", &mstp_clks[MSTP103]),
0e7ed0c1	202	CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
204aa273 KM	203
204aa273 KM	204	/* ICK */
f6ca6f11 MD	205	CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
	206	CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
	207	CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
	208	CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
	209	CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
	210	CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
	211	CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
	212	CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
c17fcfbc	213	CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP33]),
e3da5b36 MD	214	};
	215
	216	void __init r7s72100_clock_init(void)
	217	{
	218	int k, ret = 0;
	219
	220	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	221	ret = clk_register(main_clks[k]);
	222
	223	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
	224
	225	if (!ret)
	226	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	227
	228	if (!ret)
	229	ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
	230
	231	if (!ret)
	232	shmobile_clk_init();
	233	else
	234	panic("failed to setup rza1 clocks\n");
	235	}