[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-shmobile / clock-sh7372.c

/*
 * SH7372 clock framework support
 *
 * Copyright (C) 2010 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <mach/common.h>
#include <asm/clkdev.h>

/* SH7372 registers */
#define FRQCRA		0xe6150000
#define FRQCRB		0xe6150004
#define FRQCRC		0xe61500e0
#define FRQCRD		0xe61500e4
#define VCLKCR1		0xe6150008
#define VCLKCR2		0xe615000c
#define VCLKCR3		0xe615001c
#define FMSICKCR	0xe6150010
#define FMSOCKCR	0xe6150014
#define FSIACKCR	0xe6150018
#define FSIBCKCR	0xe6150090
#define SUBCKCR		0xe6150080
#define SPUCKCR		0xe6150084
#define VOUCKCR		0xe6150088
#define HDMICKCR	0xe6150094
#define DSITCKCR	0xe6150060
#define DSI0PCKCR	0xe6150064
#define DSI1PCKCR	0xe6150098
#define PLLC01CR	0xe6150028
#define PLLC2CR		0xe615002c
#define SMSTPCR0	0xe6150130
#define SMSTPCR1	0xe6150134
#define SMSTPCR2	0xe6150138
#define SMSTPCR3	0xe615013c
#define SMSTPCR4	0xe6150140

/* Platforms must set frequency on their DV_CLKI pin */
struct clk dv_clki_clk = {
};

/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk r_clk = {
	.rate           = 32768,
};

/*
 * 26MHz default rate for the EXTAL1 root input clock.
 * If needed, reset this with clk_set_rate() from the platform code.
 */
struct clk sh7372_extal1_clk = {
	.rate		= 26000000,
};

/*
 * 48MHz default rate for the EXTAL2 root input clock.
 * If needed, reset this with clk_set_rate() from the platform code.
 */
struct clk sh7372_extal2_clk = {
	.rate		= 48000000,
};

/* A fixed divide-by-2 block */
static unsigned long div2_recalc(struct clk *clk)
{
	return clk->parent->rate / 2;
}

static struct clk_ops div2_clk_ops = {
	.recalc		= div2_recalc,
};

/* Divide dv_clki by two */
struct clk dv_clki_div2_clk = {
	.ops		= &div2_clk_ops,
	.parent		= &dv_clki_clk,
};

/* Divide extal1 by two */
static struct clk extal1_div2_clk = {
	.ops		= &div2_clk_ops,
	.parent		= &sh7372_extal1_clk,
};

/* Divide extal2 by two */
static struct clk extal2_div2_clk = {
	.ops		= &div2_clk_ops,
	.parent		= &sh7372_extal2_clk,
};

/* Divide extal2 by four */
static struct clk extal2_div4_clk = {
	.ops		= &div2_clk_ops,
	.parent		= &extal2_div2_clk,
};

/* PLLC0 and PLLC1 */
static unsigned long pllc01_recalc(struct clk *clk)
{
	unsigned long mult = 1;

	if (__raw_readl(PLLC01CR) & (1 << 14))
		mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;

	return clk->parent->rate * mult;
}

static struct clk_ops pllc01_clk_ops = {
	.recalc		= pllc01_recalc,
};

static struct clk pllc0_clk = {
	.ops		= &pllc01_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
	.parent		= &extal1_div2_clk,
	.enable_reg	= (void __iomem *)FRQCRC,
};

static struct clk pllc1_clk = {
	.ops		= &pllc01_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
	.parent		= &extal1_div2_clk,
	.enable_reg	= (void __iomem *)FRQCRA,
};

/* Divide PLLC1 by two */
static struct clk pllc1_div2_clk = {
	.ops		= &div2_clk_ops,
	.parent		= &pllc1_clk,
};

/* PLLC2 */

/* Indices are important - they are the actual src selecting values */
static struct clk *pllc2_parent[] = {
	[0] = &extal1_div2_clk,
	[1] = &extal2_div2_clk,
	[2] = &dv_clki_div2_clk,
};

/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
static struct cpufreq_frequency_table pllc2_freq_table[29];

static void pllc2_table_rebuild(struct clk *clk)
{
	int i;

	/* Initialise PLLC2 frequency table */
	for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
		pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
		pllc2_freq_table[i].index = i;
	}

	/* This is a special entry - switching PLL off makes it a repeater */
	pllc2_freq_table[i].frequency = clk->parent->rate;
	pllc2_freq_table[i].index = i;

	pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
	pllc2_freq_table[i].index = i;
}

static unsigned long pllc2_recalc(struct clk *clk)
{
	unsigned long mult = 1;

	pllc2_table_rebuild(clk);

	/*
	 * If the PLL is off, mult == 1, clk->rate will be updated in
	 * pllc2_enable().
	 */
	if (__raw_readl(PLLC2CR) & (1 << 31))
		mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;

	return clk->parent->rate * mult;
}

static long pllc2_round_rate(struct clk *clk, unsigned long rate)
{
	return clk_rate_table_round(clk, clk->freq_table, rate);
}

static int pllc2_enable(struct clk *clk)
{
	int i;

	__raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);

	for (i = 0; i < 100; i++)
		if (__raw_readl(PLLC2CR) & 0x80000000) {
			clk->rate = pllc2_recalc(clk);
			return 0;
		}

	pr_err("%s(): timeout!\n", __func__);

	return -ETIMEDOUT;
}

static void pllc2_disable(struct clk *clk)
{
	__raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
}

static int pllc2_set_rate(struct clk *clk,
			  unsigned long rate, int algo_id)
{
	unsigned long value;
	int idx;

	idx = clk_rate_table_find(clk, clk->freq_table, rate);
	if (idx < 0)
		return idx;

	if (rate == clk->parent->rate) {
		pllc2_disable(clk);
		return 0;
	}

	value = __raw_readl(PLLC2CR) & ~(0x3f << 24);

	if (value & 0x80000000)
		pllc2_disable(clk);

	__raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);

	if (value & 0x80000000)
		return pllc2_enable(clk);

	return 0;
}

static int pllc2_set_parent(struct clk *clk, struct clk *parent)
{
	u32 value;
	int ret, i;

	if (!clk->parent_table || !clk->parent_num)
		return -EINVAL;

	/* Search the parent */
	for (i = 0; i < clk->parent_num; i++)
		if (clk->parent_table[i] == parent)
			break;

	if (i == clk->parent_num)
		return -ENODEV;

	ret = clk_reparent(clk, parent);
	if (ret < 0)
		return ret;

	value = __raw_readl(PLLC2CR) & ~(3 << 6);

	__raw_writel(value | (i << 6), PLLC2CR);

	/* Rebiuld the frequency table */
	pllc2_table_rebuild(clk);

	return 0;
}

static struct clk_ops pllc2_clk_ops = {
	.recalc		= pllc2_recalc,
	.round_rate	= pllc2_round_rate,
	.set_rate	= pllc2_set_rate,
	.enable		= pllc2_enable,
	.disable	= pllc2_disable,
	.set_parent	= pllc2_set_parent,
};

struct clk pllc2_clk = {
	.ops		= &pllc2_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
	.parent		= &extal1_div2_clk,
	.freq_table	= pllc2_freq_table,
	.parent_table	= pllc2_parent,
	.parent_num	= ARRAY_SIZE(pllc2_parent),
};

static struct clk *main_clks[] = {
	&dv_clki_clk,
	&r_clk,
	&sh7372_extal1_clk,
	&sh7372_extal2_clk,
	&dv_clki_div2_clk,
	&extal1_div2_clk,
	&extal2_div2_clk,
	&extal2_div4_clk,
	&pllc0_clk,
	&pllc1_clk,
	&pllc1_div2_clk,
	&pllc2_clk,
};

static void div4_kick(struct clk *clk)
{
	unsigned long value;

	/* set KICK bit in FRQCRB to update hardware setting */
	value = __raw_readl(FRQCRB);
	value |= (1 << 31);
	__raw_writel(value, FRQCRB);
}

static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
			  24, 32, 36, 48, 0, 72, 96, 0 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
	.kick = div4_kick,
};

enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
       DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
       DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
       DIV4_DDRP, DIV4_NR };

#define DIV4(_reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)

static struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
	[DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
	[DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
	[DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
	[DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
	[DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
	[DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
	[DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
	[DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
	[DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
	[DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
	[DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
	[DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
	[DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
};

enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
       DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU,
       DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
       DIV6_NR };

static struct clk div6_clks[DIV6_NR] = {
	[DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
	[DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
	[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
	[DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
	[DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
	[DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0),
	[DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0),
	[DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
	[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
	[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
	[DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
	[DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
	[DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
};

enum { DIV6_HDMI, DIV6_REPARENT_NR };

/* Indices are important - they are the actual src selecting values */
static struct clk *hdmi_parent[] = {
	[0] = &pllc1_div2_clk,
	[1] = &pllc2_clk,
	[2] = &dv_clki_clk,
	[3] = NULL,	/* pllc2_div4 not implemented yet */
};

static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
	[DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
				      hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
};

enum { MSTP001,
       MSTP131, MSTP130,
       MSTP129, MSTP128,
       MSTP118, MSTP117, MSTP116,
       MSTP106, MSTP101, MSTP100,
       MSTP223,
       MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
       MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
       MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
       MSTP_NR };

#define MSTP(_parent, _reg, _bit, _flags) \
  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)

static struct clk mstp_clks[MSTP_NR] = {
	[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
	[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
	[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
	[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
	[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
	[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
	[MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
	[MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
	[MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
	[MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
	[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
	[MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
	[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
	[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
	[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
	[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
	[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
	[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
	[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
	[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
	[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */
	[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
	[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
	[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
	[MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
	[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
	[MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
	[MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
	[MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
	[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
	[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
	[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
};

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }

static struct clk_lookup lookups[] = {
	/* main clocks */
	CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk),
	CLKDEV_CON_ID("r_clk", &r_clk),
	CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
	CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
	CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
	CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
	CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
	CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
	CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
	CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
	CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),

	/* DIV4 clocks */
	CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
	CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
	CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
	CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
	CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
	CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
	CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
	CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
	CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
	CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
	CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
	CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
	CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
	CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
	CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),

	/* DIV6 clocks */
	CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
	CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
	CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
	CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
	CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
	CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]),
	CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]),
	CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
	CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
	CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
	CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
	CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
	CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
	CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),

	/* MSTP32 clocks */
	CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
	CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
	CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
	CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
	CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
	CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
	CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
	CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
	CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
	CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
	CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
	CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
	CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
	CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
	CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP323]), /* USB0 */
	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
	CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
	CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
	CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
	CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
	CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
	CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
	{.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]},
};

void __init sh7372_clock_init(void)
{
	int k, ret = 0;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		clk_init();
	else
		panic("failed to setup sh7372 clocks\n");

}
Commit	Line	Data
495b3cea MD	1	/*
	2	* SH7372 clock framework support
	3	*
	4	* Copyright (C) 2010 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
495b3cea MD	21	#include <linux/io.h>
	22	#include <linux/sh_clk.h>
	23	#include <mach/common.h>
	24	#include <asm/clkdev.h>
	25
	26	/* SH7372 registers */
	27	#define FRQCRA 0xe6150000
	28	#define FRQCRB 0xe6150004
	29	#define FRQCRC 0xe61500e0
	30	#define FRQCRD 0xe61500e4
	31	#define VCLKCR1 0xe6150008
	32	#define VCLKCR2 0xe615000c
	33	#define VCLKCR3 0xe615001c
	34	#define FMSICKCR 0xe6150010
	35	#define FMSOCKCR 0xe6150014
	36	#define FSIACKCR 0xe6150018
	37	#define FSIBCKCR 0xe6150090
	38	#define SUBCKCR 0xe6150080
	39	#define SPUCKCR 0xe6150084
	40	#define VOUCKCR 0xe6150088
	41	#define HDMICKCR 0xe6150094
	42	#define DSITCKCR 0xe6150060
	43	#define DSI0PCKCR 0xe6150064
	44	#define DSI1PCKCR 0xe6150098
	45	#define PLLC01CR 0xe6150028
	46	#define PLLC2CR 0xe615002c
	47	#define SMSTPCR0 0xe6150130
	48	#define SMSTPCR1 0xe6150134
	49	#define SMSTPCR2 0xe6150138
	50	#define SMSTPCR3 0xe615013c
	51	#define SMSTPCR4 0xe6150140
	52
b90884c8 GL	53	/* Platforms must set frequency on their DV_CLKI pin */
	54	struct clk dv_clki_clk = {
	55	};
	56
495b3cea MD	57	/* Fixed 32 KHz root clock from EXTALR pin */
	58	static struct clk r_clk = {
	59	.rate = 32768,
	60	};
	61
	62	/*
	63	* 26MHz default rate for the EXTAL1 root input clock.
	64	* If needed, reset this with clk_set_rate() from the platform code.
	65	*/
83ca5c87	66	struct clk sh7372_extal1_clk = {
3b79bece	67	.rate = 26000000,
495b3cea MD	68	};
	69
	70	/*
	71	* 48MHz default rate for the EXTAL2 root input clock.
	72	* If needed, reset this with clk_set_rate() from the platform code.
	73	*/
83ca5c87	74	struct clk sh7372_extal2_clk = {
495b3cea MD	75	.rate = 48000000,
	76	};
	77
	78	/* A fixed divide-by-2 block */
	79	static unsigned long div2_recalc(struct clk *clk)
	80	{
	81	return clk->parent->rate / 2;
	82	}
	83
	84	static struct clk_ops div2_clk_ops = {
	85	.recalc = div2_recalc,
	86	};
	87
b90884c8 GL	88	/* Divide dv_clki by two */
	89	struct clk dv_clki_div2_clk = {
	90	.ops = &div2_clk_ops,
	91	.parent = &dv_clki_clk,
	92	};
	93
495b3cea MD	94	/* Divide extal1 by two */
	95	static struct clk extal1_div2_clk = {
	96	.ops = &div2_clk_ops,
83ca5c87	97	.parent = &sh7372_extal1_clk,
495b3cea MD	98	};
	99
	100	/* Divide extal2 by two */
	101	static struct clk extal2_div2_clk = {
	102	.ops = &div2_clk_ops,
83ca5c87	103	.parent = &sh7372_extal2_clk,
495b3cea MD	104	};
	105
	106	/* Divide extal2 by four */
	107	static struct clk extal2_div4_clk = {
	108	.ops = &div2_clk_ops,
	109	.parent = &extal2_div2_clk,
	110	};
	111
	112	/* PLLC0 and PLLC1 */
	113	static unsigned long pllc01_recalc(struct clk *clk)
	114	{
	115	unsigned long mult = 1;
	116
	117	if (__raw_readl(PLLC01CR) & (1 << 14))
	118	mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
	119
	120	return clk->parent->rate * mult;
	121	}
	122
	123	static struct clk_ops pllc01_clk_ops = {
	124	.recalc = pllc01_recalc,
	125	};
	126
	127	static struct clk pllc0_clk = {
	128	.ops = &pllc01_clk_ops,
	129	.flags = CLK_ENABLE_ON_INIT,
	130	.parent = &extal1_div2_clk,
	131	.enable_reg = (void __iomem *)FRQCRC,
	132	};
	133
	134	static struct clk pllc1_clk = {
	135	.ops = &pllc01_clk_ops,
	136	.flags = CLK_ENABLE_ON_INIT,
	137	.parent = &extal1_div2_clk,
	138	.enable_reg = (void __iomem *)FRQCRA,
	139	};
	140
	141	/* Divide PLLC1 by two */
	142	static struct clk pllc1_div2_clk = {
	143	.ops = &div2_clk_ops,
	144	.parent = &pllc1_clk,
	145	};
	146
	147	/* PLLC2 */
b90884c8 GL	148
	149	/* Indices are important - they are the actual src selecting values */
	150	static struct clk *pllc2_parent[] = {
	151	[0] = &extal1_div2_clk,
	152	[1] = &extal2_div2_clk,
	153	[2] = &dv_clki_div2_clk,
	154	};
	155
	156	/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
	157	static struct cpufreq_frequency_table pllc2_freq_table[29];
	158
	159	static void pllc2_table_rebuild(struct clk *clk)
	160	{
	161	int i;
	162
	163	/* Initialise PLLC2 frequency table */
	164	for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
	165	pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
	166	pllc2_freq_table[i].index = i;
	167	}
	168
	169	/* This is a special entry - switching PLL off makes it a repeater */
	170	pllc2_freq_table[i].frequency = clk->parent->rate;
	171	pllc2_freq_table[i].index = i;
	172
	173	pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
	174	pllc2_freq_table[i].index = i;
	175	}
	176
495b3cea MD	177	static unsigned long pllc2_recalc(struct clk *clk)
	178	{
	179	unsigned long mult = 1;
	180
b90884c8 GL	181	pllc2_table_rebuild(clk);
	182
	183	/*
	184	* If the PLL is off, mult == 1, clk->rate will be updated in
	185	* pllc2_enable().
	186	*/
495b3cea MD	187	if (__raw_readl(PLLC2CR) & (1 << 31))
	188	mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
	189
	190	return clk->parent->rate * mult;
	191	}
	192
b90884c8 GL	193	static long pllc2_round_rate(struct clk *clk, unsigned long rate)
	194	{
	195	return clk_rate_table_round(clk, clk->freq_table, rate);
	196	}
	197
	198	static int pllc2_enable(struct clk *clk)
	199	{
	200	int i;
	201
	202	__raw_writel(__raw_readl(PLLC2CR) \| 0x80000000, PLLC2CR);
	203
	204	for (i = 0; i < 100; i++)
	205	if (__raw_readl(PLLC2CR) & 0x80000000) {
	206	clk->rate = pllc2_recalc(clk);
	207	return 0;
	208	}
	209
	210	pr_err("%s(): timeout!\n", __func__);
	211
	212	return -ETIMEDOUT;
	213	}
	214
	215	static void pllc2_disable(struct clk *clk)
	216	{
	217	__raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
	218	}
	219
	220	static int pllc2_set_rate(struct clk *clk,
	221	unsigned long rate, int algo_id)
	222	{
	223	unsigned long value;
	224	int idx;
	225
	226	idx = clk_rate_table_find(clk, clk->freq_table, rate);
	227	if (idx < 0)
	228	return idx;
	229
	230	if (rate == clk->parent->rate) {
	231	pllc2_disable(clk);
	232	return 0;
	233	}
	234
	235	value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
	236
	237	if (value & 0x80000000)
	238	pllc2_disable(clk);
	239
	240	__raw_writel((value & ~0x80000000) \| ((idx + 19) << 24), PLLC2CR);
	241
	242	if (value & 0x80000000)
	243	return pllc2_enable(clk);
	244
	245	return 0;
	246	}
	247
	248	static int pllc2_set_parent(struct clk clk, struct clk parent)
	249	{
	250	u32 value;
	251	int ret, i;
	252
	253	if (!clk->parent_table \|\| !clk->parent_num)
	254	return -EINVAL;
	255
	256	/* Search the parent */
257	for (i = 0; i < clk->parent_num; i++)
258	if (clk->parent_table[i] == parent)
259	break;
260
261	if (i == clk->parent_num)
262	return -ENODEV;
263
264	ret = clk_reparent(clk, parent);
265	if (ret < 0)
266	return ret;
267
268	value = __raw_readl(PLLC2CR) & ~(3 << 6);
269
270	__raw_writel(value \| (i << 6), PLLC2CR);
271
272	/* Rebiuld the frequency table */
273	pllc2_table_rebuild(clk);
274
275	return 0;
276	}
277
495b3cea MD	278	static struct clk_ops pllc2_clk_ops = {
495b3cea MD	279	.recalc = pllc2_recalc,
b90884c8 GL	280	.round_rate = pllc2_round_rate,
	281	.set_rate = pllc2_set_rate,
	282	.enable = pllc2_enable,
	283	.disable = pllc2_disable,
	284	.set_parent = pllc2_set_parent,
495b3cea MD	285	};
495b3cea MD	286
b90884c8	287	struct clk pllc2_clk = {
495b3cea MD	288	.ops = &pllc2_clk_ops,
	289	.flags = CLK_ENABLE_ON_INIT,
	290	.parent = &extal1_div2_clk,
b90884c8 GL	291	.freq_table = pllc2_freq_table,
	292	.parent_table = pllc2_parent,
	293	.parent_num = ARRAY_SIZE(pllc2_parent),
495b3cea MD	294	};
495b3cea MD	295
83ca5c87	296	static struct clk *main_clks[] = {
b90884c8	297	&dv_clki_clk,
495b3cea	298	&r_clk,
83ca5c87 MD	299	&sh7372_extal1_clk,
83ca5c87 MD	300	&sh7372_extal2_clk,
b90884c8	301	&dv_clki_div2_clk,
495b3cea MD	302	&extal1_div2_clk,
	303	&extal2_div2_clk,
	304	&extal2_div4_clk,
	305	&pllc0_clk,
	306	&pllc1_clk,
	307	&pllc1_div2_clk,
	308	&pllc2_clk,
	309	};
	310
	311	static void div4_kick(struct clk *clk)
	312	{
	313	unsigned long value;
	314
	315	/* set KICK bit in FRQCRB to update hardware setting */
	316	value = __raw_readl(FRQCRB);
	317	value \|= (1 << 31);
	318	__raw_writel(value, FRQCRB);
	319	}
	320
	321	static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
	322	24, 32, 36, 48, 0, 72, 96, 0 };
	323
	324	static struct clk_div_mult_table div4_div_mult_table = {
	325	.divisors = divisors,
	326	.nr_divisors = ARRAY_SIZE(divisors),
	327	};
	328
	329	static struct clk_div4_table div4_table = {
	330	.div_mult_table = &div4_div_mult_table,
	331	.kick = div4_kick,
	332	};
	333
	334	enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
	335	DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
	336	DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
	337	DIV4_DDRP, DIV4_NR };
	338
	339	#define DIV4(_reg, _bit, _mask, _flags) \
	340	SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
	341
83ca5c87	342	static struct clk div4_clks[DIV4_NR] = {
495b3cea MD	343	[DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
	344	[DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
	345	[DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
	346	[DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
	347	[DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
	348	[DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
	349	[DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
	350	[DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
	351	[DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
	352	[DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
	353	[DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
	354	[DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
	355	[DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
	356	[DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
	357	[DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
	358	};
	359
	360	enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
	361	DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU,
b90884c8	362	DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
495b3cea MD	363	DIV6_NR };
495b3cea MD	364
83ca5c87	365	static struct clk div6_clks[DIV6_NR] = {
495b3cea MD	366	[DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
	367	[DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
	368	[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
	369	[DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
	370	[DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
	371	[DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0),
	372	[DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0),
83ca5c87	373	[DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
495b3cea MD	374	[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
495b3cea MD	375	[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
495b3cea MD	376	[DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
	377	[DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
	378	[DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
	379	};
	380
b90884c8 GL	381	enum { DIV6_HDMI, DIV6_REPARENT_NR };
	382
	383	/* Indices are important - they are the actual src selecting values */
	384	static struct clk *hdmi_parent[] = {
	385	[0] = &pllc1_div2_clk,
	386	[1] = &pllc2_clk,
	387	[2] = &dv_clki_clk,
	388	[3] = NULL, /* pllc2_div4 not implemented yet */
	389	};
	390
	391	static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
	392	[DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
	393	hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
	394	};
	395
495b3cea	396	enum { MSTP001,
d473e0a5 GL	397	MSTP131, MSTP130,
	398	MSTP129, MSTP128,
	399	MSTP118, MSTP117, MSTP116,
	400	MSTP106, MSTP101, MSTP100,
495b3cea MD	401	MSTP223,
495b3cea MD	402	MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
21a89344	403	MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
b90884c8	404	MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
495b3cea MD	405	MSTP_NR };
	406
	407	#define MSTP(_parent, _reg, _bit, _flags) \
	408	SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
	409
	410	static struct clk mstp_clks[MSTP_NR] = {
	411	[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
	412	[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
	413	[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
	414	[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
	415	[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
6e86ccad GL	416	[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
6e86ccad GL	417	[MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
495b3cea MD	418	[MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
	419	[MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
	420	[MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
d473e0a5	421	[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
495b3cea MD	422	[MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
	423	[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
	424	[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
	425	[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
	426	[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
	427	[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
	428	[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
	429	[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
	430	[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
f14c4f14	431	[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */
495b3cea MD	432	[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
	433	[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
	434	[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
	435	[MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
21a89344	436	[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
495b3cea	437	[MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
b90884c8	438	[MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
495b3cea MD	439	[MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
	440	[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
	441	[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
	442	[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
	443	};
	444
	445	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
	446	#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
	447
	448	static struct clk_lookup lookups[] = {
	449	/* main clocks */
b90884c8	450	CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk),
495b3cea	451	CLKDEV_CON_ID("r_clk", &r_clk),
83ca5c87 MD	452	CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
83ca5c87 MD	453	CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
495b3cea MD	454	CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
	455	CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
	456	CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
	457	CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
	458	CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
	459	CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
	460	CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
	461
	462	/* DIV4 clocks */
	463	CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
	464	CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
	465	CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
	466	CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
	467	CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
	468	CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
	469	CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
	470	CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
	471	CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
	472	CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
	473	CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
	474	CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
	475	CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
	476	CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
	477	CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
	478
	479	/* DIV6 clocks */
	480	CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
	481	CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
	482	CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
	483	CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
	484	CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
	485	CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]),
	486	CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]),
	487	CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
	488	CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
	489	CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
b90884c8	490	CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
495b3cea MD	491	CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
	492	CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
	493	CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
	494
	495	/* MSTP32 clocks */
	496	CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
83ca5c87 MD	497	CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
	498	CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
	499	CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
	500	CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
d473e0a5 GL	501	CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
d473e0a5 GL	502	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
495b3cea MD	503	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
	504	CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
	505	CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
d473e0a5	506	CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
495b3cea MD	507	CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
	508	CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
	509	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
	510	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
	511	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
	512	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
	513	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
	514	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
	515	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
	516	CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
9848f2f3	517	CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
495b3cea MD	518	CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
	519	CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
	520	CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP323]), /* USB0 */
	521	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
	522	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
21a89344	523	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
495b3cea	524	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
b90884c8	525	CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
495b3cea MD	526	CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
	527	CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
	528	CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
	529	CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
	530	CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
b90884c8	531	{.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]},
495b3cea MD	532	};
	533
	534	void __init sh7372_clock_init(void)
	535	{
	536	int k, ret = 0;
	537
	538	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	539	ret = clk_register(main_clks[k]);
	540
	541	if (!ret)
	542	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	543
	544	if (!ret)
	545	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
	546
b90884c8 GL	547	if (!ret)
	548	ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR);
	549
495b3cea MD	550	if (!ret)
	551	ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
	552
	553	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
	554
	555	if (!ret)
	556	clk_init();
	557	else
	558	panic("failed to setup sh7372 clocks\n");
	559
	560	}