[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-shmobile / platsmp-apmu.c

/*
 * SMP support for SoCs with APMU
 *
 * Copyright (C) 2014  Renesas Electronics Corporation
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/cpu_pm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/of_address.h>
#include <linux/smp.h>
#include <linux/suspend.h>
#include <linux/threads.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/proc-fns.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include "common.h"
#include "platsmp-apmu.h"
#include "rcar-gen2.h"

static struct {
	void __iomem *iomem;
	int bit;
} apmu_cpus[NR_CPUS];

#define WUPCR_OFFS	 0x10		/* Wake Up Control Register */
#define PSTR_OFFS	 0x40		/* Power Status Register */
#define CPUNCR_OFFS(n)	(0x100 + (0x10 * (n)))
					/* CPUn Power Status Control Register */
#define DBGRCR_OFFS	0x180		/* Debug Resource Reset Control Reg. */

/* Power Status Register */
#define CPUNST(r, n)	(((r) >> (n * 4)) & 3)	/* CPUn Status Bit */
#define CPUST_RUN	0		/* Run Mode */
#define CPUST_STANDBY	3		/* CoreStandby Mode */

/* Debug Resource Reset Control Register */
#define DBGCPUREN	BIT(24)		/* CPU Other Reset Request Enable */
#define DBGCPUNREN(n)	BIT((n) + 20)	/* CPUn Reset Request Enable */
#define DBGCPUPREN	BIT(19)		/* CPU Peripheral Reset Req. Enable */

static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
{
	/* request power on */
	writel_relaxed(BIT(bit), p + WUPCR_OFFS);

	/* wait for APMU to finish */
	while (readl_relaxed(p + WUPCR_OFFS) != 0)
		;

	return 0;
}

static int __maybe_unused apmu_power_off(void __iomem *p, int bit)
{
	/* request Core Standby for next WFI */
	writel_relaxed(3, p + CPUNCR_OFFS(bit));
	return 0;
}

static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
{
	int k;

	for (k = 0; k < 1000; k++) {
		if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY)
			return 1;

		mdelay(1);
	}

	return 0;
}

static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
{
	void __iomem *p = apmu_cpus[cpu].iomem;

	return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
}

#ifdef CONFIG_SMP
static void apmu_init_cpu(struct resource *res, int cpu, int bit)
{
	u32 x;

	if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
		return;

	apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
	apmu_cpus[cpu].bit = bit;

	pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);

	/* Setup for debug mode */
	x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS);
	x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN;
	writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);
}

static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
			   struct rcar_apmu_config *apmu_config, int num)
{
	int id;
	int k;
	int bit, index;
	bool is_allowed;

	for (k = 0; k < num; k++) {
		/* only enable the cluster that includes the boot CPU */
		is_allowed = false;
		for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
			id = apmu_config[k].cpus[bit];
			if (id >= 0) {
				if (id == cpu_logical_map(0))
					is_allowed = true;
			}
		}
		if (!is_allowed)
			continue;

		for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
			id = apmu_config[k].cpus[bit];
			if (id >= 0) {
				index = get_logical_index(id);
				if (index >= 0)
					fn(&apmu_config[k].iomem, index, bit);
			}
		}
	}
}

static const struct of_device_id apmu_ids[] = {
	{ .compatible = "renesas,apmu" },
	{ /*sentinel*/ }
};

static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
{
	struct device_node *np_apmu, *np_cpu;
	struct resource res;
	int bit, index;
	u32 id;

	for_each_matching_node(np_apmu, apmu_ids) {
		/* only enable the cluster that includes the boot CPU */
		bool is_allowed = false;

		for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
			np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
			if (np_cpu) {
				if (!of_property_read_u32(np_cpu, "reg", &id)) {
					if (id == cpu_logical_map(0)) {
						is_allowed = true;
						of_node_put(np_cpu);
						break;
					}

				}
				of_node_put(np_cpu);
			}
		}
		if (!is_allowed)
			continue;

		for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
			np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
			if (np_cpu) {
				if (!of_property_read_u32(np_cpu, "reg", &id)) {
					index = get_logical_index(id);
					if ((index >= 0) &&
					    !of_address_to_resource(np_apmu,
								    0, &res))
						fn(&res, index, bit);
				}
				of_node_put(np_cpu);
			}
		}
	}
}

static void __init shmobile_smp_apmu_setup_boot(void)
{
	/* install boot code shared by all CPUs */
	shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
}

void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
					   struct rcar_apmu_config *apmu_config,
					   int num)
{
	shmobile_smp_apmu_setup_boot();
	apmu_parse_cfg(apmu_init_cpu, apmu_config, num);
}

int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	/* For this particular CPU register boot vector */
	shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);

	return apmu_wrap(cpu, apmu_power_on);
}

static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
{
	shmobile_smp_apmu_setup_boot();
	apmu_parse_dt(apmu_init_cpu);
	rcar_gen2_pm_init();
}

static struct smp_operations apmu_smp_ops __initdata = {
	.smp_prepare_cpus	= shmobile_smp_apmu_prepare_cpus_dt,
	.smp_boot_secondary	= shmobile_smp_apmu_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_can_disable	= shmobile_smp_cpu_can_disable,
	.cpu_die		= shmobile_smp_apmu_cpu_die,
	.cpu_kill		= shmobile_smp_apmu_cpu_kill,
#endif
};

CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops);
#endif /* CONFIG_SMP */

#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND)
/* nicked from arch/arm/mach-exynos/hotplug.c */
static inline void cpu_enter_lowpower_a15(void)
{
	unsigned int v;

	asm volatile(
	"       mrc     p15, 0, %0, c1, c0, 0\n"
	"       bic     %0, %0, %1\n"
	"       mcr     p15, 0, %0, c1, c0, 0\n"
		: "=&r" (v)
		: "Ir" (CR_C)
		: "cc");

	flush_cache_louis();

	asm volatile(
	/*
	 * Turn off coherency
	 */
	"       mrc     p15, 0, %0, c1, c0, 1\n"
	"       bic     %0, %0, %1\n"
	"       mcr     p15, 0, %0, c1, c0, 1\n"
		: "=&r" (v)
		: "Ir" (0x40)
		: "cc");

	isb();
	dsb();
}

static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)
{

	/* Select next sleep mode using the APMU */
	apmu_wrap(cpu, apmu_power_off);

	/* Do ARM specific CPU shutdown */
	cpu_enter_lowpower_a15();
}

static inline void cpu_leave_lowpower(void)
{
	unsigned int v;

	asm volatile("mrc    p15, 0, %0, c1, c0, 0\n"
		     "       orr     %0, %0, %1\n"
		     "       mcr     p15, 0, %0, c1, c0, 0\n"
		     "       mrc     p15, 0, %0, c1, c0, 1\n"
		     "       orr     %0, %0, %2\n"
		     "       mcr     p15, 0, %0, c1, c0, 1\n"
		     : "=&r" (v)
		     : "Ir" (CR_C), "Ir" (0x40)
		     : "cc");
}
#endif

#if defined(CONFIG_HOTPLUG_CPU)
void shmobile_smp_apmu_cpu_die(unsigned int cpu)
{
	/* For this particular CPU deregister boot vector */
	shmobile_smp_hook(cpu, 0, 0);

	/* Shutdown CPU core */
	shmobile_smp_apmu_cpu_shutdown(cpu);

	/* jump to shared mach-shmobile sleep / reset code */
	shmobile_smp_sleep();
}

int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
{
	return apmu_wrap(cpu, apmu_power_off_poll);
}
#endif

#if defined(CONFIG_SUSPEND)
static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
{
	shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
	shmobile_smp_apmu_cpu_shutdown(cpu);
	cpu_do_idle(); /* WFI selects Core Standby */
	return 1;
}

static int shmobile_smp_apmu_enter_suspend(suspend_state_t state)
{
	cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend);
	cpu_leave_lowpower();
	return 0;
}

void __init shmobile_smp_apmu_suspend_init(void)
{
	shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
}
#endif
Commit	Line	Data
a112de8c MD	1	/*
	2	* SMP support for SoCs with APMU
	3	*
a8d2ff39	4	* Copyright (C) 2014 Renesas Electronics Corporation
a112de8c MD	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
d6d757c9	11	#include <linux/cpu_pm.h>
a112de8c MD	12	#include <linux/delay.h>
	13	#include <linux/init.h>
	14	#include <linux/io.h>
	15	#include <linux/ioport.h>
	16	#include <linux/of_address.h>
	17	#include <linux/smp.h>
d6d757c9	18	#include <linux/suspend.h>
784500be	19	#include <linux/threads.h>
a112de8c MD	20	#include <asm/cacheflush.h>
a112de8c MD	21	#include <asm/cp15.h>
d6d757c9	22	#include <asm/proc-fns.h>
a112de8c	23	#include <asm/smp_plat.h>
d6d757c9	24	#include <asm/suspend.h>
fd44aa5e	25	#include "common.h"
a8d2ff39	26	#include "platsmp-apmu.h"
5f3bca0d	27	#include "rcar-gen2.h"
a112de8c MD	28
	29	static struct {
	30	void __iomem *iomem;
	31	int bit;
784500be	32	} apmu_cpus[NR_CPUS];
a112de8c	33
460d4117 GU	34	#define WUPCR_OFFS 0x10 /* Wake Up Control Register */
	35	#define PSTR_OFFS 0x40 /* Power Status Register */
	36	#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
	37	/* CPUn Power Status Control Register */
10f778a9	38	#define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */
460d4117 GU	39
	40	/* Power Status Register */
	41	#define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */
	42	#define CPUST_RUN 0 /* Run Mode */
	43	#define CPUST_STANDBY 3 /* CoreStandby Mode */
a112de8c	44
10f778a9 GU	45	/* Debug Resource Reset Control Register */
	46	#define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */
	47	#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */
	48	#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */
	49
784500be	50	static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
a112de8c MD	51	{
	52	/* request power on */
	53	writel_relaxed(BIT(bit), p + WUPCR_OFFS);
	54
	55	/* wait for APMU to finish */
	56	while (readl_relaxed(p + WUPCR_OFFS) != 0)
	57	;
	58
	59	return 0;
	60	}
	61
151dd346	62	static int __maybe_unused apmu_power_off(void __iomem *p, int bit)
a112de8c MD	63	{
	64	/* request Core Standby for next WFI */
	65	writel_relaxed(3, p + CPUNCR_OFFS(bit));
	66	return 0;
	67	}
	68
784500be	69	static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
a112de8c MD	70	{
	71	int k;
	72
	73	for (k = 0; k < 1000; k++) {
460d4117	74	if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY)
a112de8c MD	75	return 1;
	76
	77	mdelay(1);
	78	}
	79
	80	return 0;
	81	}
	82
151dd346	83	static int __maybe_unused apmu_wrap(int cpu, int (fn)(void __iomem p, int cpu))
a112de8c MD	84	{
	85	void __iomem *p = apmu_cpus[cpu].iomem;
	86
	87	return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
	88	}
	89
d3f3fb0c	90	#ifdef CONFIG_SMP
a112de8c MD	91	static void apmu_init_cpu(struct resource *res, int cpu, int bit)
a112de8c MD	92	{
10f778a9 GU	93	u32 x;
10f778a9 GU	94
784500be	95	if ((cpu >= ARRAY_SIZE(apmu_cpus)) \|\| apmu_cpus[cpu].iomem)
a112de8c MD	96	return;
	97
	98	apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
	99	apmu_cpus[cpu].bit = bit;
	100
56ff8731	101	pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
10f778a9 GU	102
	103	/* Setup for debug mode */
	104	x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS);
	105	x \|= DBGCPUREN \| DBGCPUNREN(bit) \| DBGCPUPREN;
	106	writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);
a112de8c MD	107	}
a112de8c MD	108
a8d2ff39 HN	109	static void apmu_parse_cfg(void (fn)(struct resource res, int cpu, int bit),
a8d2ff39 HN	110	struct rcar_apmu_config *apmu_config, int num)
a112de8c	111	{
6e67d2cc	112	int id;
a112de8c MD	113	int k;
a112de8c MD	114	int bit, index;
ee490bcc	115	bool is_allowed;
a112de8c	116
a8d2ff39	117	for (k = 0; k < num; k++) {
ee490bcc MD	118	/* only enable the cluster that includes the boot CPU */
	119	is_allowed = false;
	120	for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
	121	id = apmu_config[k].cpus[bit];
	122	if (id >= 0) {
	123	if (id == cpu_logical_map(0))
	124	is_allowed = true;
	125	}
	126	}
	127	if (!is_allowed)
	128	continue;
	129
a112de8c MD	130	for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
	131	id = apmu_config[k].cpus[bit];
	132	if (id >= 0) {
	133	index = get_logical_index(id);
	134	if (index >= 0)
	135	fn(&apmu_config[k].iomem, index, bit);
	136	}
	137	}
	138	}
	139	}
	140
5f3bca0d MD	141	static const struct of_device_id apmu_ids[] = {
	142	{ .compatible = "renesas,apmu" },
	143	{ /sentinel/ }
	144	};
	145
	146	static void apmu_parse_dt(void (fn)(struct resource res, int cpu, int bit))
	147	{
	148	struct device_node np_apmu, np_cpu;
	149	struct resource res;
	150	int bit, index;
	151	u32 id;
	152
	153	for_each_matching_node(np_apmu, apmu_ids) {
	154	/* only enable the cluster that includes the boot CPU */
	155	bool is_allowed = false;
	156
	157	for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
	158	np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
	159	if (np_cpu) {
	160	if (!of_property_read_u32(np_cpu, "reg", &id)) {
	161	if (id == cpu_logical_map(0)) {
	162	is_allowed = true;
	163	of_node_put(np_cpu);
	164	break;
	165	}
	166
	167	}
	168	of_node_put(np_cpu);
	169	}
	170	}
	171	if (!is_allowed)
	172	continue;
	173
	174	for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
	175	np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
	176	if (np_cpu) {
	177	if (!of_property_read_u32(np_cpu, "reg", &id)) {
	178	index = get_logical_index(id);
	179	if ((index >= 0) &&
	180	!of_address_to_resource(np_apmu,
	181	0, &res))
	182	fn(&res, index, bit);
	183	}
	184	of_node_put(np_cpu);
	185	}
	186	}
	187	}
	188	}
	189
	190	static void __init shmobile_smp_apmu_setup_boot(void)
a112de8c MD	191	{
a112de8c MD	192	/* install boot code shared by all CPUs */
64fc2a94	193	shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
5f3bca0d	194	}
a112de8c	195
5f3bca0d MD	196	void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
	197	struct rcar_apmu_config *apmu_config,
	198	int num)
	199	{
	200	shmobile_smp_apmu_setup_boot();
a8d2ff39	201	apmu_parse_cfg(apmu_init_cpu, apmu_config, num);
a112de8c MD	202	}
	203
	204	int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
	205	{
	206	/* For this particular CPU register boot vector */
64fc2a94	207	shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);
a112de8c MD	208
	209	return apmu_wrap(cpu, apmu_power_on);
	210	}
5f3bca0d MD	211
	212	static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
	213	{
	214	shmobile_smp_apmu_setup_boot();
	215	apmu_parse_dt(apmu_init_cpu);
	216	rcar_gen2_pm_init();
	217	}
	218
5f3bca0d MD	219	static struct smp_operations apmu_smp_ops __initdata = {
5f3bca0d MD	220	.smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt,
d03c8f78	221	.smp_boot_secondary = shmobile_smp_apmu_boot_secondary,
5f3bca0d MD	222	#ifdef CONFIG_HOTPLUG_CPU
	223	.cpu_can_disable = shmobile_smp_cpu_can_disable,
	224	.cpu_die = shmobile_smp_apmu_cpu_die,
	225	.cpu_kill = shmobile_smp_apmu_cpu_kill,
784500be	226	#endif
5f3bca0d MD	227	};
	228
	229	CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops);
	230	#endif /* CONFIG_SMP */
a112de8c	231
d6d757c9	232	#if defined(CONFIG_HOTPLUG_CPU) \|\| defined(CONFIG_SUSPEND)
a112de8c MD	233	/* nicked from arch/arm/mach-exynos/hotplug.c */
	234	static inline void cpu_enter_lowpower_a15(void)
	235	{
	236	unsigned int v;
	237
	238	asm volatile(
	239	" mrc p15, 0, %0, c1, c0, 0\n"
	240	" bic %0, %0, %1\n"
	241	" mcr p15, 0, %0, c1, c0, 0\n"
	242	: "=&r" (v)
	243	: "Ir" (CR_C)
	244	: "cc");
	245
	246	flush_cache_louis();
	247
	248	asm volatile(
	249	/*
	250	* Turn off coherency
	251	*/
	252	" mrc p15, 0, %0, c1, c0, 1\n"
	253	" bic %0, %0, %1\n"
	254	" mcr p15, 0, %0, c1, c0, 1\n"
	255	: "=&r" (v)
	256	: "Ir" (0x40)
	257	: "cc");
	258
	259	isb();
	260	dsb();
	261	}
	262
54245073	263	static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)
a112de8c	264	{
a112de8c MD	265
	266	/* Select next sleep mode using the APMU */
	267	apmu_wrap(cpu, apmu_power_off);
	268
	269	/* Do ARM specific CPU shutdown */
	270	cpu_enter_lowpower_a15();
d6d757c9	271	}
	272
	273	static inline void cpu_leave_lowpower(void)
	274	{
	275	unsigned int v;
	276
	277	asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
	278	" orr %0, %0, %1\n"
	279	" mcr p15, 0, %0, c1, c0, 0\n"
	280	" mrc p15, 0, %0, c1, c0, 1\n"
	281	" orr %0, %0, %2\n"
	282	" mcr p15, 0, %0, c1, c0, 1\n"
	283	: "=&r" (v)
	284	: "Ir" (CR_C), "Ir" (0x40)
	285	: "cc");
	286	}
	287	#endif
	288
	289	#if defined(CONFIG_HOTPLUG_CPU)
	290	void shmobile_smp_apmu_cpu_die(unsigned int cpu)
	291	{
	292	/* For this particular CPU deregister boot vector */
	293	shmobile_smp_hook(cpu, 0, 0);
	294
	295	/* Shutdown CPU core */
	296	shmobile_smp_apmu_cpu_shutdown(cpu);
a112de8c MD	297
	298	/* jump to shared mach-shmobile sleep / reset code */
	299	shmobile_smp_sleep();
	300	}
	301
	302	int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
	303	{
	304	return apmu_wrap(cpu, apmu_power_off_poll);
	305	}
	306	#endif
d6d757c9	307
	308	#if defined(CONFIG_SUSPEND)
	309	static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
	310	{
64fc2a94	311	shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
d6d757c9	312	shmobile_smp_apmu_cpu_shutdown(cpu);
	313	cpu_do_idle(); /* WFI selects Core Standby */
	314	return 1;
	315	}
	316
	317	static int shmobile_smp_apmu_enter_suspend(suspend_state_t state)
	318	{
	319	cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend);
	320	cpu_leave_lowpower();
	321	return 0;
	322	}
	323
0d77c9aa	324	void __init shmobile_smp_apmu_suspend_init(void)
d6d757c9	325	{
	326	shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
	327	}
d6d757c9	328	#endif