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ARM: shmobile: Add r8a7740 Maximum CPU Frequency to DTS
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-shmobile / setup-r8a7740.c
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6c01ba44
KM		 1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
6831f3a9 20#include <linux/delay.h>
3841e6f5 21#include <linux/dma-mapping.h>
6c01ba44
KM		 22#include <linux/kernel.h>
23#include <linux/init.h>
6831f3a9 24#include <linux/io.h>
70e3f3d4
KM		 25#include <linux/irqchip.h>
26#include <linux/irqchip/arm-gic.h>
0b7d7820 27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
6c01ba44 28#include <linux/platform_device.h>
755d57b2 29#include <linux/of_platform.h>
6c01ba44 30#include <linux/serial_sci.h>
643c3307 31#include <linux/sh_dma.h>
6c01ba44 32#include <linux/sh_timer.h>
f671e022 33#include <linux/platform_data/sh_ipmmu.h>
d7de938f 34#include <mach/dma-register.h>
6c01ba44 35#include <mach/r8a7740.h>
8459293c 36#include <mach/pm-rmobile.h>
d3ab7221 37#include <mach/common.h>
250a2723 38#include <mach/irqs.h>
6c01ba44 39#include <asm/mach-types.h>
d3ab7221 40#include <asm/mach/map.h>
6c01ba44 41#include <asm/mach/arch.h>
23e5bc03 42#include <asm/mach/time.h>
6c01ba44 43
d3ab7221
MD		 44static struct map_desc r8a7740_io_desc[] __initdata = {
45 /*
46 * for CPGA/INTC/PFC
47 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
48 */
49 {
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
52 .length = 160 << 20,
53 .type = MT_DEVICE_NONSHARED
54 },
55#ifdef CONFIG_CACHE_L2X0
56 /*
57 * for l2x0_init()
58 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
59 */
60 {
61 .virtual = 0xf0002000,
62 .pfn = __phys_to_pfn(0xf0100000),
63 .length = PAGE_SIZE,
64 .type = MT_DEVICE_NONSHARED
65 },
66#endif
67};
68
69void __init r8a7740_map_io(void)
70{
71 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
72}
73
02b01adb 74/* PFC */
3404622a
MD		 75static const struct resource pfc_resources[] = {
76 DEFINE_RES_MEM(0xe6050000, 0x8000),
77 DEFINE_RES_MEM(0xe605800c, 0x0020),
02b01adb
LP		 78};
79
80void __init r8a7740_pinmux_init(void)
81{
3404622a
MD		 82 platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
83 ARRAY_SIZE(pfc_resources));
02b01adb
LP		 84}
85
0b7d7820
BH		 86static struct renesas_intc_irqpin_config irqpin0_platform_data = {
87 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
88};
89
90static struct resource irqpin0_resources[] = {
91 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
92 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
93 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
94 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
95 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
96 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
97 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
98 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
99 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
100 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
101 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
102 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
103 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
104};
105
106static struct platform_device irqpin0_device = {
107 .name = "renesas_intc_irqpin",
108 .id = 0,
109 .resource = irqpin0_resources,
110 .num_resources = ARRAY_SIZE(irqpin0_resources),
111 .dev = {
112 .platform_data = &irqpin0_platform_data,
113 },
114};
115
116static struct renesas_intc_irqpin_config irqpin1_platform_data = {
117 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
118};
119
120static struct resource irqpin1_resources[] = {
121 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
122 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
123 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
124 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
125 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
126 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
127 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
128 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
129 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
130 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
131 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
132 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
133 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
134};
135
136static struct platform_device irqpin1_device = {
137 .name = "renesas_intc_irqpin",
138 .id = 1,
139 .resource = irqpin1_resources,
140 .num_resources = ARRAY_SIZE(irqpin1_resources),
141 .dev = {
142 .platform_data = &irqpin1_platform_data,
143 },
144};
145
146static struct renesas_intc_irqpin_config irqpin2_platform_data = {
147 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
148};
149
150static struct resource irqpin2_resources[] = {
151 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
152 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
153 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
154 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
155 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
156 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
157 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
158 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
159 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
160 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
161 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
162 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
163 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
164};
165
166static struct platform_device irqpin2_device = {
167 .name = "renesas_intc_irqpin",
168 .id = 2,
169 .resource = irqpin2_resources,
170 .num_resources = ARRAY_SIZE(irqpin2_resources),
171 .dev = {
172 .platform_data = &irqpin2_platform_data,
173 },
174};
175
176static struct renesas_intc_irqpin_config irqpin3_platform_data = {
177 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
178};
179
180static struct resource irqpin3_resources[] = {
181 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
182 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
183 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
184 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
185 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
186 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
187 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
188 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
189 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
190 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
191 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
192 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
193 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
194};
195
196static struct platform_device irqpin3_device = {
197 .name = "renesas_intc_irqpin",
198 .id = 3,
199 .resource = irqpin3_resources,
200 .num_resources = ARRAY_SIZE(irqpin3_resources),
201 .dev = {
202 .platform_data = &irqpin3_platform_data,
203 },
204};
205
c9e06d8e
LP		 206/* SCIF */
207#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
208static struct plat_sci_port scif##index##_platform_data = { \
209 .type = scif_type, \
c9e06d8e 210 .flags = UPF_BOOT_AUTOCONF, \
c9e06d8e
LP		 211 .scscr = SCSCR_RE | SCSCR_TE, \
212}; \
213 \
8bf2f8c5
LP		 214static struct resource scif##index##_resources[] = { \
215 DEFINE_RES_MEM(baseaddr, 0x100), \
216 DEFINE_RES_IRQ(irq), \
217}; \
218 \
c9e06d8e
LP		 219static struct platform_device scif##index##_device = { \
220 .name = "sh-sci", \
221 .id = index, \
8bf2f8c5
LP		 222 .resource = scif##index##_resources, \
223 .num_resources = ARRAY_SIZE(scif##index##_resources), \
c9e06d8e
LP		 224 .dev = { \
225 .platform_data = &scif##index##_platform_data, \
226 }, \
227}
6c01ba44 228
c9e06d8e
LP		 229R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
230R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
231R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
232R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
233R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
234R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
235R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
236R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
237R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
6c01ba44
KM		 238
239/* CMT */
240static struct sh_timer_config cmt10_platform_data = {
241 .name = "CMT10",
242 .channel_offset = 0x10,
243 .timer_bit = 0,
244 .clockevent_rating = 125,
245 .clocksource_rating = 125,
246};
247
248static struct resource cmt10_resources[] = {
249 [0] = {
250 .name = "CMT10",
251 .start = 0xe6138010,
252 .end = 0xe613801b,
253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
0b7d7820 256 .start = gic_spi(58),
6c01ba44
KM		 257 .flags = IORESOURCE_IRQ,
258 },
259};
260
261static struct platform_device cmt10_device = {
262 .name = "sh_cmt",
263 .id = 10,
264 .dev = {
265 .platform_data = &cmt10_platform_data,
266 },
267 .resource = cmt10_resources,
268 .num_resources = ARRAY_SIZE(cmt10_resources),
269};
270
e67d7afc
KM		 271/* TMU */
272static struct sh_timer_config tmu00_platform_data = {
273 .name = "TMU00",
274 .channel_offset = 0x4,
275 .timer_bit = 0,
276 .clockevent_rating = 200,
277};
278
279static struct resource tmu00_resources[] = {
280 [0] = {
281 .name = "TMU00",
282 .start = 0xfff80008,
283 .end = 0xfff80014 - 1,
284 .flags = IORESOURCE_MEM,
285 },
286 [1] = {
0b7d7820 287 .start = gic_spi(198),
e67d7afc
KM		 288 .flags = IORESOURCE_IRQ,
289 },
290};
291
292static struct platform_device tmu00_device = {
293 .name = "sh_tmu",
294 .id = 0,
295 .dev = {
296 .platform_data = &tmu00_platform_data,
297 },
298 .resource = tmu00_resources,
299 .num_resources = ARRAY_SIZE(tmu00_resources),
300};
301
302static struct sh_timer_config tmu01_platform_data = {
303 .name = "TMU01",
304 .channel_offset = 0x10,
305 .timer_bit = 1,
306 .clocksource_rating = 200,
307};
308
309static struct resource tmu01_resources[] = {
310 [0] = {
311 .name = "TMU01",
312 .start = 0xfff80014,
313 .end = 0xfff80020 - 1,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
0b7d7820 317 .start = gic_spi(199),
e67d7afc
KM		 318 .flags = IORESOURCE_IRQ,
319 },
320};
321
322static struct platform_device tmu01_device = {
323 .name = "sh_tmu",
324 .id = 1,
325 .dev = {
326 .platform_data = &tmu01_platform_data,
327 },
328 .resource = tmu01_resources,
329 .num_resources = ARRAY_SIZE(tmu01_resources),
330};
331
332static struct sh_timer_config tmu02_platform_data = {
333 .name = "TMU02",
334 .channel_offset = 0x1C,
335 .timer_bit = 2,
336 .clocksource_rating = 200,
337};
338
339static struct resource tmu02_resources[] = {
340 [0] = {
341 .name = "TMU02",
342 .start = 0xfff80020,
343 .end = 0xfff8002C - 1,
344 .flags = IORESOURCE_MEM,
345 },
346 [1] = {
0b7d7820 347 .start = gic_spi(200),
e67d7afc
KM		 348 .flags = IORESOURCE_IRQ,
349 },
350};
351
352static struct platform_device tmu02_device = {
353 .name = "sh_tmu",
354 .id = 2,
355 .dev = {
356 .platform_data = &tmu02_platform_data,
357 },
358 .resource = tmu02_resources,
359 .num_resources = ARRAY_SIZE(tmu02_resources),
360};
361
f671e022
HE		 362/* IPMMUI (an IPMMU module for ICB/LMB) */
363static struct resource ipmmu_resources[] = {
364 [0] = {
365 .name = "IPMMUI",
366 .start = 0xfe951000,
367 .end = 0xfe9510ff,
368 .flags = IORESOURCE_MEM,
369 },
370};
371
372static const char * const ipmmu_dev_names[] = {
373 "sh_mobile_lcdc_fb.0",
374 "sh_mobile_lcdc_fb.1",
375 "sh_mobile_ceu.0",
376};
377
378static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
379 .dev_names = ipmmu_dev_names,
380 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
381};
382
383static struct platform_device ipmmu_device = {
384 .name = "ipmmu",
385 .id = -1,
386 .dev = {
387 .platform_data = &ipmmu_platform_data,
388 },
389 .resource = ipmmu_resources,
390 .num_resources = ARRAY_SIZE(ipmmu_resources),
391};
392
744fdc8d 393static struct platform_device *r8a7740_devices_dt[] __initdata = {
6c01ba44
KM		 394 &scif0_device,
395 &scif1_device,
396 &scif2_device,
397 &scif3_device,
398 &scif4_device,
399 &scif5_device,
400 &scif6_device,
401 &scif7_device,
c9e06d8e 402 &scif8_device,
6c01ba44 403 &cmt10_device,
744fdc8d
BH		 404};
405
406static struct platform_device *r8a7740_early_devices[] __initdata = {
407 &irqpin0_device,
408 &irqpin1_device,
409 &irqpin2_device,
410 &irqpin3_device,
e67d7afc
KM		 411 &tmu00_device,
412 &tmu01_device,
413 &tmu02_device,
f671e022 414 &ipmmu_device,
6c01ba44
KM		 415};
416
643c3307 417/* DMA */
643c3307
KM		 418static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
419 {
cb76eb81
KM		 420 .slave_id = SHDMA_SLAVE_SDHI0_TX,
421 .addr = 0xe6850030,
422 .chcr = CHCR_TX(XMIT_SZ_16BIT),
423 .mid_rid = 0xc1,
424 }, {
425 .slave_id = SHDMA_SLAVE_SDHI0_RX,
426 .addr = 0xe6850030,
427 .chcr = CHCR_RX(XMIT_SZ_16BIT),
428 .mid_rid = 0xc2,
429 }, {
430 .slave_id = SHDMA_SLAVE_SDHI1_TX,
431 .addr = 0xe6860030,
432 .chcr = CHCR_TX(XMIT_SZ_16BIT),
433 .mid_rid = 0xc9,
434 }, {
435 .slave_id = SHDMA_SLAVE_SDHI1_RX,
436 .addr = 0xe6860030,
437 .chcr = CHCR_RX(XMIT_SZ_16BIT),
438 .mid_rid = 0xca,
439 }, {
440 .slave_id = SHDMA_SLAVE_SDHI2_TX,
441 .addr = 0xe6870030,
442 .chcr = CHCR_TX(XMIT_SZ_16BIT),
443 .mid_rid = 0xcd,
444 }, {
445 .slave_id = SHDMA_SLAVE_SDHI2_RX,
446 .addr = 0xe6870030,
447 .chcr = CHCR_RX(XMIT_SZ_16BIT),
448 .mid_rid = 0xce,
449 }, {
643c3307
KM		 450 .slave_id = SHDMA_SLAVE_FSIA_TX,
451 .addr = 0xfe1f0024,
452 .chcr = CHCR_TX(XMIT_SZ_32BIT),
453 .mid_rid = 0xb1,
454 }, {
455 .slave_id = SHDMA_SLAVE_FSIA_RX,
456 .addr = 0xfe1f0020,
457 .chcr = CHCR_RX(XMIT_SZ_32BIT),
458 .mid_rid = 0xb2,
459 }, {
460 .slave_id = SHDMA_SLAVE_FSIB_TX,
461 .addr = 0xfe1f0064,
462 .chcr = CHCR_TX(XMIT_SZ_32BIT),
463 .mid_rid = 0xb5,
9a145624
GL		 464 }, {
465 .slave_id = SHDMA_SLAVE_MMCIF_TX,
466 .addr = 0xe6bd0034,
467 .chcr = CHCR_TX(XMIT_SZ_32BIT),
468 .mid_rid = 0xd1,
469 }, {
470 .slave_id = SHDMA_SLAVE_MMCIF_RX,
471 .addr = 0xe6bd0034,
472 .chcr = CHCR_RX(XMIT_SZ_32BIT),
473 .mid_rid = 0xd2,
643c3307
KM		 474 },
475};
476
477#define DMA_CHANNEL(a, b, c) \
478{ \
479 .offset = a, \
480 .dmars = b, \
481 .dmars_bit = c, \
482 .chclr_offset = (0x220 - 0x20) + a \
483}
484
485static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
486 DMA_CHANNEL(0x00, 0, 0),
487 DMA_CHANNEL(0x10, 0, 8),
488 DMA_CHANNEL(0x20, 4, 0),
489 DMA_CHANNEL(0x30, 4, 8),
490 DMA_CHANNEL(0x50, 8, 0),
491 DMA_CHANNEL(0x60, 8, 8),
492};
493
643c3307
KM		 494static struct sh_dmae_pdata dma_platform_data = {
495 .slave = r8a7740_dmae_slaves,
496 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
497 .channel = r8a7740_dmae_channels,
498 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
d7de938f
KM		 499 .ts_low_shift = TS_LOW_SHIFT,
500 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
501 .ts_high_shift = TS_HI_SHIFT,
502 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
503 .ts_shift = dma_ts_shift,
504 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
643c3307
KM		 505 .dmaor_init = DMAOR_DME,
506 .chclr_present = 1,
507};
508
509/* Resource order important! */
510static struct resource r8a7740_dmae0_resources[] = {
511 {
512 /* Channel registers and DMAOR */
513 .start = 0xfe008020,
514 .end = 0xfe00828f,
515 .flags = IORESOURCE_MEM,
516 },
517 {
518 /* DMARSx */
519 .start = 0xfe009000,
520 .end = 0xfe00900b,
521 .flags = IORESOURCE_MEM,
522 },
523 {
524 .name = "error_irq",
0b7d7820
BH		 525 .start = gic_spi(34),
526 .end = gic_spi(34),
643c3307
KM		 527 .flags = IORESOURCE_IRQ,
528 },
529 {
530 /* IRQ for channels 0-5 */
0b7d7820
BH		 531 .start = gic_spi(28),
532 .end = gic_spi(33),
643c3307
KM		 533 .flags = IORESOURCE_IRQ,
534 },
535};
536
537/* Resource order important! */
538static struct resource r8a7740_dmae1_resources[] = {
539 {
540 /* Channel registers and DMAOR */
541 .start = 0xfe018020,
542 .end = 0xfe01828f,
543 .flags = IORESOURCE_MEM,
544 },
545 {
546 /* DMARSx */
547 .start = 0xfe019000,
548 .end = 0xfe01900b,
549 .flags = IORESOURCE_MEM,
550 },
551 {
552 .name = "error_irq",
0b7d7820
BH		 553 .start = gic_spi(41),
554 .end = gic_spi(41),
643c3307
KM		 555 .flags = IORESOURCE_IRQ,
556 },
557 {
558 /* IRQ for channels 0-5 */
0b7d7820
BH		 559 .start = gic_spi(35),
560 .end = gic_spi(40),
643c3307
KM		 561 .flags = IORESOURCE_IRQ,
562 },
563};
564
565/* Resource order important! */
566static struct resource r8a7740_dmae2_resources[] = {
567 {
568 /* Channel registers and DMAOR */
569 .start = 0xfe028020,
570 .end = 0xfe02828f,
571 .flags = IORESOURCE_MEM,
572 },
573 {
574 /* DMARSx */
575 .start = 0xfe029000,
576 .end = 0xfe02900b,
577 .flags = IORESOURCE_MEM,
578 },
579 {
580 .name = "error_irq",
0b7d7820
BH		 581 .start = gic_spi(48),
582 .end = gic_spi(48),
643c3307
KM		 583 .flags = IORESOURCE_IRQ,
584 },
585 {
586 /* IRQ for channels 0-5 */
0b7d7820
BH		 587 .start = gic_spi(42),
588 .end = gic_spi(47),
643c3307
KM		 589 .flags = IORESOURCE_IRQ,
590 },
591};
592
593static struct platform_device dma0_device = {
594 .name = "sh-dma-engine",
595 .id = 0,
596 .resource = r8a7740_dmae0_resources,
597 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
598 .dev = {
599 .platform_data = &dma_platform_data,
600 },
601};
602
603static struct platform_device dma1_device = {
604 .name = "sh-dma-engine",
605 .id = 1,
606 .resource = r8a7740_dmae1_resources,
607 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
608 .dev = {
609 .platform_data = &dma_platform_data,
610 },
611};
612
613static struct platform_device dma2_device = {
614 .name = "sh-dma-engine",
615 .id = 2,
616 .resource = r8a7740_dmae2_resources,
617 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
618 .dev = {
619 .platform_data = &dma_platform_data,
620 },
621};
622
dbf382e5 623/* USB-DMAC */
dbf382e5
KM		 624static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
625 {
626 .offset = 0,
627 }, {
628 .offset = 0x20,
629 },
630};
631
dbf382e5
KM		 632static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
633 {
634 .slave_id = SHDMA_SLAVE_USBHS_TX,
635 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
636 }, {
637 .slave_id = SHDMA_SLAVE_USBHS_RX,
638 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
639 },
640};
641
642static struct sh_dmae_pdata usb_dma_platform_data = {
643 .slave = r8a7740_usb_dma_slaves,
644 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
645 .channel = r8a7740_usb_dma_channels,
646 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
d7de938f
KM		 647 .ts_low_shift = USBTS_LOW_SHIFT,
648 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
649 .ts_high_shift = USBTS_HI_SHIFT,
650 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
dbf382e5
KM		 651 .ts_shift = dma_usbts_shift,
652 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
653 .dmaor_init = DMAOR_DME,
654 .chcr_offset = 0x14,
655 .chcr_ie_bit = 1 << 5,
656 .dmaor_is_32bit = 1,
657 .needs_tend_set = 1,
658 .no_dmars = 1,
659 .slave_only = 1,
660};
661
662static struct resource r8a7740_usb_dma_resources[] = {
663 {
664 /* Channel registers and DMAOR */
665 .start = 0xe68a0020,
666 .end = 0xe68a0064 - 1,
667 .flags = IORESOURCE_MEM,
668 },
669 {
670 /* VCR/SWR/DMICR */
671 .start = 0xe68a0000,
672 .end = 0xe68a0014 - 1,
673 .flags = IORESOURCE_MEM,
674 },
675 {
676 /* IRQ for channels */
0b7d7820
BH		 677 .start = gic_spi(49),
678 .end = gic_spi(49),
dbf382e5
KM		 679 .flags = IORESOURCE_IRQ,
680 },
681};
682
683static struct platform_device usb_dma_device = {
684 .name = "sh-dma-engine",
685 .id = 3,
686 .resource = r8a7740_usb_dma_resources,
687 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
688 .dev = {
689 .platform_data = &usb_dma_platform_data,
690 },
691};
692
6831f3a9
KM		 693/* I2C */
694static struct resource i2c0_resources[] = {
695 [0] = {
696 .name = "IIC0",
697 .start = 0xfff20000,
698 .end = 0xfff20425 - 1,
699 .flags = IORESOURCE_MEM,
700 },
701 [1] = {
0b7d7820
BH		 702 .start = gic_spi(201),
703 .end = gic_spi(204),
6831f3a9
KM		 704 .flags = IORESOURCE_IRQ,
705 },
706};
707
708static struct resource i2c1_resources[] = {
709 [0] = {
710 .name = "IIC1",
711 .start = 0xe6c20000,
712 .end = 0xe6c20425 - 1,
713 .flags = IORESOURCE_MEM,
714 },
715 [1] = {
0b7d7820
BH		 716 .start = gic_spi(70), /* IIC1_ALI1 */
717 .end = gic_spi(73), /* IIC1_DTEI1 */
6831f3a9
KM		 718 .flags = IORESOURCE_IRQ,
719 },
720};
721
722static struct platform_device i2c0_device = {
723 .name = "i2c-sh_mobile",
724 .id = 0,
725 .resource = i2c0_resources,
726 .num_resources = ARRAY_SIZE(i2c0_resources),
727};
728
729static struct platform_device i2c1_device = {
730 .name = "i2c-sh_mobile",
731 .id = 1,
732 .resource = i2c1_resources,
733 .num_resources = ARRAY_SIZE(i2c1_resources),
734};
735
86bc52ef
NI		 736static struct resource pmu_resources[] = {
737 [0] = {
0b7d7820
BH		 738 .start = gic_spi(83),
739 .end = gic_spi(83),
86bc52ef
NI		 740 .flags = IORESOURCE_IRQ,
741 },
742};
743
744static struct platform_device pmu_device = {
745 .name = "arm-pmu",
746 .id = -1,
747 .num_resources = ARRAY_SIZE(pmu_resources),
748 .resource = pmu_resources,
749};
750
6831f3a9
KM		 751static struct platform_device *r8a7740_late_devices[] __initdata = {
752 &i2c0_device,
753 &i2c1_device,
643c3307
KM		 754 &dma0_device,
755 &dma1_device,
756 &dma2_device,
dbf382e5 757 &usb_dma_device,
86bc52ef 758 &pmu_device,
6831f3a9
KM		 759};
760
d49679e5
KM		 761/*
762 * r8a7740 chip has lasting errata on MERAM buffer.
763 * this is work-around for it.
764 * see
765 * "Media RAM (MERAM)" on r8a7740 documentation
766 */
767#define MEBUFCNTR 0xFE950098
768void r8a7740_meram_workaround(void)
769{
770 void __iomem *reg;
771
772 reg = ioremap_nocache(MEBUFCNTR, 4);
773 if (reg) {
774 iowrite32(0x01600164, reg);
775 iounmap(reg);
776 }
777}
778
6831f3a9
KM		 779#define ICCR 0x0004
780#define ICSTART 0x0070
781
782#define i2c_read(reg, offset) ioread8(reg + offset)
783#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
784
785/*
786 * r8a7740 chip has lasting errata on I2C I/O pad reset.
787 * this is work-around for it.
788 */
789static void r8a7740_i2c_workaround(struct platform_device *pdev)
790{
791 struct resource *res;
792 void __iomem *reg;
793
794 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
795 if (unlikely(!res)) {
796 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
797 return;
798 }
799
800 reg = ioremap(res->start, resource_size(res));
801 if (unlikely(!reg)) {
802 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
803 return;
804 }
805
806 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
807 i2c_read(reg, ICCR); /* dummy read */
808
809 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
810 i2c_read(reg, ICSTART); /* dummy read */
811
4228716c 812 udelay(10);
6831f3a9
KM		 813
814 i2c_write(reg, ICCR, 0x01);
6831f3a9 815 i2c_write(reg, ICSTART, 0x00);
4228716c
KM		 816
817 udelay(10);
6831f3a9
KM		 818
819 i2c_write(reg, ICCR, 0x10);
4228716c 820 udelay(10);
6831f3a9 821 i2c_write(reg, ICCR, 0x00);
4228716c 822 udelay(10);
6831f3a9 823 i2c_write(reg, ICCR, 0x10);
4228716c 824 udelay(10);
6831f3a9
KM		 825
826 iounmap(reg);
827}
828
6c01ba44
KM		 829void __init r8a7740_add_standard_devices(void)
830{
6831f3a9
KM		 831 /* I2C work-around */
832 r8a7740_i2c_workaround(&i2c0_device);
833 r8a7740_i2c_workaround(&i2c1_device);
834
7b567407 835 r8a7740_init_pm_domains();
8459293c
KM		 836
837 /* add devices */
6c01ba44
KM		 838 platform_add_devices(r8a7740_early_devices,
839 ARRAY_SIZE(r8a7740_early_devices));
744fdc8d
BH		 840 platform_add_devices(r8a7740_devices_dt,
841 ARRAY_SIZE(r8a7740_devices_dt));
6831f3a9
KM		 842 platform_add_devices(r8a7740_late_devices,
843 ARRAY_SIZE(r8a7740_late_devices));
802a5639
KM		 844
845 /* add devices to PM domain */
846
8bdd9468
RW		 847 rmobile_add_device_to_domain("A3SP", &scif0_device);
848 rmobile_add_device_to_domain("A3SP", &scif1_device);
849 rmobile_add_device_to_domain("A3SP", &scif2_device);
850 rmobile_add_device_to_domain("A3SP", &scif3_device);
851 rmobile_add_device_to_domain("A3SP", &scif4_device);
852 rmobile_add_device_to_domain("A3SP", &scif5_device);
853 rmobile_add_device_to_domain("A3SP", &scif6_device);
854 rmobile_add_device_to_domain("A3SP", &scif7_device);
c9e06d8e 855 rmobile_add_device_to_domain("A3SP", &scif8_device);
8bdd9468 856 rmobile_add_device_to_domain("A3SP", &i2c1_device);
6c01ba44
KM		 857}
858
859void __init r8a7740_add_early_devices(void)
860{
861 early_platform_add_devices(r8a7740_early_devices,
862 ARRAY_SIZE(r8a7740_early_devices));
744fdc8d
BH		 863 early_platform_add_devices(r8a7740_devices_dt,
864 ARRAY_SIZE(r8a7740_devices_dt));
d3ab7221
MD		 865
866 /* setup early console here as well */
867 shmobile_setup_console();
6c01ba44 868}
755d57b2
MD		 869
870#ifdef CONFIG_USE_OF
871
88378837
MD		 872void __init r8a7740_add_early_devices_dt(void)
873{
874 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
875
876 early_platform_add_devices(r8a7740_early_devices,
877 ARRAY_SIZE(r8a7740_early_devices));
878
879 /* setup early console here as well */
880 shmobile_setup_console();
881}
755d57b2
MD		 882
883void __init r8a7740_add_standard_devices_dt(void)
884{
744fdc8d
BH		 885 platform_add_devices(r8a7740_devices_dt,
886 ARRAY_SIZE(r8a7740_devices_dt));
88378837 887 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
755d57b2
MD		 888}
889
744fdc8d
BH		 890void __init r8a7740_init_delay(void)
891{
892 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
893};
894
70e3f3d4
KM		 895void __init r8a7740_init_irq_of(void)
896{
897 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
898 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
899 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
900
901 irqchip_init();
902
903 /* route signals to GIC */
904 iowrite32(0x0, pfc_inta_ctrl);
905
906 /*
907 * To mask the shared interrupt to SPI 149 we must ensure to set
908 * PRIO *and* MASK. Else we run into IRQ floods when registering
909 * the intc_irqpin devices
910 */
911 iowrite32(0x0, intc_prio_base + 0x0);
912 iowrite32(0x0, intc_prio_base + 0x4);
913 iowrite32(0x0, intc_prio_base + 0x8);
914 iowrite32(0x0, intc_prio_base + 0xc);
915 iowrite8(0xff, intc_msk_base + 0x0);
916 iowrite8(0xff, intc_msk_base + 0x4);
917 iowrite8(0xff, intc_msk_base + 0x8);
918 iowrite8(0xff, intc_msk_base + 0xc);
919
920 iounmap(intc_prio_base);
921 iounmap(intc_msk_base);
922 iounmap(pfc_inta_ctrl);
923}
924
744fdc8d
BH		 925static void __init r8a7740_generic_init(void)
926{
927 r8a7740_clock_init(0);
928 r8a7740_add_standard_devices_dt();
929}
930
755d57b2
MD		 931static const char *r8a7740_boards_compat_dt[] __initdata = {
932 "renesas,r8a7740",
933 NULL,
934};
935
a41acc4a 936DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
755d57b2 937 .map_io = r8a7740_map_io,
744fdc8d
BH		 938 .init_early = r8a7740_init_delay,
939 .init_irq = r8a7740_init_irq_of,
940 .init_machine = r8a7740_generic_init,
755d57b2
MD		 941 .dt_compat = r8a7740_boards_compat_dt,
942MACHINE_END
943
944#endif /* CONFIG_USE_OF */
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