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ARM: shmobile: Move most of irqs.h, keep some for pinctl
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-shmobile / setup-r8a7740.c
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6c01ba44
KM		 1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
6831f3a9 20#include <linux/delay.h>
3841e6f5 21#include <linux/dma-mapping.h>
6c01ba44
KM		 22#include <linux/kernel.h>
23#include <linux/init.h>
6831f3a9 24#include <linux/io.h>
70e3f3d4
KM		 25#include <linux/irqchip.h>
26#include <linux/irqchip/arm-gic.h>
0b7d7820 27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
6c01ba44 28#include <linux/platform_device.h>
755d57b2 29#include <linux/of_platform.h>
6c01ba44 30#include <linux/serial_sci.h>
643c3307 31#include <linux/sh_dma.h>
6c01ba44 32#include <linux/sh_timer.h>
f671e022 33#include <linux/platform_data/sh_ipmmu.h>
6c01ba44 34#include <mach/r8a7740.h>
8459293c 35#include <mach/pm-rmobile.h>
d3ab7221 36#include <mach/common.h>
6c01ba44 37#include <asm/mach-types.h>
d3ab7221 38#include <asm/mach/map.h>
6c01ba44 39#include <asm/mach/arch.h>
23e5bc03 40#include <asm/mach/time.h>
74ac0de8 41#include "dma-register.h"
b6bab126 42#include "irqs.h"
6c01ba44 43
d3ab7221
MD		 44static struct map_desc r8a7740_io_desc[] __initdata = {
45 /*
46 * for CPGA/INTC/PFC
47 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
48 */
49 {
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
52 .length = 160 << 20,
53 .type = MT_DEVICE_NONSHARED
54 },
55#ifdef CONFIG_CACHE_L2X0
56 /*
57 * for l2x0_init()
58 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
59 */
60 {
61 .virtual = 0xf0002000,
62 .pfn = __phys_to_pfn(0xf0100000),
63 .length = PAGE_SIZE,
64 .type = MT_DEVICE_NONSHARED
65 },
66#endif
67};
68
69void __init r8a7740_map_io(void)
70{
71 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
72}
73
02b01adb 74/* PFC */
3404622a
MD		 75static const struct resource pfc_resources[] = {
76 DEFINE_RES_MEM(0xe6050000, 0x8000),
77 DEFINE_RES_MEM(0xe605800c, 0x0020),
02b01adb
LP		 78};
79
80void __init r8a7740_pinmux_init(void)
81{
3404622a
MD		 82 platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
83 ARRAY_SIZE(pfc_resources));
02b01adb
LP		 84}
85
0b7d7820
BH		 86static struct renesas_intc_irqpin_config irqpin0_platform_data = {
87 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
88};
89
90static struct resource irqpin0_resources[] = {
91 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
92 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
93 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
94 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
95 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
96 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
97 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
98 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
99 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
100 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
101 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
102 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
103 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
104};
105
106static struct platform_device irqpin0_device = {
107 .name = "renesas_intc_irqpin",
108 .id = 0,
109 .resource = irqpin0_resources,
110 .num_resources = ARRAY_SIZE(irqpin0_resources),
111 .dev = {
112 .platform_data = &irqpin0_platform_data,
113 },
114};
115
116static struct renesas_intc_irqpin_config irqpin1_platform_data = {
117 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
118};
119
120static struct resource irqpin1_resources[] = {
121 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
122 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
123 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
124 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
125 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
126 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
127 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
128 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
129 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
130 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
131 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
132 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
133 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
134};
135
136static struct platform_device irqpin1_device = {
137 .name = "renesas_intc_irqpin",
138 .id = 1,
139 .resource = irqpin1_resources,
140 .num_resources = ARRAY_SIZE(irqpin1_resources),
141 .dev = {
142 .platform_data = &irqpin1_platform_data,
143 },
144};
145
146static struct renesas_intc_irqpin_config irqpin2_platform_data = {
147 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
148};
149
150static struct resource irqpin2_resources[] = {
151 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
152 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
153 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
154 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
155 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
156 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
157 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
158 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
159 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
160 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
161 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
162 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
163 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
164};
165
166static struct platform_device irqpin2_device = {
167 .name = "renesas_intc_irqpin",
168 .id = 2,
169 .resource = irqpin2_resources,
170 .num_resources = ARRAY_SIZE(irqpin2_resources),
171 .dev = {
172 .platform_data = &irqpin2_platform_data,
173 },
174};
175
176static struct renesas_intc_irqpin_config irqpin3_platform_data = {
177 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
178};
179
180static struct resource irqpin3_resources[] = {
181 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
182 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
183 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
184 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
185 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
186 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
187 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
188 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
189 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
190 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
191 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
192 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
193 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
194};
195
196static struct platform_device irqpin3_device = {
197 .name = "renesas_intc_irqpin",
198 .id = 3,
199 .resource = irqpin3_resources,
200 .num_resources = ARRAY_SIZE(irqpin3_resources),
201 .dev = {
202 .platform_data = &irqpin3_platform_data,
203 },
204};
205
c9e06d8e
LP		 206/* SCIF */
207#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
208static struct plat_sci_port scif##index##_platform_data = { \
209 .type = scif_type, \
c9e06d8e 210 .flags = UPF_BOOT_AUTOCONF, \
c9e06d8e
LP		 211 .scscr = SCSCR_RE | SCSCR_TE, \
212}; \
213 \
8bf2f8c5
LP		 214static struct resource scif##index##_resources[] = { \
215 DEFINE_RES_MEM(baseaddr, 0x100), \
216 DEFINE_RES_IRQ(irq), \
217}; \
218 \
c9e06d8e
LP		 219static struct platform_device scif##index##_device = { \
220 .name = "sh-sci", \
221 .id = index, \
8bf2f8c5
LP		 222 .resource = scif##index##_resources, \
223 .num_resources = ARRAY_SIZE(scif##index##_resources), \
c9e06d8e
LP		 224 .dev = { \
225 .platform_data = &scif##index##_platform_data, \
226 }, \
227}
6c01ba44 228
c9e06d8e
LP		 229R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
230R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
231R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
232R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
233R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
234R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
235R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
236R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
237R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
6c01ba44
KM		 238
239/* CMT */
e0ad56a3
LP		 240static struct sh_timer_config cmt1_platform_data = {
241 .channels_mask = 0x3f,
6c01ba44
KM		 242};
243
e0ad56a3
LP		 244static struct resource cmt1_resources[] = {
245 DEFINE_RES_MEM(0xe6138000, 0x170),
246 DEFINE_RES_IRQ(gic_spi(58)),
6c01ba44
KM		 247};
248
e0ad56a3
LP		 249static struct platform_device cmt1_device = {
250 .name = "sh-cmt-48",
251 .id = 1,
6c01ba44 252 .dev = {
e0ad56a3 253 .platform_data = &cmt1_platform_data,
6c01ba44 254 },
e0ad56a3
LP		 255 .resource = cmt1_resources,
256 .num_resources = ARRAY_SIZE(cmt1_resources),
6c01ba44
KM		 257};
258
e67d7afc 259/* TMU */
8ec72e46
LP		 260static struct sh_timer_config tmu0_platform_data = {
261 .channels_mask = 7,
e67d7afc
KM		 262};
263
8ec72e46
LP		 264static struct resource tmu0_resources[] = {
265 DEFINE_RES_MEM(0xfff80000, 0x2c),
266 DEFINE_RES_IRQ(gic_spi(198)),
267 DEFINE_RES_IRQ(gic_spi(199)),
268 DEFINE_RES_IRQ(gic_spi(200)),
e67d7afc
KM		 269};
270
8ec72e46
LP		 271static struct platform_device tmu0_device = {
272 .name = "sh-tmu",
e67d7afc
KM		 273 .id = 0,
274 .dev = {
8ec72e46 275 .platform_data = &tmu0_platform_data,
e67d7afc 276 },
8ec72e46
LP		 277 .resource = tmu0_resources,
278 .num_resources = ARRAY_SIZE(tmu0_resources),
e67d7afc
KM		 279};
280
f671e022
HE		 281/* IPMMUI (an IPMMU module for ICB/LMB) */
282static struct resource ipmmu_resources[] = {
283 [0] = {
284 .name = "IPMMUI",
285 .start = 0xfe951000,
286 .end = 0xfe9510ff,
287 .flags = IORESOURCE_MEM,
288 },
289};
290
291static const char * const ipmmu_dev_names[] = {
292 "sh_mobile_lcdc_fb.0",
293 "sh_mobile_lcdc_fb.1",
294 "sh_mobile_ceu.0",
295};
296
297static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
298 .dev_names = ipmmu_dev_names,
299 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
300};
301
302static struct platform_device ipmmu_device = {
303 .name = "ipmmu",
304 .id = -1,
305 .dev = {
306 .platform_data = &ipmmu_platform_data,
307 },
308 .resource = ipmmu_resources,
309 .num_resources = ARRAY_SIZE(ipmmu_resources),
310};
311
744fdc8d 312static struct platform_device *r8a7740_devices_dt[] __initdata = {
6c01ba44
KM		 313 &scif0_device,
314 &scif1_device,
315 &scif2_device,
316 &scif3_device,
317 &scif4_device,
318 &scif5_device,
319 &scif6_device,
320 &scif7_device,
c9e06d8e 321 &scif8_device,
e0ad56a3 322 &cmt1_device,
744fdc8d
BH		 323};
324
325static struct platform_device *r8a7740_early_devices[] __initdata = {
326 &irqpin0_device,
327 &irqpin1_device,
328 &irqpin2_device,
329 &irqpin3_device,
8ec72e46 330 &tmu0_device,
f671e022 331 &ipmmu_device,
6c01ba44
KM		 332};
333
643c3307 334/* DMA */
643c3307
KM		 335static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
336 {
cb76eb81
KM		 337 .slave_id = SHDMA_SLAVE_SDHI0_TX,
338 .addr = 0xe6850030,
339 .chcr = CHCR_TX(XMIT_SZ_16BIT),
340 .mid_rid = 0xc1,
341 }, {
342 .slave_id = SHDMA_SLAVE_SDHI0_RX,
343 .addr = 0xe6850030,
344 .chcr = CHCR_RX(XMIT_SZ_16BIT),
345 .mid_rid = 0xc2,
346 }, {
347 .slave_id = SHDMA_SLAVE_SDHI1_TX,
348 .addr = 0xe6860030,
349 .chcr = CHCR_TX(XMIT_SZ_16BIT),
350 .mid_rid = 0xc9,
351 }, {
352 .slave_id = SHDMA_SLAVE_SDHI1_RX,
353 .addr = 0xe6860030,
354 .chcr = CHCR_RX(XMIT_SZ_16BIT),
355 .mid_rid = 0xca,
356 }, {
357 .slave_id = SHDMA_SLAVE_SDHI2_TX,
358 .addr = 0xe6870030,
359 .chcr = CHCR_TX(XMIT_SZ_16BIT),
360 .mid_rid = 0xcd,
361 }, {
362 .slave_id = SHDMA_SLAVE_SDHI2_RX,
363 .addr = 0xe6870030,
364 .chcr = CHCR_RX(XMIT_SZ_16BIT),
365 .mid_rid = 0xce,
366 }, {
643c3307
KM		 367 .slave_id = SHDMA_SLAVE_FSIA_TX,
368 .addr = 0xfe1f0024,
369 .chcr = CHCR_TX(XMIT_SZ_32BIT),
370 .mid_rid = 0xb1,
371 }, {
372 .slave_id = SHDMA_SLAVE_FSIA_RX,
373 .addr = 0xfe1f0020,
374 .chcr = CHCR_RX(XMIT_SZ_32BIT),
375 .mid_rid = 0xb2,
376 }, {
377 .slave_id = SHDMA_SLAVE_FSIB_TX,
378 .addr = 0xfe1f0064,
379 .chcr = CHCR_TX(XMIT_SZ_32BIT),
380 .mid_rid = 0xb5,
9a145624
GL		 381 }, {
382 .slave_id = SHDMA_SLAVE_MMCIF_TX,
383 .addr = 0xe6bd0034,
384 .chcr = CHCR_TX(XMIT_SZ_32BIT),
385 .mid_rid = 0xd1,
386 }, {
387 .slave_id = SHDMA_SLAVE_MMCIF_RX,
388 .addr = 0xe6bd0034,
389 .chcr = CHCR_RX(XMIT_SZ_32BIT),
390 .mid_rid = 0xd2,
643c3307
KM		 391 },
392};
393
394#define DMA_CHANNEL(a, b, c) \
395{ \
396 .offset = a, \
397 .dmars = b, \
398 .dmars_bit = c, \
399 .chclr_offset = (0x220 - 0x20) + a \
400}
401
402static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
403 DMA_CHANNEL(0x00, 0, 0),
404 DMA_CHANNEL(0x10, 0, 8),
405 DMA_CHANNEL(0x20, 4, 0),
406 DMA_CHANNEL(0x30, 4, 8),
407 DMA_CHANNEL(0x50, 8, 0),
408 DMA_CHANNEL(0x60, 8, 8),
409};
410
643c3307
KM		 411static struct sh_dmae_pdata dma_platform_data = {
412 .slave = r8a7740_dmae_slaves,
413 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
414 .channel = r8a7740_dmae_channels,
415 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
d7de938f
KM		 416 .ts_low_shift = TS_LOW_SHIFT,
417 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
418 .ts_high_shift = TS_HI_SHIFT,
419 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
420 .ts_shift = dma_ts_shift,
421 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
643c3307
KM		 422 .dmaor_init = DMAOR_DME,
423 .chclr_present = 1,
424};
425
426/* Resource order important! */
427static struct resource r8a7740_dmae0_resources[] = {
428 {
429 /* Channel registers and DMAOR */
430 .start = 0xfe008020,
431 .end = 0xfe00828f,
432 .flags = IORESOURCE_MEM,
433 },
434 {
435 /* DMARSx */
436 .start = 0xfe009000,
437 .end = 0xfe00900b,
438 .flags = IORESOURCE_MEM,
439 },
440 {
441 .name = "error_irq",
0b7d7820
BH		 442 .start = gic_spi(34),
443 .end = gic_spi(34),
643c3307
KM		 444 .flags = IORESOURCE_IRQ,
445 },
446 {
447 /* IRQ for channels 0-5 */
0b7d7820
BH		 448 .start = gic_spi(28),
449 .end = gic_spi(33),
643c3307
KM		 450 .flags = IORESOURCE_IRQ,
451 },
452};
453
454/* Resource order important! */
455static struct resource r8a7740_dmae1_resources[] = {
456 {
457 /* Channel registers and DMAOR */
458 .start = 0xfe018020,
459 .end = 0xfe01828f,
460 .flags = IORESOURCE_MEM,
461 },
462 {
463 /* DMARSx */
464 .start = 0xfe019000,
465 .end = 0xfe01900b,
466 .flags = IORESOURCE_MEM,
467 },
468 {
469 .name = "error_irq",
0b7d7820
BH		 470 .start = gic_spi(41),
471 .end = gic_spi(41),
643c3307
KM		 472 .flags = IORESOURCE_IRQ,
473 },
474 {
475 /* IRQ for channels 0-5 */
0b7d7820
BH		 476 .start = gic_spi(35),
477 .end = gic_spi(40),
643c3307
KM		 478 .flags = IORESOURCE_IRQ,
479 },
480};
481
482/* Resource order important! */
483static struct resource r8a7740_dmae2_resources[] = {
484 {
485 /* Channel registers and DMAOR */
486 .start = 0xfe028020,
487 .end = 0xfe02828f,
488 .flags = IORESOURCE_MEM,
489 },
490 {
491 /* DMARSx */
492 .start = 0xfe029000,
493 .end = 0xfe02900b,
494 .flags = IORESOURCE_MEM,
495 },
496 {
497 .name = "error_irq",
0b7d7820
BH		 498 .start = gic_spi(48),
499 .end = gic_spi(48),
643c3307
KM		 500 .flags = IORESOURCE_IRQ,
501 },
502 {
503 /* IRQ for channels 0-5 */
0b7d7820
BH		 504 .start = gic_spi(42),
505 .end = gic_spi(47),
643c3307
KM		 506 .flags = IORESOURCE_IRQ,
507 },
508};
509
510static struct platform_device dma0_device = {
511 .name = "sh-dma-engine",
512 .id = 0,
513 .resource = r8a7740_dmae0_resources,
514 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
515 .dev = {
516 .platform_data = &dma_platform_data,
517 },
518};
519
520static struct platform_device dma1_device = {
521 .name = "sh-dma-engine",
522 .id = 1,
523 .resource = r8a7740_dmae1_resources,
524 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
525 .dev = {
526 .platform_data = &dma_platform_data,
527 },
528};
529
530static struct platform_device dma2_device = {
531 .name = "sh-dma-engine",
532 .id = 2,
533 .resource = r8a7740_dmae2_resources,
534 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
535 .dev = {
536 .platform_data = &dma_platform_data,
537 },
538};
539
dbf382e5 540/* USB-DMAC */
dbf382e5
KM		 541static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
542 {
543 .offset = 0,
544 }, {
545 .offset = 0x20,
546 },
547};
548
dbf382e5
KM		 549static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
550 {
551 .slave_id = SHDMA_SLAVE_USBHS_TX,
552 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
553 }, {
554 .slave_id = SHDMA_SLAVE_USBHS_RX,
555 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
556 },
557};
558
559static struct sh_dmae_pdata usb_dma_platform_data = {
560 .slave = r8a7740_usb_dma_slaves,
561 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
562 .channel = r8a7740_usb_dma_channels,
563 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
d7de938f
KM		 564 .ts_low_shift = USBTS_LOW_SHIFT,
565 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
566 .ts_high_shift = USBTS_HI_SHIFT,
567 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
dbf382e5
KM		 568 .ts_shift = dma_usbts_shift,
569 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
570 .dmaor_init = DMAOR_DME,
571 .chcr_offset = 0x14,
572 .chcr_ie_bit = 1 << 5,
573 .dmaor_is_32bit = 1,
574 .needs_tend_set = 1,
575 .no_dmars = 1,
576 .slave_only = 1,
577};
578
579static struct resource r8a7740_usb_dma_resources[] = {
580 {
581 /* Channel registers and DMAOR */
582 .start = 0xe68a0020,
583 .end = 0xe68a0064 - 1,
584 .flags = IORESOURCE_MEM,
585 },
586 {
587 /* VCR/SWR/DMICR */
588 .start = 0xe68a0000,
589 .end = 0xe68a0014 - 1,
590 .flags = IORESOURCE_MEM,
591 },
592 {
593 /* IRQ for channels */
0b7d7820
BH		 594 .start = gic_spi(49),
595 .end = gic_spi(49),
dbf382e5
KM		 596 .flags = IORESOURCE_IRQ,
597 },
598};
599
600static struct platform_device usb_dma_device = {
601 .name = "sh-dma-engine",
602 .id = 3,
603 .resource = r8a7740_usb_dma_resources,
604 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
605 .dev = {
606 .platform_data = &usb_dma_platform_data,
607 },
608};
609
6831f3a9
KM		 610/* I2C */
611static struct resource i2c0_resources[] = {
612 [0] = {
613 .name = "IIC0",
614 .start = 0xfff20000,
615 .end = 0xfff20425 - 1,
616 .flags = IORESOURCE_MEM,
617 },
618 [1] = {
0b7d7820
BH		 619 .start = gic_spi(201),
620 .end = gic_spi(204),
6831f3a9
KM		 621 .flags = IORESOURCE_IRQ,
622 },
623};
624
625static struct resource i2c1_resources[] = {
626 [0] = {
627 .name = "IIC1",
628 .start = 0xe6c20000,
629 .end = 0xe6c20425 - 1,
630 .flags = IORESOURCE_MEM,
631 },
632 [1] = {
0b7d7820
BH		 633 .start = gic_spi(70), /* IIC1_ALI1 */
634 .end = gic_spi(73), /* IIC1_DTEI1 */
6831f3a9
KM		 635 .flags = IORESOURCE_IRQ,
636 },
637};
638
639static struct platform_device i2c0_device = {
640 .name = "i2c-sh_mobile",
641 .id = 0,
642 .resource = i2c0_resources,
643 .num_resources = ARRAY_SIZE(i2c0_resources),
644};
645
646static struct platform_device i2c1_device = {
647 .name = "i2c-sh_mobile",
648 .id = 1,
649 .resource = i2c1_resources,
650 .num_resources = ARRAY_SIZE(i2c1_resources),
651};
652
86bc52ef
NI		 653static struct resource pmu_resources[] = {
654 [0] = {
0b7d7820
BH		 655 .start = gic_spi(83),
656 .end = gic_spi(83),
86bc52ef
NI		 657 .flags = IORESOURCE_IRQ,
658 },
659};
660
661static struct platform_device pmu_device = {
662 .name = "arm-pmu",
663 .id = -1,
664 .num_resources = ARRAY_SIZE(pmu_resources),
665 .resource = pmu_resources,
666};
667
6831f3a9
KM		 668static struct platform_device *r8a7740_late_devices[] __initdata = {
669 &i2c0_device,
670 &i2c1_device,
643c3307
KM		 671 &dma0_device,
672 &dma1_device,
673 &dma2_device,
dbf382e5 674 &usb_dma_device,
86bc52ef 675 &pmu_device,
6831f3a9
KM		 676};
677
d49679e5
KM		 678/*
679 * r8a7740 chip has lasting errata on MERAM buffer.
680 * this is work-around for it.
681 * see
682 * "Media RAM (MERAM)" on r8a7740 documentation
683 */
684#define MEBUFCNTR 0xFE950098
bb6c3d58 685void __init r8a7740_meram_workaround(void)
d49679e5
KM		 686{
687 void __iomem *reg;
688
689 reg = ioremap_nocache(MEBUFCNTR, 4);
690 if (reg) {
691 iowrite32(0x01600164, reg);
692 iounmap(reg);
693 }
694}
695
6831f3a9
KM		 696#define ICCR 0x0004
697#define ICSTART 0x0070
698
699#define i2c_read(reg, offset) ioread8(reg + offset)
700#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
701
702/*
703 * r8a7740 chip has lasting errata on I2C I/O pad reset.
704 * this is work-around for it.
705 */
706static void r8a7740_i2c_workaround(struct platform_device *pdev)
707{
708 struct resource *res;
709 void __iomem *reg;
710
711 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
712 if (unlikely(!res)) {
713 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
714 return;
715 }
716
717 reg = ioremap(res->start, resource_size(res));
718 if (unlikely(!reg)) {
719 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
720 return;
721 }
722
723 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
724 i2c_read(reg, ICCR); /* dummy read */
725
726 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
727 i2c_read(reg, ICSTART); /* dummy read */
728
4228716c 729 udelay(10);
6831f3a9
KM		 730
731 i2c_write(reg, ICCR, 0x01);
6831f3a9 732 i2c_write(reg, ICSTART, 0x00);
4228716c
KM		 733
734 udelay(10);
6831f3a9
KM		 735
736 i2c_write(reg, ICCR, 0x10);
4228716c 737 udelay(10);
6831f3a9 738 i2c_write(reg, ICCR, 0x00);
4228716c 739 udelay(10);
6831f3a9 740 i2c_write(reg, ICCR, 0x10);
4228716c 741 udelay(10);
6831f3a9
KM		 742
743 iounmap(reg);
744}
745
6c01ba44
KM		 746void __init r8a7740_add_standard_devices(void)
747{
6831f3a9
KM		 748 /* I2C work-around */
749 r8a7740_i2c_workaround(&i2c0_device);
750 r8a7740_i2c_workaround(&i2c1_device);
751
7b567407 752 r8a7740_init_pm_domains();
8459293c
KM		 753
754 /* add devices */
6c01ba44
KM		 755 platform_add_devices(r8a7740_early_devices,
756 ARRAY_SIZE(r8a7740_early_devices));
744fdc8d
BH		 757 platform_add_devices(r8a7740_devices_dt,
758 ARRAY_SIZE(r8a7740_devices_dt));
6831f3a9
KM		 759 platform_add_devices(r8a7740_late_devices,
760 ARRAY_SIZE(r8a7740_late_devices));
802a5639
KM		 761
762 /* add devices to PM domain */
763
8bdd9468
RW		 764 rmobile_add_device_to_domain("A3SP", &scif0_device);
765 rmobile_add_device_to_domain("A3SP", &scif1_device);
766 rmobile_add_device_to_domain("A3SP", &scif2_device);
767 rmobile_add_device_to_domain("A3SP", &scif3_device);
768 rmobile_add_device_to_domain("A3SP", &scif4_device);
769 rmobile_add_device_to_domain("A3SP", &scif5_device);
770 rmobile_add_device_to_domain("A3SP", &scif6_device);
771 rmobile_add_device_to_domain("A3SP", &scif7_device);
c9e06d8e 772 rmobile_add_device_to_domain("A3SP", &scif8_device);
8bdd9468 773 rmobile_add_device_to_domain("A3SP", &i2c1_device);
6c01ba44
KM		 774}
775
776void __init r8a7740_add_early_devices(void)
777{
778 early_platform_add_devices(r8a7740_early_devices,
779 ARRAY_SIZE(r8a7740_early_devices));
744fdc8d
BH		 780 early_platform_add_devices(r8a7740_devices_dt,
781 ARRAY_SIZE(r8a7740_devices_dt));
d3ab7221
MD		 782
783 /* setup early console here as well */
784 shmobile_setup_console();
6c01ba44 785}
755d57b2
MD		 786
787#ifdef CONFIG_USE_OF
788
755d57b2
MD		 789void __init r8a7740_add_standard_devices_dt(void)
790{
744fdc8d
BH		 791 platform_add_devices(r8a7740_devices_dt,
792 ARRAY_SIZE(r8a7740_devices_dt));
88378837 793 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
755d57b2
MD		 794}
795
70e3f3d4
KM		 796void __init r8a7740_init_irq_of(void)
797{
798 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
799 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
800 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
801
802 irqchip_init();
803
804 /* route signals to GIC */
805 iowrite32(0x0, pfc_inta_ctrl);
806
807 /*
808 * To mask the shared interrupt to SPI 149 we must ensure to set
809 * PRIO *and* MASK. Else we run into IRQ floods when registering
810 * the intc_irqpin devices
811 */
812 iowrite32(0x0, intc_prio_base + 0x0);
813 iowrite32(0x0, intc_prio_base + 0x4);
814 iowrite32(0x0, intc_prio_base + 0x8);
815 iowrite32(0x0, intc_prio_base + 0xc);
816 iowrite8(0xff, intc_msk_base + 0x0);
817 iowrite8(0xff, intc_msk_base + 0x4);
818 iowrite8(0xff, intc_msk_base + 0x8);
819 iowrite8(0xff, intc_msk_base + 0xc);
820
821 iounmap(intc_prio_base);
822 iounmap(intc_msk_base);
823 iounmap(pfc_inta_ctrl);
824}
825
744fdc8d
BH		 826static void __init r8a7740_generic_init(void)
827{
828 r8a7740_clock_init(0);
829 r8a7740_add_standard_devices_dt();
830}
831
755d57b2
MD		 832static const char *r8a7740_boards_compat_dt[] __initdata = {
833 "renesas,r8a7740",
834 NULL,
835};
836
a41acc4a 837DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
755d57b2 838 .map_io = r8a7740_map_io,
a0c1fb0c 839 .init_early = shmobile_init_delay,
744fdc8d
BH		 840 .init_irq = r8a7740_init_irq_of,
841 .init_machine = r8a7740_generic_init,
34b9fa40 842 .init_late = shmobile_init_late,
755d57b2
MD		 843 .dt_compat = r8a7740_boards_compat_dt,
844MACHINE_END
845
846#endif /* CONFIG_USE_OF */
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