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0468b2d6 MD |
1 | /* |
2 | * r8a7790 processor support | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2013 Magnus Damm | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | */ | |
20 | ||
21 | #include <linux/irq.h> | |
22 | #include <linux/irqchip.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/of_platform.h> | |
55d9fab2 | 25 | #include <linux/serial_sci.h> |
8f5ec0a5 | 26 | #include <linux/platform_data/irq-renesas-irqc.h> |
0468b2d6 MD |
27 | #include <mach/common.h> |
28 | #include <mach/irqs.h> | |
29 | #include <mach/r8a7790.h> | |
30 | #include <asm/mach/arch.h> | |
31 | ||
69e351d0 MD |
32 | static const struct resource pfc_resources[] = { |
33 | DEFINE_RES_MEM(0xe6060000, 0x250), | |
c9dff050 | 34 | DEFINE_RES_MEM(0xe6050000, 0x5050), |
69e351d0 MD |
35 | }; |
36 | ||
37 | void __init r8a7790_pinmux_init(void) | |
38 | { | |
39 | platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, | |
40 | ARRAY_SIZE(pfc_resources)); | |
41 | } | |
42 | ||
55d9fab2 MD |
43 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ |
44 | .type = scif_type, \ | |
45 | .mapbase = baseaddr, \ | |
46 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | |
47 | .irqs = SCIx_IRQ_MUXED(irq) | |
48 | ||
49 | #define SCIFA_DATA(index, baseaddr, irq) \ | |
50 | [index] = { \ | |
51 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | |
52 | .scbrr_algo_id = SCBRR_ALGO_4, \ | |
53 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ | |
54 | } | |
55 | ||
56 | #define SCIFB_DATA(index, baseaddr, irq) \ | |
57 | [index] = { \ | |
58 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | |
59 | .scbrr_algo_id = SCBRR_ALGO_4, \ | |
60 | .scscr = SCSCR_RE | SCSCR_TE, \ | |
61 | } | |
62 | ||
63 | #define SCIF_DATA(index, baseaddr, irq) \ | |
64 | [index] = { \ | |
65 | SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ | |
66 | .scbrr_algo_id = SCBRR_ALGO_2, \ | |
67 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ | |
68 | } | |
69 | ||
d44f8308 UH |
70 | #define HSCIF_DATA(index, baseaddr, irq) \ |
71 | [index] = { \ | |
72 | SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ | |
73 | .scbrr_algo_id = SCBRR_ALGO_6, \ | |
74 | .scscr = SCSCR_RE | SCSCR_TE, \ | |
75 | } | |
76 | ||
77 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, | |
78 | HSCIF0, HSCIF1 }; | |
55d9fab2 MD |
79 | |
80 | static const struct plat_sci_port scif[] = { | |
81 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | |
82 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | |
83 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | |
84 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | |
85 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | |
86 | SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ | |
87 | SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ | |
88 | SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ | |
d44f8308 UH |
89 | HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */ |
90 | HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */ | |
55d9fab2 MD |
91 | }; |
92 | ||
93 | static inline void r8a7790_register_scif(int idx) | |
94 | { | |
95 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | |
96 | sizeof(struct plat_sci_port)); | |
97 | } | |
98 | ||
8f5ec0a5 MD |
99 | static struct renesas_irqc_config irqc0_data = { |
100 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ | |
101 | }; | |
102 | ||
103 | static struct resource irqc0_resources[] = { | |
104 | DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ | |
105 | DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ | |
106 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ | |
107 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ | |
108 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ | |
109 | }; | |
110 | ||
111 | #define r8a7790_register_irqc(idx) \ | |
112 | platform_device_register_resndata(&platform_bus, "renesas_irqc", \ | |
113 | idx, irqc##idx##_resources, \ | |
114 | ARRAY_SIZE(irqc##idx##_resources), \ | |
115 | &irqc##idx##_data, \ | |
116 | sizeof(struct renesas_irqc_config)) | |
117 | ||
0468b2d6 MD |
118 | void __init r8a7790_add_standard_devices(void) |
119 | { | |
55d9fab2 MD |
120 | r8a7790_register_scif(SCIFA0); |
121 | r8a7790_register_scif(SCIFA1); | |
122 | r8a7790_register_scif(SCIFB0); | |
123 | r8a7790_register_scif(SCIFB1); | |
124 | r8a7790_register_scif(SCIFB2); | |
125 | r8a7790_register_scif(SCIFA2); | |
126 | r8a7790_register_scif(SCIF0); | |
127 | r8a7790_register_scif(SCIF1); | |
d44f8308 UH |
128 | r8a7790_register_scif(HSCIF0); |
129 | r8a7790_register_scif(HSCIF1); | |
8f5ec0a5 | 130 | r8a7790_register_irqc(0); |
0468b2d6 MD |
131 | } |
132 | ||
ab5fdfd5 MD |
133 | void __init r8a7790_timer_init(void) |
134 | { | |
135 | void __iomem *cntcr; | |
136 | ||
137 | /* make sure arch timer is started by setting bit 0 of CNTCT */ | |
138 | cntcr = ioremap(0xe6080000, PAGE_SIZE); | |
139 | iowrite32(1, cntcr); | |
140 | iounmap(cntcr); | |
141 | ||
142 | shmobile_timer_init(); | |
143 | } | |
144 | ||
0468b2d6 MD |
145 | #ifdef CONFIG_USE_OF |
146 | void __init r8a7790_add_standard_devices_dt(void) | |
147 | { | |
148 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | |
149 | } | |
150 | ||
151 | static const char *r8a7790_boards_compat_dt[] __initdata = { | |
152 | "renesas,r8a7790", | |
153 | NULL, | |
154 | }; | |
155 | ||
156 | DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") | |
157 | .init_irq = irqchip_init, | |
158 | .init_machine = r8a7790_add_standard_devices_dt, | |
ab5fdfd5 | 159 | .init_time = r8a7790_timer_init, |
0468b2d6 MD |
160 | .dt_compat = r8a7790_boards_compat_dt, |
161 | MACHINE_END | |
162 | #endif /* CONFIG_USE_OF */ |