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6d9598e2 MD |
1 | /* |
2 | * sh73a0 processor support | |
3 | * | |
4 | * Copyright (C) 2010 Takashi Yoshii | |
5 | * Copyright (C) 2010 Magnus Damm | |
6 | * Copyright (C) 2008 Yoshihiro Shimoda | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | */ | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
4eca134f | 25 | #include <linux/irqchip.h> |
6d9598e2 | 26 | #include <linux/platform_device.h> |
48609533 | 27 | #include <linux/of_platform.h> |
6d9598e2 MD |
28 | #include <linux/delay.h> |
29 | #include <linux/input.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/serial_sci.h> | |
681e1b3e | 32 | #include <linux/sh_dma.h> |
6d9598e2 MD |
33 | #include <linux/sh_intc.h> |
34 | #include <linux/sh_timer.h> | |
9a27dee7 | 35 | #include <linux/platform_data/sh_ipmmu.h> |
341eb546 | 36 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> |
6088b422 | 37 | #include <mach/dma-register.h> |
6d9598e2 | 38 | #include <mach/hardware.h> |
250a2723 | 39 | #include <mach/irqs.h> |
681e1b3e | 40 | #include <mach/sh73a0.h> |
50e15c34 | 41 | #include <mach/common.h> |
6d9598e2 | 42 | #include <asm/mach-types.h> |
50e15c34 | 43 | #include <asm/mach/map.h> |
6d9598e2 | 44 | #include <asm/mach/arch.h> |
3be26fdb | 45 | #include <asm/mach/time.h> |
6d9598e2 | 46 | |
50e15c34 MD |
47 | static struct map_desc sh73a0_io_desc[] __initdata = { |
48 | /* create a 1:1 entity map for 0xe6xxxxxx | |
49 | * used by CPGA, INTC and PFC. | |
50 | */ | |
51 | { | |
52 | .virtual = 0xe6000000, | |
53 | .pfn = __phys_to_pfn(0xe6000000), | |
54 | .length = 256 << 20, | |
55 | .type = MT_DEVICE_NONSHARED | |
56 | }, | |
57 | }; | |
58 | ||
59 | void __init sh73a0_map_io(void) | |
60 | { | |
61 | iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); | |
62 | } | |
63 | ||
994d66a4 LP |
64 | static struct resource sh73a0_pfc_resources[] = { |
65 | [0] = { | |
66 | .start = 0xe6050000, | |
67 | .end = 0xe6057fff, | |
68 | .flags = IORESOURCE_MEM, | |
69 | }, | |
70 | [1] = { | |
71 | .start = 0xe605801c, | |
72 | .end = 0xe6058027, | |
73 | .flags = IORESOURCE_MEM, | |
74 | } | |
75 | }; | |
76 | ||
77 | static struct platform_device sh73a0_pfc_device = { | |
78 | .name = "pfc-sh73a0", | |
79 | .id = -1, | |
80 | .resource = sh73a0_pfc_resources, | |
81 | .num_resources = ARRAY_SIZE(sh73a0_pfc_resources), | |
82 | }; | |
83 | ||
84 | void __init sh73a0_pinmux_init(void) | |
85 | { | |
86 | platform_device_register(&sh73a0_pfc_device); | |
87 | } | |
88 | ||
6d9598e2 MD |
89 | static struct plat_sci_port scif0_platform_data = { |
90 | .mapbase = 0xe6c40000, | |
91 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
92 | .scscr = SCSCR_RE | SCSCR_TE, |
93 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
94 | .type = PORT_SCIFA, |
95 | .irqs = { gic_spi(72), gic_spi(72), | |
96 | gic_spi(72), gic_spi(72) }, | |
97 | }; | |
98 | ||
99 | static struct platform_device scif0_device = { | |
100 | .name = "sh-sci", | |
101 | .id = 0, | |
102 | .dev = { | |
103 | .platform_data = &scif0_platform_data, | |
104 | }, | |
105 | }; | |
106 | ||
107 | static struct plat_sci_port scif1_platform_data = { | |
108 | .mapbase = 0xe6c50000, | |
109 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
110 | .scscr = SCSCR_RE | SCSCR_TE, |
111 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
112 | .type = PORT_SCIFA, |
113 | .irqs = { gic_spi(73), gic_spi(73), | |
114 | gic_spi(73), gic_spi(73) }, | |
115 | }; | |
116 | ||
117 | static struct platform_device scif1_device = { | |
118 | .name = "sh-sci", | |
119 | .id = 1, | |
120 | .dev = { | |
121 | .platform_data = &scif1_platform_data, | |
122 | }, | |
123 | }; | |
124 | ||
125 | static struct plat_sci_port scif2_platform_data = { | |
126 | .mapbase = 0xe6c60000, | |
127 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
128 | .scscr = SCSCR_RE | SCSCR_TE, |
129 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
130 | .type = PORT_SCIFA, |
131 | .irqs = { gic_spi(74), gic_spi(74), | |
132 | gic_spi(74), gic_spi(74) }, | |
133 | }; | |
134 | ||
135 | static struct platform_device scif2_device = { | |
136 | .name = "sh-sci", | |
137 | .id = 2, | |
138 | .dev = { | |
139 | .platform_data = &scif2_platform_data, | |
140 | }, | |
141 | }; | |
142 | ||
143 | static struct plat_sci_port scif3_platform_data = { | |
144 | .mapbase = 0xe6c70000, | |
145 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
146 | .scscr = SCSCR_RE | SCSCR_TE, |
147 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
148 | .type = PORT_SCIFA, |
149 | .irqs = { gic_spi(75), gic_spi(75), | |
150 | gic_spi(75), gic_spi(75) }, | |
151 | }; | |
152 | ||
153 | static struct platform_device scif3_device = { | |
154 | .name = "sh-sci", | |
155 | .id = 3, | |
156 | .dev = { | |
157 | .platform_data = &scif3_platform_data, | |
158 | }, | |
159 | }; | |
160 | ||
161 | static struct plat_sci_port scif4_platform_data = { | |
162 | .mapbase = 0xe6c80000, | |
163 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
164 | .scscr = SCSCR_RE | SCSCR_TE, |
165 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
166 | .type = PORT_SCIFA, |
167 | .irqs = { gic_spi(78), gic_spi(78), | |
168 | gic_spi(78), gic_spi(78) }, | |
169 | }; | |
170 | ||
171 | static struct platform_device scif4_device = { | |
172 | .name = "sh-sci", | |
173 | .id = 4, | |
174 | .dev = { | |
175 | .platform_data = &scif4_platform_data, | |
176 | }, | |
177 | }; | |
178 | ||
179 | static struct plat_sci_port scif5_platform_data = { | |
180 | .mapbase = 0xe6cb0000, | |
181 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
182 | .scscr = SCSCR_RE | SCSCR_TE, |
183 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
184 | .type = PORT_SCIFA, |
185 | .irqs = { gic_spi(79), gic_spi(79), | |
186 | gic_spi(79), gic_spi(79) }, | |
187 | }; | |
188 | ||
189 | static struct platform_device scif5_device = { | |
190 | .name = "sh-sci", | |
191 | .id = 5, | |
192 | .dev = { | |
193 | .platform_data = &scif5_platform_data, | |
194 | }, | |
195 | }; | |
196 | ||
197 | static struct plat_sci_port scif6_platform_data = { | |
198 | .mapbase = 0xe6cc0000, | |
199 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
200 | .scscr = SCSCR_RE | SCSCR_TE, |
201 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
202 | .type = PORT_SCIFA, |
203 | .irqs = { gic_spi(156), gic_spi(156), | |
204 | gic_spi(156), gic_spi(156) }, | |
205 | }; | |
206 | ||
207 | static struct platform_device scif6_device = { | |
208 | .name = "sh-sci", | |
209 | .id = 6, | |
210 | .dev = { | |
211 | .platform_data = &scif6_platform_data, | |
212 | }, | |
213 | }; | |
214 | ||
215 | static struct plat_sci_port scif7_platform_data = { | |
216 | .mapbase = 0xe6cd0000, | |
217 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
218 | .scscr = SCSCR_RE | SCSCR_TE, |
219 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
220 | .type = PORT_SCIFA, |
221 | .irqs = { gic_spi(143), gic_spi(143), | |
222 | gic_spi(143), gic_spi(143) }, | |
223 | }; | |
224 | ||
225 | static struct platform_device scif7_device = { | |
226 | .name = "sh-sci", | |
227 | .id = 7, | |
228 | .dev = { | |
229 | .platform_data = &scif7_platform_data, | |
230 | }, | |
231 | }; | |
232 | ||
233 | static struct plat_sci_port scif8_platform_data = { | |
234 | .mapbase = 0xe6c30000, | |
235 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
236 | .scscr = SCSCR_RE | SCSCR_TE, |
237 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
238 | .type = PORT_SCIFB, |
239 | .irqs = { gic_spi(80), gic_spi(80), | |
240 | gic_spi(80), gic_spi(80) }, | |
241 | }; | |
242 | ||
243 | static struct platform_device scif8_device = { | |
244 | .name = "sh-sci", | |
245 | .id = 8, | |
246 | .dev = { | |
247 | .platform_data = &scif8_platform_data, | |
248 | }, | |
249 | }; | |
250 | ||
251 | static struct sh_timer_config cmt10_platform_data = { | |
252 | .name = "CMT10", | |
253 | .channel_offset = 0x10, | |
254 | .timer_bit = 0, | |
255 | .clockevent_rating = 125, | |
256 | .clocksource_rating = 125, | |
257 | }; | |
258 | ||
259 | static struct resource cmt10_resources[] = { | |
260 | [0] = { | |
261 | .name = "CMT10", | |
262 | .start = 0xe6138010, | |
263 | .end = 0xe613801b, | |
264 | .flags = IORESOURCE_MEM, | |
265 | }, | |
266 | [1] = { | |
267 | .start = gic_spi(65), | |
268 | .flags = IORESOURCE_IRQ, | |
269 | }, | |
270 | }; | |
271 | ||
272 | static struct platform_device cmt10_device = { | |
273 | .name = "sh_cmt", | |
274 | .id = 10, | |
275 | .dev = { | |
276 | .platform_data = &cmt10_platform_data, | |
277 | }, | |
278 | .resource = cmt10_resources, | |
279 | .num_resources = ARRAY_SIZE(cmt10_resources), | |
280 | }; | |
281 | ||
5010f3db MD |
282 | /* TMU */ |
283 | static struct sh_timer_config tmu00_platform_data = { | |
284 | .name = "TMU00", | |
285 | .channel_offset = 0x4, | |
286 | .timer_bit = 0, | |
287 | .clockevent_rating = 200, | |
288 | }; | |
289 | ||
290 | static struct resource tmu00_resources[] = { | |
abbec5f4 | 291 | [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"), |
5010f3db MD |
292 | [1] = { |
293 | .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ | |
294 | .flags = IORESOURCE_IRQ, | |
295 | }, | |
296 | }; | |
297 | ||
298 | static struct platform_device tmu00_device = { | |
299 | .name = "sh_tmu", | |
300 | .id = 0, | |
301 | .dev = { | |
302 | .platform_data = &tmu00_platform_data, | |
303 | }, | |
304 | .resource = tmu00_resources, | |
305 | .num_resources = ARRAY_SIZE(tmu00_resources), | |
306 | }; | |
307 | ||
308 | static struct sh_timer_config tmu01_platform_data = { | |
309 | .name = "TMU01", | |
310 | .channel_offset = 0x10, | |
311 | .timer_bit = 1, | |
312 | .clocksource_rating = 200, | |
313 | }; | |
314 | ||
315 | static struct resource tmu01_resources[] = { | |
abbec5f4 | 316 | [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"), |
5010f3db MD |
317 | [1] = { |
318 | .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ | |
319 | .flags = IORESOURCE_IRQ, | |
320 | }, | |
321 | }; | |
322 | ||
323 | static struct platform_device tmu01_device = { | |
324 | .name = "sh_tmu", | |
325 | .id = 1, | |
326 | .dev = { | |
327 | .platform_data = &tmu01_platform_data, | |
328 | }, | |
329 | .resource = tmu01_resources, | |
330 | .num_resources = ARRAY_SIZE(tmu01_resources), | |
331 | }; | |
332 | ||
b028f94b | 333 | static struct resource i2c0_resources[] = { |
abbec5f4 | 334 | [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"), |
b028f94b TY |
335 | [1] = { |
336 | .start = gic_spi(167), | |
337 | .end = gic_spi(170), | |
338 | .flags = IORESOURCE_IRQ, | |
339 | }, | |
340 | }; | |
341 | ||
342 | static struct resource i2c1_resources[] = { | |
abbec5f4 | 343 | [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"), |
b028f94b TY |
344 | [1] = { |
345 | .start = gic_spi(51), | |
346 | .end = gic_spi(54), | |
347 | .flags = IORESOURCE_IRQ, | |
348 | }, | |
349 | }; | |
350 | ||
351 | static struct resource i2c2_resources[] = { | |
abbec5f4 | 352 | [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"), |
b028f94b TY |
353 | [1] = { |
354 | .start = gic_spi(171), | |
355 | .end = gic_spi(174), | |
356 | .flags = IORESOURCE_IRQ, | |
357 | }, | |
358 | }; | |
359 | ||
360 | static struct resource i2c3_resources[] = { | |
abbec5f4 | 361 | [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"), |
b028f94b TY |
362 | [1] = { |
363 | .start = gic_spi(183), | |
364 | .end = gic_spi(186), | |
365 | .flags = IORESOURCE_IRQ, | |
366 | }, | |
367 | }; | |
368 | ||
369 | static struct resource i2c4_resources[] = { | |
abbec5f4 | 370 | [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"), |
b028f94b TY |
371 | [1] = { |
372 | .start = gic_spi(187), | |
373 | .end = gic_spi(190), | |
374 | .flags = IORESOURCE_IRQ, | |
375 | }, | |
376 | }; | |
377 | ||
378 | static struct platform_device i2c0_device = { | |
379 | .name = "i2c-sh_mobile", | |
380 | .id = 0, | |
381 | .resource = i2c0_resources, | |
382 | .num_resources = ARRAY_SIZE(i2c0_resources), | |
383 | }; | |
384 | ||
385 | static struct platform_device i2c1_device = { | |
386 | .name = "i2c-sh_mobile", | |
387 | .id = 1, | |
388 | .resource = i2c1_resources, | |
389 | .num_resources = ARRAY_SIZE(i2c1_resources), | |
390 | }; | |
391 | ||
392 | static struct platform_device i2c2_device = { | |
393 | .name = "i2c-sh_mobile", | |
394 | .id = 2, | |
395 | .resource = i2c2_resources, | |
396 | .num_resources = ARRAY_SIZE(i2c2_resources), | |
397 | }; | |
398 | ||
399 | static struct platform_device i2c3_device = { | |
400 | .name = "i2c-sh_mobile", | |
401 | .id = 3, | |
402 | .resource = i2c3_resources, | |
403 | .num_resources = ARRAY_SIZE(i2c3_resources), | |
404 | }; | |
405 | ||
406 | static struct platform_device i2c4_device = { | |
407 | .name = "i2c-sh_mobile", | |
408 | .id = 4, | |
409 | .resource = i2c4_resources, | |
410 | .num_resources = ARRAY_SIZE(i2c4_resources), | |
411 | }; | |
412 | ||
681e1b3e MD |
413 | static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { |
414 | { | |
415 | .slave_id = SHDMA_SLAVE_SCIF0_TX, | |
416 | .addr = 0xe6c40020, | |
417 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
418 | .mid_rid = 0x21, | |
419 | }, { | |
420 | .slave_id = SHDMA_SLAVE_SCIF0_RX, | |
421 | .addr = 0xe6c40024, | |
422 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
423 | .mid_rid = 0x22, | |
424 | }, { | |
425 | .slave_id = SHDMA_SLAVE_SCIF1_TX, | |
426 | .addr = 0xe6c50020, | |
427 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
428 | .mid_rid = 0x25, | |
429 | }, { | |
430 | .slave_id = SHDMA_SLAVE_SCIF1_RX, | |
431 | .addr = 0xe6c50024, | |
432 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
433 | .mid_rid = 0x26, | |
434 | }, { | |
435 | .slave_id = SHDMA_SLAVE_SCIF2_TX, | |
436 | .addr = 0xe6c60020, | |
437 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
438 | .mid_rid = 0x29, | |
439 | }, { | |
440 | .slave_id = SHDMA_SLAVE_SCIF2_RX, | |
441 | .addr = 0xe6c60024, | |
442 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
443 | .mid_rid = 0x2a, | |
444 | }, { | |
445 | .slave_id = SHDMA_SLAVE_SCIF3_TX, | |
446 | .addr = 0xe6c70020, | |
447 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
448 | .mid_rid = 0x2d, | |
449 | }, { | |
450 | .slave_id = SHDMA_SLAVE_SCIF3_RX, | |
451 | .addr = 0xe6c70024, | |
452 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
453 | .mid_rid = 0x2e, | |
454 | }, { | |
455 | .slave_id = SHDMA_SLAVE_SCIF4_TX, | |
456 | .addr = 0xe6c80020, | |
457 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
458 | .mid_rid = 0x39, | |
459 | }, { | |
460 | .slave_id = SHDMA_SLAVE_SCIF4_RX, | |
461 | .addr = 0xe6c80024, | |
462 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
463 | .mid_rid = 0x3a, | |
464 | }, { | |
465 | .slave_id = SHDMA_SLAVE_SCIF5_TX, | |
466 | .addr = 0xe6cb0020, | |
467 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
468 | .mid_rid = 0x35, | |
469 | }, { | |
470 | .slave_id = SHDMA_SLAVE_SCIF5_RX, | |
471 | .addr = 0xe6cb0024, | |
472 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
473 | .mid_rid = 0x36, | |
474 | }, { | |
475 | .slave_id = SHDMA_SLAVE_SCIF6_TX, | |
476 | .addr = 0xe6cc0020, | |
477 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
478 | .mid_rid = 0x1d, | |
479 | }, { | |
480 | .slave_id = SHDMA_SLAVE_SCIF6_RX, | |
481 | .addr = 0xe6cc0024, | |
482 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
483 | .mid_rid = 0x1e, | |
484 | }, { | |
485 | .slave_id = SHDMA_SLAVE_SCIF7_TX, | |
486 | .addr = 0xe6cd0020, | |
487 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
488 | .mid_rid = 0x19, | |
489 | }, { | |
490 | .slave_id = SHDMA_SLAVE_SCIF7_RX, | |
491 | .addr = 0xe6cd0024, | |
492 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
493 | .mid_rid = 0x1a, | |
494 | }, { | |
495 | .slave_id = SHDMA_SLAVE_SCIF8_TX, | |
496 | .addr = 0xe6c30040, | |
497 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
498 | .mid_rid = 0x3d, | |
499 | }, { | |
500 | .slave_id = SHDMA_SLAVE_SCIF8_RX, | |
501 | .addr = 0xe6c30060, | |
502 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
503 | .mid_rid = 0x3e, | |
504 | }, { | |
505 | .slave_id = SHDMA_SLAVE_SDHI0_TX, | |
506 | .addr = 0xee100030, | |
507 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
508 | .mid_rid = 0xc1, | |
509 | }, { | |
510 | .slave_id = SHDMA_SLAVE_SDHI0_RX, | |
511 | .addr = 0xee100030, | |
512 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
513 | .mid_rid = 0xc2, | |
514 | }, { | |
515 | .slave_id = SHDMA_SLAVE_SDHI1_TX, | |
516 | .addr = 0xee120030, | |
517 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
518 | .mid_rid = 0xc9, | |
519 | }, { | |
520 | .slave_id = SHDMA_SLAVE_SDHI1_RX, | |
521 | .addr = 0xee120030, | |
522 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
523 | .mid_rid = 0xca, | |
524 | }, { | |
525 | .slave_id = SHDMA_SLAVE_SDHI2_TX, | |
526 | .addr = 0xee140030, | |
527 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
528 | .mid_rid = 0xcd, | |
529 | }, { | |
530 | .slave_id = SHDMA_SLAVE_SDHI2_RX, | |
531 | .addr = 0xee140030, | |
532 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
533 | .mid_rid = 0xce, | |
534 | }, { | |
535 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | |
536 | .addr = 0xe6bd0034, | |
537 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
538 | .mid_rid = 0xd1, | |
539 | }, { | |
540 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | |
541 | .addr = 0xe6bd0034, | |
542 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
543 | .mid_rid = 0xd2, | |
544 | }, | |
545 | }; | |
546 | ||
547 | #define DMAE_CHANNEL(_offset) \ | |
548 | { \ | |
549 | .offset = _offset - 0x20, \ | |
550 | .dmars = _offset - 0x20 + 0x40, \ | |
551 | } | |
552 | ||
553 | static const struct sh_dmae_channel sh73a0_dmae_channels[] = { | |
554 | DMAE_CHANNEL(0x8000), | |
555 | DMAE_CHANNEL(0x8080), | |
556 | DMAE_CHANNEL(0x8100), | |
557 | DMAE_CHANNEL(0x8180), | |
558 | DMAE_CHANNEL(0x8200), | |
559 | DMAE_CHANNEL(0x8280), | |
560 | DMAE_CHANNEL(0x8300), | |
561 | DMAE_CHANNEL(0x8380), | |
562 | DMAE_CHANNEL(0x8400), | |
563 | DMAE_CHANNEL(0x8480), | |
564 | DMAE_CHANNEL(0x8500), | |
565 | DMAE_CHANNEL(0x8580), | |
566 | DMAE_CHANNEL(0x8600), | |
567 | DMAE_CHANNEL(0x8680), | |
568 | DMAE_CHANNEL(0x8700), | |
569 | DMAE_CHANNEL(0x8780), | |
570 | DMAE_CHANNEL(0x8800), | |
571 | DMAE_CHANNEL(0x8880), | |
572 | DMAE_CHANNEL(0x8900), | |
573 | DMAE_CHANNEL(0x8980), | |
574 | }; | |
575 | ||
681e1b3e MD |
576 | static struct sh_dmae_pdata sh73a0_dmae_platform_data = { |
577 | .slave = sh73a0_dmae_slaves, | |
578 | .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), | |
579 | .channel = sh73a0_dmae_channels, | |
580 | .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), | |
6088b422 KM |
581 | .ts_low_shift = TS_LOW_SHIFT, |
582 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | |
583 | .ts_high_shift = TS_HI_SHIFT, | |
584 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | |
585 | .ts_shift = dma_ts_shift, | |
586 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | |
681e1b3e MD |
587 | .dmaor_init = DMAOR_DME, |
588 | }; | |
589 | ||
590 | static struct resource sh73a0_dmae_resources[] = { | |
abbec5f4 | 591 | DEFINE_RES_MEM(0xfe000020, 0x89e0), |
681e1b3e | 592 | { |
20052462 | 593 | .name = "error_irq", |
681e1b3e MD |
594 | .start = gic_spi(129), |
595 | .end = gic_spi(129), | |
596 | .flags = IORESOURCE_IRQ, | |
597 | }, | |
598 | { | |
599 | /* IRQ for channels 0-19 */ | |
600 | .start = gic_spi(109), | |
601 | .end = gic_spi(128), | |
602 | .flags = IORESOURCE_IRQ, | |
603 | }, | |
604 | }; | |
605 | ||
606 | static struct platform_device dma0_device = { | |
607 | .name = "sh-dma-engine", | |
608 | .id = 0, | |
609 | .resource = sh73a0_dmae_resources, | |
610 | .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), | |
611 | .dev = { | |
612 | .platform_data = &sh73a0_dmae_platform_data, | |
613 | }, | |
614 | }; | |
615 | ||
832290b2 KM |
616 | /* MPDMAC */ |
617 | static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { | |
618 | { | |
619 | .slave_id = SHDMA_SLAVE_FSI2A_RX, | |
620 | .addr = 0xec230020, | |
621 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
622 | .mid_rid = 0xd6, /* CHECK ME */ | |
623 | }, { | |
624 | .slave_id = SHDMA_SLAVE_FSI2A_TX, | |
625 | .addr = 0xec230024, | |
626 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
627 | .mid_rid = 0xd5, /* CHECK ME */ | |
628 | }, { | |
629 | .slave_id = SHDMA_SLAVE_FSI2C_RX, | |
630 | .addr = 0xec230060, | |
631 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
632 | .mid_rid = 0xda, /* CHECK ME */ | |
633 | }, { | |
634 | .slave_id = SHDMA_SLAVE_FSI2C_TX, | |
635 | .addr = 0xec230064, | |
636 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
637 | .mid_rid = 0xd9, /* CHECK ME */ | |
638 | }, { | |
639 | .slave_id = SHDMA_SLAVE_FSI2B_RX, | |
640 | .addr = 0xec240020, | |
641 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
642 | .mid_rid = 0x8e, /* CHECK ME */ | |
643 | }, { | |
644 | .slave_id = SHDMA_SLAVE_FSI2B_TX, | |
645 | .addr = 0xec240024, | |
646 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
647 | .mid_rid = 0x8d, /* CHECK ME */ | |
648 | }, { | |
649 | .slave_id = SHDMA_SLAVE_FSI2D_RX, | |
650 | .addr = 0xec240060, | |
651 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
652 | .mid_rid = 0x9a, /* CHECK ME */ | |
653 | }, | |
654 | }; | |
655 | ||
656 | #define MPDMA_CHANNEL(a, b, c) \ | |
657 | { \ | |
658 | .offset = a, \ | |
659 | .dmars = b, \ | |
660 | .dmars_bit = c, \ | |
661 | .chclr_offset = (0x220 - 0x20) + a \ | |
662 | } | |
663 | ||
664 | static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { | |
665 | MPDMA_CHANNEL(0x00, 0, 0), | |
666 | MPDMA_CHANNEL(0x10, 0, 8), | |
667 | MPDMA_CHANNEL(0x20, 4, 0), | |
668 | MPDMA_CHANNEL(0x30, 4, 8), | |
669 | MPDMA_CHANNEL(0x50, 8, 0), | |
670 | MPDMA_CHANNEL(0x70, 8, 8), | |
671 | }; | |
672 | ||
673 | static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { | |
674 | .slave = sh73a0_mpdma_slaves, | |
675 | .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), | |
676 | .channel = sh73a0_mpdma_channels, | |
677 | .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), | |
6088b422 KM |
678 | .ts_low_shift = TS_LOW_SHIFT, |
679 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | |
680 | .ts_high_shift = TS_HI_SHIFT, | |
681 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | |
682 | .ts_shift = dma_ts_shift, | |
683 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | |
832290b2 KM |
684 | .dmaor_init = DMAOR_DME, |
685 | .chclr_present = 1, | |
686 | }; | |
687 | ||
688 | /* Resource order important! */ | |
689 | static struct resource sh73a0_mpdma_resources[] = { | |
abbec5f4 SH |
690 | /* Channel registers and DMAOR */ |
691 | DEFINE_RES_MEM(0xec618020, 0x270), | |
692 | /* DMARSx */ | |
693 | DEFINE_RES_MEM(0xec619000, 0xc), | |
832290b2 KM |
694 | { |
695 | .name = "error_irq", | |
696 | .start = gic_spi(181), | |
697 | .end = gic_spi(181), | |
698 | .flags = IORESOURCE_IRQ, | |
699 | }, | |
700 | { | |
701 | /* IRQ for channels 0-5 */ | |
702 | .start = gic_spi(175), | |
703 | .end = gic_spi(180), | |
704 | .flags = IORESOURCE_IRQ, | |
705 | }, | |
706 | }; | |
707 | ||
708 | static struct platform_device mpdma0_device = { | |
709 | .name = "sh-dma-engine", | |
710 | .id = 1, | |
711 | .resource = sh73a0_mpdma_resources, | |
712 | .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), | |
713 | .dev = { | |
714 | .platform_data = &sh73a0_mpdma_platform_data, | |
715 | }, | |
716 | }; | |
717 | ||
f23f5be0 TK |
718 | static struct resource pmu_resources[] = { |
719 | [0] = { | |
720 | .start = gic_spi(55), | |
721 | .end = gic_spi(55), | |
722 | .flags = IORESOURCE_IRQ, | |
723 | }, | |
724 | [1] = { | |
725 | .start = gic_spi(56), | |
726 | .end = gic_spi(56), | |
727 | .flags = IORESOURCE_IRQ, | |
728 | }, | |
729 | }; | |
730 | ||
731 | static struct platform_device pmu_device = { | |
732 | .name = "arm-pmu", | |
733 | .id = -1, | |
734 | .num_resources = ARRAY_SIZE(pmu_resources), | |
735 | .resource = pmu_resources, | |
736 | }; | |
737 | ||
9a27dee7 HE |
738 | /* an IPMMU module for ICB */ |
739 | static struct resource ipmmu_resources[] = { | |
abbec5f4 | 740 | DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"), |
9a27dee7 HE |
741 | }; |
742 | ||
743 | static const char * const ipmmu_dev_names[] = { | |
744 | "sh_mobile_lcdc_fb.0", | |
745 | }; | |
746 | ||
747 | static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { | |
748 | .dev_names = ipmmu_dev_names, | |
749 | .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), | |
750 | }; | |
751 | ||
752 | static struct platform_device ipmmu_device = { | |
753 | .name = "ipmmu", | |
754 | .id = -1, | |
755 | .dev = { | |
756 | .platform_data = &ipmmu_platform_data, | |
757 | }, | |
758 | .resource = ipmmu_resources, | |
759 | .num_resources = ARRAY_SIZE(ipmmu_resources), | |
760 | }; | |
761 | ||
1461f8b6 | 762 | static struct renesas_intc_irqpin_config irqpin0_platform_data = { |
341eb546 MD |
763 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ |
764 | }; | |
765 | ||
766 | static struct resource irqpin0_resources[] = { | |
767 | DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ | |
768 | DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ | |
769 | DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ | |
770 | DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ | |
771 | DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ | |
772 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ | |
773 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ | |
774 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ | |
775 | DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ | |
776 | DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ | |
777 | DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ | |
778 | DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ | |
779 | DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ | |
780 | }; | |
781 | ||
782 | static struct platform_device irqpin0_device = { | |
783 | .name = "renesas_intc_irqpin", | |
784 | .id = 0, | |
785 | .resource = irqpin0_resources, | |
786 | .num_resources = ARRAY_SIZE(irqpin0_resources), | |
787 | .dev = { | |
788 | .platform_data = &irqpin0_platform_data, | |
789 | }, | |
790 | }; | |
791 | ||
1461f8b6 | 792 | static struct renesas_intc_irqpin_config irqpin1_platform_data = { |
341eb546 MD |
793 | .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ |
794 | .control_parent = true, /* Disable spurious IRQ10 */ | |
795 | }; | |
796 | ||
797 | static struct resource irqpin1_resources[] = { | |
798 | DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ | |
799 | DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ | |
800 | DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ | |
801 | DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ | |
802 | DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ | |
803 | DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ | |
804 | DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ | |
805 | DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ | |
806 | DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ | |
807 | DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ | |
808 | DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ | |
809 | DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ | |
810 | DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ | |
811 | }; | |
812 | ||
813 | static struct platform_device irqpin1_device = { | |
814 | .name = "renesas_intc_irqpin", | |
815 | .id = 1, | |
816 | .resource = irqpin1_resources, | |
817 | .num_resources = ARRAY_SIZE(irqpin1_resources), | |
818 | .dev = { | |
819 | .platform_data = &irqpin1_platform_data, | |
820 | }, | |
821 | }; | |
822 | ||
1461f8b6 | 823 | static struct renesas_intc_irqpin_config irqpin2_platform_data = { |
341eb546 MD |
824 | .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ |
825 | }; | |
826 | ||
827 | static struct resource irqpin2_resources[] = { | |
828 | DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ | |
829 | DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ | |
830 | DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ | |
831 | DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ | |
832 | DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ | |
833 | DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ | |
834 | DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ | |
835 | DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ | |
836 | DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ | |
837 | DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ | |
838 | DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ | |
839 | DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ | |
840 | DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ | |
841 | }; | |
842 | ||
843 | static struct platform_device irqpin2_device = { | |
844 | .name = "renesas_intc_irqpin", | |
845 | .id = 2, | |
846 | .resource = irqpin2_resources, | |
847 | .num_resources = ARRAY_SIZE(irqpin2_resources), | |
848 | .dev = { | |
849 | .platform_data = &irqpin2_platform_data, | |
850 | }, | |
851 | }; | |
852 | ||
1461f8b6 | 853 | static struct renesas_intc_irqpin_config irqpin3_platform_data = { |
341eb546 MD |
854 | .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ |
855 | }; | |
856 | ||
857 | static struct resource irqpin3_resources[] = { | |
858 | DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ | |
859 | DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ | |
860 | DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ | |
861 | DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ | |
862 | DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ | |
863 | DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ | |
864 | DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ | |
865 | DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ | |
866 | DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ | |
867 | DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ | |
868 | DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ | |
869 | DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ | |
870 | DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ | |
871 | }; | |
872 | ||
873 | static struct platform_device irqpin3_device = { | |
874 | .name = "renesas_intc_irqpin", | |
875 | .id = 3, | |
876 | .resource = irqpin3_resources, | |
877 | .num_resources = ARRAY_SIZE(irqpin3_resources), | |
878 | .dev = { | |
879 | .platform_data = &irqpin3_platform_data, | |
880 | }, | |
881 | }; | |
882 | ||
3b00f934 | 883 | static struct platform_device *sh73a0_devices_dt[] __initdata = { |
6d9598e2 MD |
884 | &scif0_device, |
885 | &scif1_device, | |
886 | &scif2_device, | |
887 | &scif3_device, | |
888 | &scif4_device, | |
889 | &scif5_device, | |
890 | &scif6_device, | |
891 | &scif7_device, | |
892 | &scif8_device, | |
893 | &cmt10_device, | |
48609533 SH |
894 | }; |
895 | ||
896 | static struct platform_device *sh73a0_early_devices[] __initdata = { | |
5010f3db MD |
897 | &tmu00_device, |
898 | &tmu01_device, | |
9a27dee7 | 899 | &ipmmu_device, |
6d9598e2 MD |
900 | }; |
901 | ||
b028f94b TY |
902 | static struct platform_device *sh73a0_late_devices[] __initdata = { |
903 | &i2c0_device, | |
904 | &i2c1_device, | |
905 | &i2c2_device, | |
906 | &i2c3_device, | |
907 | &i2c4_device, | |
681e1b3e | 908 | &dma0_device, |
832290b2 | 909 | &mpdma0_device, |
f23f5be0 | 910 | &pmu_device, |
341eb546 MD |
911 | &irqpin0_device, |
912 | &irqpin1_device, | |
913 | &irqpin2_device, | |
914 | &irqpin3_device, | |
b028f94b TY |
915 | }; |
916 | ||
0a4b04dc | 917 | #define SRCR2 IOMEM(0xe61580b0) |
681e1b3e | 918 | |
6d9598e2 MD |
919 | void __init sh73a0_add_standard_devices(void) |
920 | { | |
681e1b3e MD |
921 | /* Clear software reset bit on SY-DMAC module */ |
922 | __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); | |
923 | ||
3b00f934 SH |
924 | platform_add_devices(sh73a0_devices_dt, |
925 | ARRAY_SIZE(sh73a0_devices_dt)); | |
6d9598e2 MD |
926 | platform_add_devices(sh73a0_early_devices, |
927 | ARRAY_SIZE(sh73a0_early_devices)); | |
b028f94b TY |
928 | platform_add_devices(sh73a0_late_devices, |
929 | ARRAY_SIZE(sh73a0_late_devices)); | |
6d9598e2 MD |
930 | } |
931 | ||
d6720003 KM |
932 | /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ |
933 | void __init __weak sh73a0_register_twd(void) { } | |
934 | ||
6bb27d73 | 935 | void __init sh73a0_earlytimer_init(void) |
3be26fdb MD |
936 | { |
937 | sh73a0_clock_init(); | |
938 | shmobile_earlytimer_init(); | |
d6720003 | 939 | sh73a0_register_twd(); |
3be26fdb MD |
940 | } |
941 | ||
6d9598e2 MD |
942 | void __init sh73a0_add_early_devices(void) |
943 | { | |
3b00f934 SH |
944 | early_platform_add_devices(sh73a0_devices_dt, |
945 | ARRAY_SIZE(sh73a0_devices_dt)); | |
6d9598e2 MD |
946 | early_platform_add_devices(sh73a0_early_devices, |
947 | ARRAY_SIZE(sh73a0_early_devices)); | |
50e15c34 MD |
948 | |
949 | /* setup early console here as well */ | |
950 | shmobile_setup_console(); | |
6d9598e2 | 951 | } |
48609533 SH |
952 | |
953 | #ifdef CONFIG_USE_OF | |
954 | ||
3b00f934 | 955 | void __init sh73a0_init_delay(void) |
48609533 SH |
956 | { |
957 | shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ | |
48609533 SH |
958 | } |
959 | ||
960 | static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { | |
961 | {}, | |
962 | }; | |
963 | ||
964 | void __init sh73a0_add_standard_devices_dt(void) | |
965 | { | |
d2347382 GL |
966 | struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; |
967 | ||
48609533 SH |
968 | /* clocks are setup late during boot in the case of DT */ |
969 | sh73a0_clock_init(); | |
970 | ||
3b00f934 SH |
971 | platform_add_devices(sh73a0_devices_dt, |
972 | ARRAY_SIZE(sh73a0_devices_dt)); | |
48609533 SH |
973 | of_platform_populate(NULL, of_default_bus_match_table, |
974 | sh73a0_auxdata_lookup, NULL); | |
d2347382 GL |
975 | |
976 | /* Instantiate cpufreq-cpu0 */ | |
977 | platform_device_register_full(&devinfo); | |
48609533 SH |
978 | } |
979 | ||
980 | static const char *sh73a0_boards_compat_dt[] __initdata = { | |
981 | "renesas,sh73a0", | |
982 | NULL, | |
983 | }; | |
984 | ||
985 | DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") | |
f9989507 | 986 | .smp = smp_ops(sh73a0_smp_ops), |
48609533 | 987 | .map_io = sh73a0_map_io, |
3b00f934 | 988 | .init_early = sh73a0_init_delay, |
48609533 | 989 | .nr_irqs = NR_IRQS_LEGACY, |
4eca134f | 990 | .init_irq = irqchip_init, |
48609533 | 991 | .init_machine = sh73a0_add_standard_devices_dt, |
48609533 SH |
992 | .dt_compat = sh73a0_boards_compat_dt, |
993 | MACHINE_END | |
994 | #endif /* CONFIG_USE_OF */ |