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[mirror_ubuntu-eoan-kernel.git] / arch / arm / mach-shmobile / setup-sh73a0.c
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6d9598e2
MD		 1/*
2 * sh73a0 processor support
3 *
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
48609533 26#include <linux/of_platform.h>
6d9598e2
MD		 27#include <linux/delay.h>
28#include <linux/input.h>
b207422b 29#include <linux/i2c/i2c-sh_mobile.h>
6d9598e2
MD		 30#include <linux/io.h>
31#include <linux/serial_sci.h>
681e1b3e 32#include <linux/sh_dma.h>
6d9598e2 33#include <linux/sh_timer.h>
9a27dee7 34#include <linux/platform_data/sh_ipmmu.h>
341eb546 35#include <linux/platform_data/irq-renesas-intc-irqpin.h>
ded59d6d 36
6d9598e2 37#include <asm/mach-types.h>
50e15c34 38#include <asm/mach/map.h>
6d9598e2 39#include <asm/mach/arch.h>
3be26fdb 40#include <asm/mach/time.h>
ded59d6d 41
fd44aa5e 42#include "common.h"
74ac0de8 43#include "dma-register.h"
86155b35 44#include "intc.h"
b6bab126 45#include "irqs.h"
ded59d6d 46#include "sh73a0.h"
6d9598e2 47
50e15c34
MD		 48static struct map_desc sh73a0_io_desc[] __initdata = {
49 /* create a 1:1 entity map for 0xe6xxxxxx
50 * used by CPGA, INTC and PFC.
51 */
52 {
53 .virtual = 0xe6000000,
54 .pfn = __phys_to_pfn(0xe6000000),
55 .length = 256 << 20,
56 .type = MT_DEVICE_NONSHARED
57 },
58};
59
60void __init sh73a0_map_io(void)
61{
62 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
63}
64
474f6758
MD		 65/* PFC */
66static struct resource pfc_resources[] __initdata = {
67 DEFINE_RES_MEM(0xe6050000, 0x8000),
68 DEFINE_RES_MEM(0xe605801c, 0x000c),
994d66a4
LP		 69};
70
71void __init sh73a0_pinmux_init(void)
72{
474f6758
MD		 73 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
74 ARRAY_SIZE(pfc_resources));
994d66a4
LP		 75}
76
d000fff9
LP		 77/* SCIF */
78#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
79static struct plat_sci_port scif##index##_platform_data = { \
80 .type = scif_type, \
d000fff9 81 .flags = UPF_BOOT_AUTOCONF, \
d000fff9
LP		 82 .scscr = SCSCR_RE | SCSCR_TE, \
83}; \
84 \
31e1ee86
LP		 85static struct resource scif##index##_resources[] = { \
86 DEFINE_RES_MEM(baseaddr, 0x100), \
87 DEFINE_RES_IRQ(irq), \
88}; \
89 \
d000fff9
LP		 90static struct platform_device scif##index##_device = { \
91 .name = "sh-sci", \
92 .id = index, \
31e1ee86
LP		 93 .resource = scif##index##_resources, \
94 .num_resources = ARRAY_SIZE(scif##index##_resources), \
d000fff9
LP		 95 .dev = { \
96 .platform_data = &scif##index##_platform_data, \
97 }, \
98}
6d9598e2 99
d000fff9
LP		 100SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
101SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
102SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
103SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
104SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
105SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
106SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
107SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
108SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
6d9598e2 109
652256fd
LP		 110static struct sh_timer_config cmt1_platform_data = {
111 .channels_mask = 0x3f,
6d9598e2
MD		 112};
113
652256fd
LP		 114static struct resource cmt1_resources[] = {
115 DEFINE_RES_MEM(0xe6138000, 0x200),
116 DEFINE_RES_IRQ(gic_spi(65)),
6d9598e2
MD		 117};
118
652256fd
LP		 119static struct platform_device cmt1_device = {
120 .name = "sh-cmt-48",
121 .id = 1,
6d9598e2 122 .dev = {
652256fd 123 .platform_data = &cmt1_platform_data,
6d9598e2 124 },
652256fd
LP		 125 .resource = cmt1_resources,
126 .num_resources = ARRAY_SIZE(cmt1_resources),
6d9598e2
MD		 127};
128
5010f3db 129/* TMU */
3df592bc
LP		 130static struct sh_timer_config tmu0_platform_data = {
131 .channels_mask = 7,
5010f3db
MD		 132};
133
3df592bc
LP		 134static struct resource tmu0_resources[] = {
135 DEFINE_RES_MEM(0xfff60000, 0x2c),
136 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
137 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
138 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
5010f3db
MD		 139};
140
3df592bc
LP		 141static struct platform_device tmu0_device = {
142 .name = "sh-tmu",
5010f3db
MD		 143 .id = 0,
144 .dev = {
3df592bc 145 .platform_data = &tmu0_platform_data,
5010f3db 146 },
3df592bc
LP		 147 .resource = tmu0_resources,
148 .num_resources = ARRAY_SIZE(tmu0_resources),
5010f3db
MD		 149};
150
b028f94b 151static struct resource i2c0_resources[] = {
8e85524b 152 [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
b028f94b
TY		 153 [1] = {
154 .start = gic_spi(167),
155 .end = gic_spi(170),
156 .flags = IORESOURCE_IRQ,
157 },
158};
159
160static struct resource i2c1_resources[] = {
8e85524b 161 [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
b028f94b
TY		 162 [1] = {
163 .start = gic_spi(51),
164 .end = gic_spi(54),
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct resource i2c2_resources[] = {
8e85524b 170 [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
b028f94b
TY		 171 [1] = {
172 .start = gic_spi(171),
173 .end = gic_spi(174),
174 .flags = IORESOURCE_IRQ,
175 },
176};
177
178static struct resource i2c3_resources[] = {
8e85524b 179 [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
b028f94b
TY		 180 [1] = {
181 .start = gic_spi(183),
182 .end = gic_spi(186),
183 .flags = IORESOURCE_IRQ,
184 },
185};
186
187static struct resource i2c4_resources[] = {
8e85524b 188 [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
b028f94b
TY		 189 [1] = {
190 .start = gic_spi(187),
191 .end = gic_spi(190),
192 .flags = IORESOURCE_IRQ,
193 },
194};
195
b207422b
GU		 196static struct i2c_sh_mobile_platform_data i2c_platform_data = {
197 .clks_per_count = 2,
198};
199
b028f94b
TY		 200static struct platform_device i2c0_device = {
201 .name = "i2c-sh_mobile",
202 .id = 0,
203 .resource = i2c0_resources,
204 .num_resources = ARRAY_SIZE(i2c0_resources),
b207422b
GU		 205 .dev = {
206 .platform_data = &i2c_platform_data,
207 },
b028f94b
TY		 208};
209
210static struct platform_device i2c1_device = {
211 .name = "i2c-sh_mobile",
212 .id = 1,
213 .resource = i2c1_resources,
214 .num_resources = ARRAY_SIZE(i2c1_resources),
b207422b
GU		 215 .dev = {
216 .platform_data = &i2c_platform_data,
217 },
b028f94b
TY		 218};
219
220static struct platform_device i2c2_device = {
221 .name = "i2c-sh_mobile",
222 .id = 2,
223 .resource = i2c2_resources,
224 .num_resources = ARRAY_SIZE(i2c2_resources),
b207422b
GU		 225 .dev = {
226 .platform_data = &i2c_platform_data,
227 },
b028f94b
TY		 228};
229
230static struct platform_device i2c3_device = {
231 .name = "i2c-sh_mobile",
232 .id = 3,
233 .resource = i2c3_resources,
234 .num_resources = ARRAY_SIZE(i2c3_resources),
b207422b
GU		 235 .dev = {
236 .platform_data = &i2c_platform_data,
237 },
b028f94b
TY		 238};
239
240static struct platform_device i2c4_device = {
241 .name = "i2c-sh_mobile",
242 .id = 4,
243 .resource = i2c4_resources,
244 .num_resources = ARRAY_SIZE(i2c4_resources),
b207422b
GU		 245 .dev = {
246 .platform_data = &i2c_platform_data,
247 },
b028f94b
TY		 248};
249
681e1b3e
MD		 250static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
251 {
252 .slave_id = SHDMA_SLAVE_SCIF0_TX,
253 .addr = 0xe6c40020,
254 .chcr = CHCR_TX(XMIT_SZ_8BIT),
255 .mid_rid = 0x21,
256 }, {
257 .slave_id = SHDMA_SLAVE_SCIF0_RX,
258 .addr = 0xe6c40024,
259 .chcr = CHCR_RX(XMIT_SZ_8BIT),
260 .mid_rid = 0x22,
261 }, {
262 .slave_id = SHDMA_SLAVE_SCIF1_TX,
263 .addr = 0xe6c50020,
264 .chcr = CHCR_TX(XMIT_SZ_8BIT),
265 .mid_rid = 0x25,
266 }, {
267 .slave_id = SHDMA_SLAVE_SCIF1_RX,
268 .addr = 0xe6c50024,
269 .chcr = CHCR_RX(XMIT_SZ_8BIT),
270 .mid_rid = 0x26,
271 }, {
272 .slave_id = SHDMA_SLAVE_SCIF2_TX,
273 .addr = 0xe6c60020,
274 .chcr = CHCR_TX(XMIT_SZ_8BIT),
275 .mid_rid = 0x29,
276 }, {
277 .slave_id = SHDMA_SLAVE_SCIF2_RX,
278 .addr = 0xe6c60024,
279 .chcr = CHCR_RX(XMIT_SZ_8BIT),
280 .mid_rid = 0x2a,
281 }, {
282 .slave_id = SHDMA_SLAVE_SCIF3_TX,
283 .addr = 0xe6c70020,
284 .chcr = CHCR_TX(XMIT_SZ_8BIT),
285 .mid_rid = 0x2d,
286 }, {
287 .slave_id = SHDMA_SLAVE_SCIF3_RX,
288 .addr = 0xe6c70024,
289 .chcr = CHCR_RX(XMIT_SZ_8BIT),
290 .mid_rid = 0x2e,
291 }, {
292 .slave_id = SHDMA_SLAVE_SCIF4_TX,
293 .addr = 0xe6c80020,
294 .chcr = CHCR_TX(XMIT_SZ_8BIT),
295 .mid_rid = 0x39,
296 }, {
297 .slave_id = SHDMA_SLAVE_SCIF4_RX,
298 .addr = 0xe6c80024,
299 .chcr = CHCR_RX(XMIT_SZ_8BIT),
300 .mid_rid = 0x3a,
301 }, {
302 .slave_id = SHDMA_SLAVE_SCIF5_TX,
303 .addr = 0xe6cb0020,
304 .chcr = CHCR_TX(XMIT_SZ_8BIT),
305 .mid_rid = 0x35,
306 }, {
307 .slave_id = SHDMA_SLAVE_SCIF5_RX,
308 .addr = 0xe6cb0024,
309 .chcr = CHCR_RX(XMIT_SZ_8BIT),
310 .mid_rid = 0x36,
311 }, {
312 .slave_id = SHDMA_SLAVE_SCIF6_TX,
313 .addr = 0xe6cc0020,
314 .chcr = CHCR_TX(XMIT_SZ_8BIT),
315 .mid_rid = 0x1d,
316 }, {
317 .slave_id = SHDMA_SLAVE_SCIF6_RX,
318 .addr = 0xe6cc0024,
319 .chcr = CHCR_RX(XMIT_SZ_8BIT),
320 .mid_rid = 0x1e,
321 }, {
322 .slave_id = SHDMA_SLAVE_SCIF7_TX,
323 .addr = 0xe6cd0020,
324 .chcr = CHCR_TX(XMIT_SZ_8BIT),
325 .mid_rid = 0x19,
326 }, {
327 .slave_id = SHDMA_SLAVE_SCIF7_RX,
328 .addr = 0xe6cd0024,
329 .chcr = CHCR_RX(XMIT_SZ_8BIT),
330 .mid_rid = 0x1a,
331 }, {
332 .slave_id = SHDMA_SLAVE_SCIF8_TX,
333 .addr = 0xe6c30040,
334 .chcr = CHCR_TX(XMIT_SZ_8BIT),
335 .mid_rid = 0x3d,
336 }, {
337 .slave_id = SHDMA_SLAVE_SCIF8_RX,
338 .addr = 0xe6c30060,
339 .chcr = CHCR_RX(XMIT_SZ_8BIT),
340 .mid_rid = 0x3e,
341 }, {
342 .slave_id = SHDMA_SLAVE_SDHI0_TX,
343 .addr = 0xee100030,
344 .chcr = CHCR_TX(XMIT_SZ_16BIT),
345 .mid_rid = 0xc1,
346 }, {
347 .slave_id = SHDMA_SLAVE_SDHI0_RX,
348 .addr = 0xee100030,
349 .chcr = CHCR_RX(XMIT_SZ_16BIT),
350 .mid_rid = 0xc2,
351 }, {
352 .slave_id = SHDMA_SLAVE_SDHI1_TX,
353 .addr = 0xee120030,
354 .chcr = CHCR_TX(XMIT_SZ_16BIT),
355 .mid_rid = 0xc9,
356 }, {
357 .slave_id = SHDMA_SLAVE_SDHI1_RX,
358 .addr = 0xee120030,
359 .chcr = CHCR_RX(XMIT_SZ_16BIT),
360 .mid_rid = 0xca,
361 }, {
362 .slave_id = SHDMA_SLAVE_SDHI2_TX,
363 .addr = 0xee140030,
364 .chcr = CHCR_TX(XMIT_SZ_16BIT),
365 .mid_rid = 0xcd,
366 }, {
367 .slave_id = SHDMA_SLAVE_SDHI2_RX,
368 .addr = 0xee140030,
369 .chcr = CHCR_RX(XMIT_SZ_16BIT),
370 .mid_rid = 0xce,
371 }, {
372 .slave_id = SHDMA_SLAVE_MMCIF_TX,
373 .addr = 0xe6bd0034,
374 .chcr = CHCR_TX(XMIT_SZ_32BIT),
375 .mid_rid = 0xd1,
376 }, {
377 .slave_id = SHDMA_SLAVE_MMCIF_RX,
378 .addr = 0xe6bd0034,
379 .chcr = CHCR_RX(XMIT_SZ_32BIT),
380 .mid_rid = 0xd2,
381 },
382};
383
384#define DMAE_CHANNEL(_offset) \
385 { \
386 .offset = _offset - 0x20, \
387 .dmars = _offset - 0x20 + 0x40, \
388 }
389
390static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
391 DMAE_CHANNEL(0x8000),
392 DMAE_CHANNEL(0x8080),
393 DMAE_CHANNEL(0x8100),
394 DMAE_CHANNEL(0x8180),
395 DMAE_CHANNEL(0x8200),
396 DMAE_CHANNEL(0x8280),
397 DMAE_CHANNEL(0x8300),
398 DMAE_CHANNEL(0x8380),
399 DMAE_CHANNEL(0x8400),
400 DMAE_CHANNEL(0x8480),
401 DMAE_CHANNEL(0x8500),
402 DMAE_CHANNEL(0x8580),
403 DMAE_CHANNEL(0x8600),
404 DMAE_CHANNEL(0x8680),
405 DMAE_CHANNEL(0x8700),
406 DMAE_CHANNEL(0x8780),
407 DMAE_CHANNEL(0x8800),
408 DMAE_CHANNEL(0x8880),
409 DMAE_CHANNEL(0x8900),
410 DMAE_CHANNEL(0x8980),
411};
412
681e1b3e
MD		 413static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
414 .slave = sh73a0_dmae_slaves,
415 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
416 .channel = sh73a0_dmae_channels,
417 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
6088b422
KM		 418 .ts_low_shift = TS_LOW_SHIFT,
419 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
420 .ts_high_shift = TS_HI_SHIFT,
421 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
422 .ts_shift = dma_ts_shift,
423 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
681e1b3e
MD		 424 .dmaor_init = DMAOR_DME,
425};
426
427static struct resource sh73a0_dmae_resources[] = {
abbec5f4 428 DEFINE_RES_MEM(0xfe000020, 0x89e0),
681e1b3e 429 {
20052462 430 .name = "error_irq",
681e1b3e
MD		 431 .start = gic_spi(129),
432 .end = gic_spi(129),
433 .flags = IORESOURCE_IRQ,
434 },
435 {
436 /* IRQ for channels 0-19 */
437 .start = gic_spi(109),
438 .end = gic_spi(128),
439 .flags = IORESOURCE_IRQ,
440 },
441};
442
443static struct platform_device dma0_device = {
444 .name = "sh-dma-engine",
445 .id = 0,
446 .resource = sh73a0_dmae_resources,
447 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
448 .dev = {
449 .platform_data = &sh73a0_dmae_platform_data,
450 },
451};
452
832290b2
KM		 453/* MPDMAC */
454static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
455 {
456 .slave_id = SHDMA_SLAVE_FSI2A_RX,
457 .addr = 0xec230020,
458 .chcr = CHCR_RX(XMIT_SZ_32BIT),
459 .mid_rid = 0xd6, /* CHECK ME */
460 }, {
461 .slave_id = SHDMA_SLAVE_FSI2A_TX,
462 .addr = 0xec230024,
463 .chcr = CHCR_TX(XMIT_SZ_32BIT),
464 .mid_rid = 0xd5, /* CHECK ME */
465 }, {
466 .slave_id = SHDMA_SLAVE_FSI2C_RX,
467 .addr = 0xec230060,
468 .chcr = CHCR_RX(XMIT_SZ_32BIT),
469 .mid_rid = 0xda, /* CHECK ME */
470 }, {
471 .slave_id = SHDMA_SLAVE_FSI2C_TX,
472 .addr = 0xec230064,
473 .chcr = CHCR_TX(XMIT_SZ_32BIT),
474 .mid_rid = 0xd9, /* CHECK ME */
475 }, {
476 .slave_id = SHDMA_SLAVE_FSI2B_RX,
477 .addr = 0xec240020,
478 .chcr = CHCR_RX(XMIT_SZ_32BIT),
479 .mid_rid = 0x8e, /* CHECK ME */
480 }, {
481 .slave_id = SHDMA_SLAVE_FSI2B_TX,
482 .addr = 0xec240024,
483 .chcr = CHCR_RX(XMIT_SZ_32BIT),
484 .mid_rid = 0x8d, /* CHECK ME */
485 }, {
486 .slave_id = SHDMA_SLAVE_FSI2D_RX,
487 .addr = 0xec240060,
488 .chcr = CHCR_RX(XMIT_SZ_32BIT),
489 .mid_rid = 0x9a, /* CHECK ME */
490 },
491};
492
493#define MPDMA_CHANNEL(a, b, c) \
494{ \
495 .offset = a, \
496 .dmars = b, \
497 .dmars_bit = c, \
498 .chclr_offset = (0x220 - 0x20) + a \
499}
500
501static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
502 MPDMA_CHANNEL(0x00, 0, 0),
503 MPDMA_CHANNEL(0x10, 0, 8),
504 MPDMA_CHANNEL(0x20, 4, 0),
505 MPDMA_CHANNEL(0x30, 4, 8),
506 MPDMA_CHANNEL(0x50, 8, 0),
507 MPDMA_CHANNEL(0x70, 8, 8),
508};
509
510static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
511 .slave = sh73a0_mpdma_slaves,
512 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
513 .channel = sh73a0_mpdma_channels,
514 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
6088b422
KM		 515 .ts_low_shift = TS_LOW_SHIFT,
516 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
517 .ts_high_shift = TS_HI_SHIFT,
518 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
519 .ts_shift = dma_ts_shift,
520 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
832290b2
KM		 521 .dmaor_init = DMAOR_DME,
522 .chclr_present = 1,
523};
524
525/* Resource order important! */
526static struct resource sh73a0_mpdma_resources[] = {
abbec5f4
SH		 527 /* Channel registers and DMAOR */
528 DEFINE_RES_MEM(0xec618020, 0x270),
529 /* DMARSx */
530 DEFINE_RES_MEM(0xec619000, 0xc),
832290b2
KM		 531 {
532 .name = "error_irq",
533 .start = gic_spi(181),
534 .end = gic_spi(181),
535 .flags = IORESOURCE_IRQ,
536 },
537 {
538 /* IRQ for channels 0-5 */
539 .start = gic_spi(175),
540 .end = gic_spi(180),
541 .flags = IORESOURCE_IRQ,
542 },
543};
544
545static struct platform_device mpdma0_device = {
546 .name = "sh-dma-engine",
547 .id = 1,
548 .resource = sh73a0_mpdma_resources,
549 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
550 .dev = {
551 .platform_data = &sh73a0_mpdma_platform_data,
552 },
553};
554
f23f5be0
TK		 555static struct resource pmu_resources[] = {
556 [0] = {
557 .start = gic_spi(55),
558 .end = gic_spi(55),
559 .flags = IORESOURCE_IRQ,
560 },
561 [1] = {
562 .start = gic_spi(56),
563 .end = gic_spi(56),
564 .flags = IORESOURCE_IRQ,
565 },
566};
567
568static struct platform_device pmu_device = {
569 .name = "arm-pmu",
570 .id = -1,
571 .num_resources = ARRAY_SIZE(pmu_resources),
572 .resource = pmu_resources,
573};
574
9a27dee7
HE		 575/* an IPMMU module for ICB */
576static struct resource ipmmu_resources[] = {
6244cd73 577 DEFINE_RES_MEM(0xfe951000, 0x100),
9a27dee7
HE		 578};
579
580static const char * const ipmmu_dev_names[] = {
581 "sh_mobile_lcdc_fb.0",
582};
583
584static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
585 .dev_names = ipmmu_dev_names,
586 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
587};
588
589static struct platform_device ipmmu_device = {
590 .name = "ipmmu",
591 .id = -1,
592 .dev = {
593 .platform_data = &ipmmu_platform_data,
594 },
595 .resource = ipmmu_resources,
596 .num_resources = ARRAY_SIZE(ipmmu_resources),
597};
598
1461f8b6 599static struct renesas_intc_irqpin_config irqpin0_platform_data = {
341eb546
MD		 600 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
601};
602
603static struct resource irqpin0_resources[] = {
604 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
605 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
606 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
607 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
608 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
609 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
610 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
611 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
612 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
613 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
614 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
615 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
616 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
617};
618
619static struct platform_device irqpin0_device = {
620 .name = "renesas_intc_irqpin",
621 .id = 0,
622 .resource = irqpin0_resources,
623 .num_resources = ARRAY_SIZE(irqpin0_resources),
624 .dev = {
625 .platform_data = &irqpin0_platform_data,
626 },
627};
628
1461f8b6 629static struct renesas_intc_irqpin_config irqpin1_platform_data = {
341eb546
MD		 630 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
631 .control_parent = true, /* Disable spurious IRQ10 */
632};
633
634static struct resource irqpin1_resources[] = {
635 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
636 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
637 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
638 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
639 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
640 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
641 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
642 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
643 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
644 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
645 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
646 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
647 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
648};
649
650static struct platform_device irqpin1_device = {
651 .name = "renesas_intc_irqpin",
652 .id = 1,
653 .resource = irqpin1_resources,
654 .num_resources = ARRAY_SIZE(irqpin1_resources),
655 .dev = {
656 .platform_data = &irqpin1_platform_data,
657 },
658};
659
1461f8b6 660static struct renesas_intc_irqpin_config irqpin2_platform_data = {
341eb546
MD		 661 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
662};
663
664static struct resource irqpin2_resources[] = {
665 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
666 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
667 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
668 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
669 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
670 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
671 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
672 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
673 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
674 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
675 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
676 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
677 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
678};
679
680static struct platform_device irqpin2_device = {
681 .name = "renesas_intc_irqpin",
682 .id = 2,
683 .resource = irqpin2_resources,
684 .num_resources = ARRAY_SIZE(irqpin2_resources),
685 .dev = {
686 .platform_data = &irqpin2_platform_data,
687 },
688};
689
1461f8b6 690static struct renesas_intc_irqpin_config irqpin3_platform_data = {
341eb546
MD		 691 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
692};
693
694static struct resource irqpin3_resources[] = {
695 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
696 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
697 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
698 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
699 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
700 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
701 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
702 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
703 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
704 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
705 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
706 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
707 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
708};
709
710static struct platform_device irqpin3_device = {
711 .name = "renesas_intc_irqpin",
712 .id = 3,
713 .resource = irqpin3_resources,
714 .num_resources = ARRAY_SIZE(irqpin3_resources),
715 .dev = {
716 .platform_data = &irqpin3_platform_data,
717 },
718};
719
700ce7c2 720static struct platform_device *sh73a0_early_devices[] __initdata = {
6d9598e2
MD		 721 &scif0_device,
722 &scif1_device,
723 &scif2_device,
724 &scif3_device,
725 &scif4_device,
726 &scif5_device,
727 &scif6_device,
728 &scif7_device,
729 &scif8_device,
3df592bc 730 &tmu0_device,
9a27dee7 731 &ipmmu_device,
48a0d1e0 732 &cmt1_device,
6d9598e2
MD		 733};
734
b028f94b
TY		 735static struct platform_device *sh73a0_late_devices[] __initdata = {
736 &i2c0_device,
737 &i2c1_device,
738 &i2c2_device,
739 &i2c3_device,
740 &i2c4_device,
681e1b3e 741 &dma0_device,
832290b2 742 &mpdma0_device,
f23f5be0 743 &pmu_device,
341eb546
MD		 744 &irqpin0_device,
745 &irqpin1_device,
746 &irqpin2_device,
747 &irqpin3_device,
b028f94b
TY		 748};
749
0a4b04dc 750#define SRCR2 IOMEM(0xe61580b0)
681e1b3e 751
6d9598e2
MD		 752void __init sh73a0_add_standard_devices(void)
753{
681e1b3e
MD		 754 /* Clear software reset bit on SY-DMAC module */
755 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
756
6d9598e2
MD		 757 platform_add_devices(sh73a0_early_devices,
758 ARRAY_SIZE(sh73a0_early_devices));
b028f94b
TY		 759 platform_add_devices(sh73a0_late_devices,
760 ARRAY_SIZE(sh73a0_late_devices));
6d9598e2
MD		 761}
762
43cb8cb7
MD		 763void __init sh73a0_init_delay(void)
764{
5df622a5 765 shmobile_init_delay();
43cb8cb7
MD		 766}
767
d6720003
KM		 768/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
769void __init __weak sh73a0_register_twd(void) { }
770
6bb27d73 771void __init sh73a0_earlytimer_init(void)
3be26fdb 772{
43cb8cb7 773 sh73a0_init_delay();
3be26fdb
MD		 774 sh73a0_clock_init();
775 shmobile_earlytimer_init();
d6720003 776 sh73a0_register_twd();
3be26fdb
MD		 777}
778
6d9598e2
MD		 779void __init sh73a0_add_early_devices(void)
780{
781 early_platform_add_devices(sh73a0_early_devices,
782 ARRAY_SIZE(sh73a0_early_devices));
50e15c34
MD		 783
784 /* setup early console here as well */
785 shmobile_setup_console();
6d9598e2 786}
48609533
SH		 787
788#ifdef CONFIG_USE_OF
789
48609533
SH		 790void __init sh73a0_add_standard_devices_dt(void)
791{
792 /* clocks are setup late during boot in the case of DT */
793 sh73a0_clock_init();
794
ea31597f 795 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
48609533
SH		 796}
797
798static const char *sh73a0_boards_compat_dt[] __initdata = {
799 "renesas,sh73a0",
800 NULL,
801};
802
803DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
f9989507 804 .smp = smp_ops(sh73a0_smp_ops),
48609533 805 .map_io = sh73a0_map_io,
3b00f934 806 .init_early = sh73a0_init_delay,
48609533 807 .init_machine = sh73a0_add_standard_devices_dt,
e604d809 808 .init_late = shmobile_init_late,
48609533
SH		 809 .dt_compat = sh73a0_boards_compat_dt,
810MACHINE_END
811#endif /* CONFIG_USE_OF */
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