projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 9c4566a1 DN |
1 | /* |
| 2 | * Copyright 2012 Pavel Machek <pavel@denx.de> | |
| 3 | * Copyright (C) 2012 Altera Corporation | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License as published by | |
| 7 | * the Free Software Foundation; either version 2 of the License, or | |
| 8 | * (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program; if not, write to the Free Software | |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | */ | |
| 19 | ||
| 20 | #ifndef __MACH_CORE_H | |
| 21 | #define __MACH_CORE_H | |
| 22 | ||
| 5c04b57f | 23 | #define SOCFPGA_RSTMGR_CTRL 0x04 |
| d686ce42 | 24 | #define SOCFPGA_RSTMGR_MODMPURST 0x10 |
| 5c04b57f DN |
25 | #define SOCFPGA_RSTMGR_MODPERRST 0x14 |
| 26 | #define SOCFPGA_RSTMGR_BRGMODRST 0x1c | |
| 27 | ||
| 28 | /* System Manager bits */ | |
| 29 | #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ | |
| 30 | #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ | |
| 31 | ||
| d686ce42 AT |
32 | #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ |
| 33 | ||
| 9c4566a1 DN |
34 | extern void __iomem *socfpga_scu_base_addr; |
| 35 | ||
| 36 | extern void socfpga_init_clocks(void); | |
| 37 | extern void socfpga_sysmgr_init(void); | |
| 38 | ||
| 5c04b57f DN |
39 | extern void __iomem *sys_manager_base_addr; |
| 40 | extern void __iomem *rst_manager_base_addr; | |
| 41 | ||
| 9c4566a1 DN |
42 | extern struct smp_operations socfpga_smp_ops; |
| 43 | extern char secondary_trampoline, secondary_trampoline_end; | |
| 44 | ||
| 3a4356c0 | 45 | extern unsigned long socfpga_cpu1start_addr; |
| d6dd735f | 46 | |
| de04261d | 47 | #define SOCFPGA_SCU_VIRT_BASE 0xfee00000 |
| 9c4566a1 DN |
48 | |
| 49 | #endif |