[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-spear / spear320.c

/*
 * arch/arm/mach-spear3xx/spear320.c
 *
 * SPEAr320 machine source file
 *
 * Copyright (C) 2009-2012 ST Microelectronics
 * Viresh Kumar <viresh.linux@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#define pr_fmt(fmt) "SPEAr320: " fmt

#include <linux/amba/pl022.h>
#include <linux/amba/pl08x.h>
#include <linux/amba/serial.h>
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "generic.h"
#include <mach/spear.h>

#define SPEAR320_UART1_BASE		UL(0xA3000000)
#define SPEAR320_UART2_BASE		UL(0xA4000000)
#define SPEAR320_SSP0_BASE		UL(0xA5000000)
#define SPEAR320_SSP1_BASE		UL(0xA6000000)

/* DMAC platform data's slave info */
struct pl08x_channel_data spear320_dma_info[] = {
	{
		.bus_id = "uart0_rx",
		.min_signal = 2,
		.max_signal = 2,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "uart0_tx",
		.min_signal = 3,
		.max_signal = 3,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "ssp0_rx",
		.min_signal = 8,
		.max_signal = 8,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "ssp0_tx",
		.min_signal = 9,
		.max_signal = 9,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "i2c0_rx",
		.min_signal = 10,
		.max_signal = 10,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "i2c0_tx",
		.min_signal = 11,
		.max_signal = 11,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "irda",
		.min_signal = 12,
		.max_signal = 12,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "adc",
		.min_signal = 13,
		.max_signal = 13,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "to_jpeg",
		.min_signal = 14,
		.max_signal = 14,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "from_jpeg",
		.min_signal = 15,
		.max_signal = 15,
		.muxval = 0,
		.periph_buses = PL08X_AHB1,
	}, {
		.bus_id = "ssp1_rx",
		.min_signal = 0,
		.max_signal = 0,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "ssp1_tx",
		.min_signal = 1,
		.max_signal = 1,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "ssp2_rx",
		.min_signal = 2,
		.max_signal = 2,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "ssp2_tx",
		.min_signal = 3,
		.max_signal = 3,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "uart1_rx",
		.min_signal = 4,
		.max_signal = 4,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "uart1_tx",
		.min_signal = 5,
		.max_signal = 5,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "uart2_rx",
		.min_signal = 6,
		.max_signal = 6,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "uart2_tx",
		.min_signal = 7,
		.max_signal = 7,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "i2c1_rx",
		.min_signal = 8,
		.max_signal = 8,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "i2c1_tx",
		.min_signal = 9,
		.max_signal = 9,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "i2c2_rx",
		.min_signal = 10,
		.max_signal = 10,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "i2c2_tx",
		.min_signal = 11,
		.max_signal = 11,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "i2s_rx",
		.min_signal = 12,
		.max_signal = 12,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "i2s_tx",
		.min_signal = 13,
		.max_signal = 13,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "rs485_rx",
		.min_signal = 14,
		.max_signal = 14,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	}, {
		.bus_id = "rs485_tx",
		.min_signal = 15,
		.max_signal = 15,
		.muxval = 1,
		.periph_buses = PL08X_AHB2,
	},
};

static struct pl022_ssp_controller spear320_ssp_data[] = {
	{
		.bus_id = 1,
		.enable_dma = 1,
		.dma_filter = pl08x_filter_id,
		.dma_tx_param = "ssp1_tx",
		.dma_rx_param = "ssp1_rx",
		.num_chipselect = 2,
	}, {
		.bus_id = 2,
		.enable_dma = 1,
		.dma_filter = pl08x_filter_id,
		.dma_tx_param = "ssp2_tx",
		.dma_rx_param = "ssp2_rx",
		.num_chipselect = 2,
	}
};

static struct amba_pl011_data spear320_uart_data[] = {
	{
		.dma_filter = pl08x_filter_id,
		.dma_tx_param = "uart1_tx",
		.dma_rx_param = "uart1_rx",
	}, {
		.dma_filter = pl08x_filter_id,
		.dma_tx_param = "uart2_tx",
		.dma_rx_param = "uart2_rx",
	},
};

/* Add SPEAr310 auxdata to pass platform data */
static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
			&pl022_plat_data),
	OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
			&pl080_plat_data),
	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
			&spear320_ssp_data[0]),
	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
			&spear320_ssp_data[1]),
	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
			&spear320_uart_data[0]),
	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
			&spear320_uart_data[1]),
	{}
};

static void __init spear320_dt_init(void)
{
	pl080_plat_data.slave_channels = spear320_dma_info;
	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);

	of_platform_populate(NULL, of_default_bus_match_table,
			spear320_auxdata_lookup, NULL);
}

static const char * const spear320_dt_board_compat[] = {
	"st,spear320",
	"st,spear320-evb",
	"st,spear320-hmi",
	NULL,
};

struct map_desc spear320_io_desc[] __initdata = {
	{
		.virtual	= VA_SPEAR320_SOC_CONFIG_BASE,
		.pfn		= __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	},
};

static void __init spear320_map_io(void)
{
	iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
	spear3xx_map_io();
}

DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
	.map_io		=	spear320_map_io,
	.init_irq	=	irqchip_init,
	.init_time	=	spear3xx_timer_init,
	.init_machine	=	spear320_dt_init,
	.restart	=	spear_restart,
	.dt_compat	=	spear320_dt_board_compat,
MACHINE_END
Commit	Line	Data
bc4e814e VK	1	/*
	2	* arch/arm/mach-spear3xx/spear320.c
	3	*
	4	* SPEAr320 machine source file
	5	*
c5fa4fdc	6	* Copyright (C) 2009-2012 ST Microelectronics
10d8935f	7	* Viresh Kumar <viresh.linux@gmail.com>
bc4e814e VK	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
5fb00f96 VK	14	#define pr_fmt(fmt) "SPEAr320: " fmt
5fb00f96 VK	15
c5fa4fdc VK	16	#include <linux/amba/pl022.h>
	17	#include <linux/amba/pl08x.h>
	18	#include <linux/amba/serial.h>
e9c51558	19	#include <linux/irqchip.h>
c5fa4fdc	20	#include <linux/of_platform.h>
c5fa4fdc	21	#include <asm/mach/arch.h>
54475210	22	#include <asm/mach/map.h>
2b9c613c	23	#include "generic.h"
5df33a62	24	#include <mach/spear.h>
bc4e814e	25
5019f0b1 AB	26	#define SPEAR320_UART1_BASE UL(0xA3000000)
	27	#define SPEAR320_UART2_BASE UL(0xA4000000)
	28	#define SPEAR320_SSP0_BASE UL(0xA5000000)
	29	#define SPEAR320_SSP1_BASE UL(0xA6000000)
5019f0b1	30
0b7ee717 VK	31	/* DMAC platform data's slave info */
	32	struct pl08x_channel_data spear320_dma_info[] = {
	33	{
	34	.bus_id = "uart0_rx",
	35	.min_signal = 2,
	36	.max_signal = 2,
	37	.muxval = 0,
0b7ee717 VK	38	.periph_buses = PL08X_AHB1,
	39	}, {
	40	.bus_id = "uart0_tx",
	41	.min_signal = 3,
	42	.max_signal = 3,
	43	.muxval = 0,
0b7ee717 VK	44	.periph_buses = PL08X_AHB1,
	45	}, {
	46	.bus_id = "ssp0_rx",
	47	.min_signal = 8,
	48	.max_signal = 8,
	49	.muxval = 0,
0b7ee717 VK	50	.periph_buses = PL08X_AHB1,
	51	}, {
	52	.bus_id = "ssp0_tx",
	53	.min_signal = 9,
	54	.max_signal = 9,
	55	.muxval = 0,
0b7ee717 VK	56	.periph_buses = PL08X_AHB1,
	57	}, {
	58	.bus_id = "i2c0_rx",
	59	.min_signal = 10,
	60	.max_signal = 10,
	61	.muxval = 0,
0b7ee717 VK	62	.periph_buses = PL08X_AHB1,
	63	}, {
	64	.bus_id = "i2c0_tx",
	65	.min_signal = 11,
	66	.max_signal = 11,
	67	.muxval = 0,
0b7ee717 VK	68	.periph_buses = PL08X_AHB1,
	69	}, {
	70	.bus_id = "irda",
	71	.min_signal = 12,
	72	.max_signal = 12,
	73	.muxval = 0,
0b7ee717 VK	74	.periph_buses = PL08X_AHB1,
	75	}, {
	76	.bus_id = "adc",
	77	.min_signal = 13,
	78	.max_signal = 13,
	79	.muxval = 0,
0b7ee717 VK	80	.periph_buses = PL08X_AHB1,
	81	}, {
	82	.bus_id = "to_jpeg",
	83	.min_signal = 14,
	84	.max_signal = 14,
	85	.muxval = 0,
0b7ee717 VK	86	.periph_buses = PL08X_AHB1,
	87	}, {
	88	.bus_id = "from_jpeg",
	89	.min_signal = 15,
	90	.max_signal = 15,
	91	.muxval = 0,
0b7ee717 VK	92	.periph_buses = PL08X_AHB1,
	93	}, {
	94	.bus_id = "ssp1_rx",
	95	.min_signal = 0,
	96	.max_signal = 0,
	97	.muxval = 1,
0b7ee717 VK	98	.periph_buses = PL08X_AHB2,
	99	}, {
	100	.bus_id = "ssp1_tx",
	101	.min_signal = 1,
	102	.max_signal = 1,
	103	.muxval = 1,
0b7ee717 VK	104	.periph_buses = PL08X_AHB2,
	105	}, {
	106	.bus_id = "ssp2_rx",
	107	.min_signal = 2,
	108	.max_signal = 2,
	109	.muxval = 1,
0b7ee717 VK	110	.periph_buses = PL08X_AHB2,
	111	}, {
	112	.bus_id = "ssp2_tx",
	113	.min_signal = 3,
	114	.max_signal = 3,
	115	.muxval = 1,
0b7ee717 VK	116	.periph_buses = PL08X_AHB2,
	117	}, {
	118	.bus_id = "uart1_rx",
	119	.min_signal = 4,
	120	.max_signal = 4,
	121	.muxval = 1,
0b7ee717 VK	122	.periph_buses = PL08X_AHB2,
	123	}, {
	124	.bus_id = "uart1_tx",
	125	.min_signal = 5,
	126	.max_signal = 5,
	127	.muxval = 1,
0b7ee717 VK	128	.periph_buses = PL08X_AHB2,
	129	}, {
	130	.bus_id = "uart2_rx",
	131	.min_signal = 6,
	132	.max_signal = 6,
	133	.muxval = 1,
0b7ee717 VK	134	.periph_buses = PL08X_AHB2,
	135	}, {
	136	.bus_id = "uart2_tx",
	137	.min_signal = 7,
	138	.max_signal = 7,
	139	.muxval = 1,
0b7ee717 VK	140	.periph_buses = PL08X_AHB2,
	141	}, {
	142	.bus_id = "i2c1_rx",
	143	.min_signal = 8,
	144	.max_signal = 8,
	145	.muxval = 1,
0b7ee717 VK	146	.periph_buses = PL08X_AHB2,
	147	}, {
	148	.bus_id = "i2c1_tx",
	149	.min_signal = 9,
	150	.max_signal = 9,
	151	.muxval = 1,
0b7ee717 VK	152	.periph_buses = PL08X_AHB2,
	153	}, {
	154	.bus_id = "i2c2_rx",
	155	.min_signal = 10,
	156	.max_signal = 10,
	157	.muxval = 1,
0b7ee717 VK	158	.periph_buses = PL08X_AHB2,
	159	}, {
	160	.bus_id = "i2c2_tx",
	161	.min_signal = 11,
	162	.max_signal = 11,
	163	.muxval = 1,
0b7ee717 VK	164	.periph_buses = PL08X_AHB2,
	165	}, {
	166	.bus_id = "i2s_rx",
	167	.min_signal = 12,
	168	.max_signal = 12,
	169	.muxval = 1,
0b7ee717 VK	170	.periph_buses = PL08X_AHB2,
	171	}, {
	172	.bus_id = "i2s_tx",
	173	.min_signal = 13,
	174	.max_signal = 13,
	175	.muxval = 1,
0b7ee717 VK	176	.periph_buses = PL08X_AHB2,
	177	}, {
	178	.bus_id = "rs485_rx",
	179	.min_signal = 14,
	180	.max_signal = 14,
	181	.muxval = 1,
0b7ee717 VK	182	.periph_buses = PL08X_AHB2,
	183	}, {
	184	.bus_id = "rs485_tx",
	185	.min_signal = 15,
	186	.max_signal = 15,
	187	.muxval = 1,
0b7ee717 VK	188	.periph_buses = PL08X_AHB2,
	189	},
	190	};
	191
c5fa4fdc VK	192	static struct pl022_ssp_controller spear320_ssp_data[] = {
	193	{
	194	.bus_id = 1,
	195	.enable_dma = 1,
	196	.dma_filter = pl08x_filter_id,
	197	.dma_tx_param = "ssp1_tx",
	198	.dma_rx_param = "ssp1_rx",
	199	.num_chipselect = 2,
	200	}, {
	201	.bus_id = 2,
	202	.enable_dma = 1,
	203	.dma_filter = pl08x_filter_id,
	204	.dma_tx_param = "ssp2_tx",
	205	.dma_rx_param = "ssp2_rx",
	206	.num_chipselect = 2,
	207	}
	208	};
	209
	210	static struct amba_pl011_data spear320_uart_data[] = {
	211	{
	212	.dma_filter = pl08x_filter_id,
	213	.dma_tx_param = "uart1_tx",
	214	.dma_rx_param = "uart1_rx",
	215	}, {
	216	.dma_filter = pl08x_filter_id,
	217	.dma_tx_param = "uart2_tx",
	218	.dma_rx_param = "uart2_rx",
	219	},
	220	};
c2c07831	221
c5fa4fdc VK	222	/* Add SPEAr310 auxdata to pass platform data */
	223	static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
	224	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
	225	&pl022_plat_data),
d42799b7	226	OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
0b7ee717	227	&pl080_plat_data),
c5fa4fdc VK	228	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
	229	&spear320_ssp_data[0]),
	230	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
	231	&spear320_ssp_data[1]),
	232	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
	233	&spear320_uart_data[0]),
	234	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
	235	&spear320_uart_data[1]),
	236	{}
	237	};
	238
	239	static void __init spear320_dt_init(void)
bc4e814e	240	{
0b7ee717 VK	241	pl080_plat_data.slave_channels = spear320_dma_info;
0b7ee717 VK	242	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
4c18e77f	243
c5fa4fdc VK	244	of_platform_populate(NULL, of_default_bus_match_table,
c5fa4fdc VK	245	spear320_auxdata_lookup, NULL);
70f4c0bf	246	}
70f4c0bf	247
c5fa4fdc VK	248	static const char * const spear320_dt_board_compat[] = {
	249	"st,spear320",
	250	"st,spear320-evb",
e2eb6918	251	"st,spear320-hmi",
c5fa4fdc VK	252	NULL,
c5fa4fdc VK	253	};
6618c3ad	254
66a2886d AB	255	struct map_desc spear320_io_desc[] __initdata = {
	256	{
	257	.virtual = VA_SPEAR320_SOC_CONFIG_BASE,
	258	.pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
	259	.length = SZ_16M,
	260	.type = MT_DEVICE
	261	},
	262	};
	263
c5fa4fdc VK	264	static void __init spear320_map_io(void)
c5fa4fdc VK	265	{
66a2886d	266	iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
c5fa4fdc	267	spear3xx_map_io();
70f4c0bf	268	}
c5fa4fdc VK	269
	270	DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
	271	.map_io = spear320_map_io,
e9c51558	272	.init_irq = irqchip_init,
6bb27d73	273	.init_time = spear3xx_timer_init,
c5fa4fdc VK	274	.init_machine = spear320_dt_init,
	275	.restart = spear_restart,
	276	.dt_compat = spear320_dt_board_compat,
	277	MACHINE_END