[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-spear / time.c

/*
 * arch/arm/plat-spear/time.c
 *
 * Copyright (C) 2010 ST Microelectronics
 * Shiraz Hashim<shiraz.linux.kernel@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/time.h>
#include <linux/irq.h>
#include <asm/mach/time.h>
#include "generic.h"

/*
 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
 * they share same functional clock. Any change in one's functional clock will
 * also affect other timer.
 */

#define CLKEVT	0	/* gpt0, channel0 as clockevent */
#define CLKSRC	1	/* gpt0, channel1 as clocksource */

/* Register offsets, x is channel number */
#define CR(x)		((x) * 0x80 + 0x80)
#define IR(x)		((x) * 0x80 + 0x84)
#define LOAD(x)		((x) * 0x80 + 0x88)
#define COUNT(x)	((x) * 0x80 + 0x8C)

/* Reg bit definitions */
#define CTRL_INT_ENABLE		0x0100
#define CTRL_ENABLE		0x0020
#define CTRL_ONE_SHOT		0x0010

#define CTRL_PRESCALER1		0x0
#define CTRL_PRESCALER2		0x1
#define CTRL_PRESCALER4		0x2
#define CTRL_PRESCALER8		0x3
#define CTRL_PRESCALER16	0x4
#define CTRL_PRESCALER32	0x5
#define CTRL_PRESCALER64	0x6
#define CTRL_PRESCALER128	0x7
#define CTRL_PRESCALER256	0x8

#define INT_STATUS		0x1

/*
 * Minimum clocksource/clockevent timer range in seconds
 */
#define SPEAR_MIN_RANGE 4

static __iomem void *gpt_base;
static struct clk *gpt_clk;

static int clockevent_next_event(unsigned long evt,
				 struct clock_event_device *clk_event_dev);

static void __init spear_clocksource_init(void)
{
	u32 tick_rate;
	u16 val;

	/* program the prescaler (/256)*/
	writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));

	/* find out actual clock driving Timer */
	tick_rate = clk_get_rate(gpt_clk);
	tick_rate >>= CTRL_PRESCALER256;

	writew(0xFFFF, gpt_base + LOAD(CLKSRC));

	val = readw(gpt_base + CR(CLKSRC));
	val &= ~CTRL_ONE_SHOT;	/* autoreload mode */
	val |= CTRL_ENABLE ;
	writew(val, gpt_base + CR(CLKSRC));

	/* register the clocksource */
	clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
		200, 16, clocksource_mmio_readw_up);
}

static inline void timer_shutdown(struct clock_event_device *evt)
{
	u16 val = readw(gpt_base + CR(CLKEVT));

	/* stop the timer */
	val &= ~CTRL_ENABLE;
	writew(val, gpt_base + CR(CLKEVT));
}

static int spear_shutdown(struct clock_event_device *evt)
{
	timer_shutdown(evt);

	return 0;
}

static int spear_set_oneshot(struct clock_event_device *evt)
{
	u16 val;

	/* stop the timer */
	timer_shutdown(evt);

	val = readw(gpt_base + CR(CLKEVT));
	val |= CTRL_ONE_SHOT;
	writew(val, gpt_base + CR(CLKEVT));

	return 0;
}

static int spear_set_periodic(struct clock_event_device *evt)
{
	u32 period;
	u16 val;

	/* stop the timer */
	timer_shutdown(evt);

	period = clk_get_rate(gpt_clk) / HZ;
	period >>= CTRL_PRESCALER16;
	writew(period, gpt_base + LOAD(CLKEVT));

	val = readw(gpt_base + CR(CLKEVT));
	val &= ~CTRL_ONE_SHOT;
	val |= CTRL_ENABLE | CTRL_INT_ENABLE;
	writew(val, gpt_base + CR(CLKEVT));

	return 0;
}

static struct clock_event_device clkevt = {
	.name = "tmr0",
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown = spear_shutdown,
	.set_state_periodic = spear_set_periodic,
	.set_state_oneshot = spear_set_oneshot,
	.tick_resume = spear_shutdown,
	.set_next_event = clockevent_next_event,
	.shift = 0,	/* to be computed */
};

static int clockevent_next_event(unsigned long cycles,
				 struct clock_event_device *clk_event_dev)
{
	u16 val = readw(gpt_base + CR(CLKEVT));

	if (val & CTRL_ENABLE)
		writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));

	writew(cycles, gpt_base + LOAD(CLKEVT));

	val |= CTRL_ENABLE | CTRL_INT_ENABLE;
	writew(val, gpt_base + CR(CLKEVT));

	return 0;
}

static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clkevt;

	writew(INT_STATUS, gpt_base + IR(CLKEVT));

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction spear_timer_irq = {
	.name = "timer",
	.flags = IRQF_TIMER,
	.handler = spear_timer_interrupt
};

static void __init spear_clockevent_init(int irq)
{
	u32 tick_rate;

	/* program the prescaler */
	writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));

	tick_rate = clk_get_rate(gpt_clk);
	tick_rate >>= CTRL_PRESCALER16;

	clkevt.cpumask = cpumask_of(0);

	clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);

	setup_irq(irq, &spear_timer_irq);
}

static const struct of_device_id timer_of_match[] __initconst = {
	{ .compatible = "st,spear-timer", },
	{ },
};

void __init spear_setup_of_timer(void)
{
	struct device_node *np;
	int irq, ret;

	np = of_find_matching_node(NULL, timer_of_match);
	if (!np) {
		pr_err("%s: No timer passed via DT\n", __func__);
		return;
	}

	irq = irq_of_parse_and_map(np, 0);
	if (!irq) {
		pr_err("%s: No irq passed for timer via DT\n", __func__);
		return;
	}

	gpt_base = of_iomap(np, 0);
	if (!gpt_base) {
		pr_err("%s: of iomap failed\n", __func__);
		return;
	}

	gpt_clk = clk_get_sys("gpt0", NULL);
	if (IS_ERR(gpt_clk)) {
		pr_err("%s:couldn't get clk for gpt\n", __func__);
		goto err_iomap;
	}

	ret = clk_prepare_enable(gpt_clk);
	if (ret < 0) {
		pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
		goto err_prepare_enable_clk;
	}

	spear_clockevent_init(irq);
	spear_clocksource_init();

	return;

err_prepare_enable_clk:
	clk_put(gpt_clk);
err_iomap:
	iounmap(gpt_base);
}
Commit	Line	Data
986435e3 VK	1	/*
	2	* arch/arm/plat-spear/time.c
	3	*
5c881d9a	4	* Copyright (C) 2010 ST Microelectronics
9cc23682	5	* Shiraz Hashim<shiraz.linux.kernel@gmail.com>
986435e3 VK	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/clockchips.h>
	14	#include <linux/clocksource.h>
	15	#include <linux/err.h>
	16	#include <linux/init.h>
	17	#include <linux/interrupt.h>
5019f0b1	18	#include <linux/ioport.h>
986435e3 VK	19	#include <linux/io.h>
986435e3 VK	20	#include <linux/kernel.h>
30551c01 VK	21	#include <linux/of_irq.h>
30551c01 VK	22	#include <linux/of_address.h>
986435e3 VK	23	#include <linux/time.h>
	24	#include <linux/irq.h>
	25	#include <asm/mach/time.h>
2b9c613c	26	#include "generic.h"
986435e3 VK	27
	28	/*
	29	* We would use TIMER0 and TIMER1 as clockevent and clocksource.
	30	* Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
	31	* they share same functional clock. Any change in one's functional clock will
	32	* also affect other timer.
	33	*/
	34
	35	#define CLKEVT 0 /* gpt0, channel0 as clockevent */
	36	#define CLKSRC 1 /* gpt0, channel1 as clocksource */
	37
	38	/* Register offsets, x is channel number */
	39	#define CR(x) ((x) * 0x80 + 0x80)
	40	#define IR(x) ((x) * 0x80 + 0x84)
	41	#define LOAD(x) ((x) * 0x80 + 0x88)
	42	#define COUNT(x) ((x) * 0x80 + 0x8C)
	43
	44	/* Reg bit definitions */
	45	#define CTRL_INT_ENABLE 0x0100
	46	#define CTRL_ENABLE 0x0020
	47	#define CTRL_ONE_SHOT 0x0010
	48
	49	#define CTRL_PRESCALER1 0x0
	50	#define CTRL_PRESCALER2 0x1
	51	#define CTRL_PRESCALER4 0x2
	52	#define CTRL_PRESCALER8 0x3
	53	#define CTRL_PRESCALER16 0x4
	54	#define CTRL_PRESCALER32 0x5
	55	#define CTRL_PRESCALER64 0x6
	56	#define CTRL_PRESCALER128 0x7
	57	#define CTRL_PRESCALER256 0x8
	58
	59	#define INT_STATUS 0x1
	60
4bd48940 LW	61	/*
	62	* Minimum clocksource/clockevent timer range in seconds
	63	*/
	64	#define SPEAR_MIN_RANGE 4
	65
986435e3 VK	66	static __iomem void *gpt_base;
	67	static struct clk *gpt_clk;
	68
986435e3 VK	69	static int clockevent_next_event(unsigned long evt,
	70	struct clock_event_device *clk_event_dev);
	71
1be5f692	72	static void __init spear_clocksource_init(void)
986435e3 VK	73	{
	74	u32 tick_rate;
	75	u16 val;
	76
	77	/* program the prescaler (/256)*/
	78	writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
	79
	80	/* find out actual clock driving Timer */
	81	tick_rate = clk_get_rate(gpt_clk);
	82	tick_rate >>= CTRL_PRESCALER256;
	83
	84	writew(0xFFFF, gpt_base + LOAD(CLKSRC));
	85
	86	val = readw(gpt_base + CR(CLKSRC));
	87	val &= ~CTRL_ONE_SHOT; /* autoreload mode */
	88	val \|= CTRL_ENABLE ;
	89	writew(val, gpt_base + CR(CLKSRC));
	90
986435e3	91	/* register the clocksource */
d6e15d78 RK	92	clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
d6e15d78 RK	93	200, 16, clocksource_mmio_readw_up);
986435e3 VK	94	}
986435e3 VK	95
7639c0b8 VK	96	static inline void timer_shutdown(struct clock_event_device *evt)
	97	{
	98	u16 val = readw(gpt_base + CR(CLKEVT));
986435e3	99
7639c0b8 VK	100	/* stop the timer */
	101	val &= ~CTRL_ENABLE;
	102	writew(val, gpt_base + CR(CLKEVT));
	103	}
	104
	105	static int spear_shutdown(struct clock_event_device *evt)
	106	{
	107	timer_shutdown(evt);
	108
	109	return 0;
	110	}
	111
	112	static int spear_set_oneshot(struct clock_event_device *evt)
	113	{
	114	u16 val;
	115
	116	/* stop the timer */
	117	timer_shutdown(evt);
	118
	119	val = readw(gpt_base + CR(CLKEVT));
	120	val \|= CTRL_ONE_SHOT;
	121	writew(val, gpt_base + CR(CLKEVT));
	122
	123	return 0;
	124	}
	125
	126	static int spear_set_periodic(struct clock_event_device *evt)
986435e3 VK	127	{
	128	u32 period;
	129	u16 val;
	130
	131	/* stop the timer */
7639c0b8 VK	132	timer_shutdown(evt);
	133
	134	period = clk_get_rate(gpt_clk) / HZ;
	135	period >>= CTRL_PRESCALER16;
	136	writew(period, gpt_base + LOAD(CLKEVT));
	137
986435e3	138	val = readw(gpt_base + CR(CLKEVT));
7639c0b8 VK	139	val &= ~CTRL_ONE_SHOT;
7639c0b8 VK	140	val \|= CTRL_ENABLE \| CTRL_INT_ENABLE;
986435e3 VK	141	writew(val, gpt_base + CR(CLKEVT));
986435e3 VK	142
7639c0b8	143	return 0;
986435e3 VK	144	}
986435e3 VK	145
7639c0b8 VK	146	static struct clock_event_device clkevt = {
	147	.name = "tmr0",
	148	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	149	.set_state_shutdown = spear_shutdown,
	150	.set_state_periodic = spear_set_periodic,
	151	.set_state_oneshot = spear_set_oneshot,
	152	.tick_resume = spear_shutdown,
	153	.set_next_event = clockevent_next_event,
	154	.shift = 0, /* to be computed */
	155	};
	156
986435e3 VK	157	static int clockevent_next_event(unsigned long cycles,
	158	struct clock_event_device *clk_event_dev)
	159	{
12021372 GC	160	u16 val = readw(gpt_base + CR(CLKEVT));
	161
	162	if (val & CTRL_ENABLE)
	163	writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
986435e3 VK	164
	165	writew(cycles, gpt_base + LOAD(CLKEVT));
	166
986435e3 VK	167	val \|= CTRL_ENABLE \| CTRL_INT_ENABLE;
	168	writew(val, gpt_base + CR(CLKEVT));
	169
	170	return 0;
	171	}
	172
	173	static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
	174	{
	175	struct clock_event_device *evt = &clkevt;
	176
	177	writew(INT_STATUS, gpt_base + IR(CLKEVT));
	178
	179	evt->event_handler(evt);
	180
	181	return IRQ_HANDLED;
	182	}
	183
	184	static struct irqaction spear_timer_irq = {
	185	.name = "timer",
49710fa4	186	.flags = IRQF_TIMER,
986435e3 VK	187	.handler = spear_timer_interrupt
	188	};
	189
5019f0b1	190	static void __init spear_clockevent_init(int irq)
986435e3 VK	191	{
	192	u32 tick_rate;
	193
	194	/* program the prescaler */
	195	writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
	196
	197	tick_rate = clk_get_rate(gpt_clk);
	198	tick_rate >>= CTRL_PRESCALER16;
	199
986435e3 VK	200	clkevt.cpumask = cpumask_of(0);
986435e3 VK	201
838a2ae8	202	clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
986435e3	203
5019f0b1	204	setup_irq(irq, &spear_timer_irq);
986435e3 VK	205	}
986435e3 VK	206
0527873b	207	static const struct of_device_id timer_of_match[] __initconst = {
30551c01 VK	208	{ .compatible = "st,spear-timer", },
	209	{ },
	210	};
	211
	212	void __init spear_setup_of_timer(void)
986435e3	213	{
30551c01 VK	214	struct device_node *np;
	215	int irq, ret;
	216
	217	np = of_find_matching_node(NULL, timer_of_match);
	218	if (!np) {
	219	pr_err("%s: No timer passed via DT\n", __func__);
	220	return;
	221	}
986435e3	222
30551c01 VK	223	irq = irq_of_parse_and_map(np, 0);
	224	if (!irq) {
	225	pr_err("%s: No irq passed for timer via DT\n", __func__);
986435e3 VK	226	return;
	227	}
	228
30551c01	229	gpt_base = of_iomap(np, 0);
986435e3	230	if (!gpt_base) {
30551c01 VK	231	pr_err("%s: of iomap failed\n", __func__);
30551c01 VK	232	return;
986435e3 VK	233	}
	234
	235	gpt_clk = clk_get_sys("gpt0", NULL);
ce340961	236	if (IS_ERR(gpt_clk)) {
986435e3 VK	237	pr_err("%s:couldn't get clk for gpt\n", __func__);
	238	goto err_iomap;
	239	}
	240
f8abc080	241	ret = clk_prepare_enable(gpt_clk);
5c881d9a	242	if (ret < 0) {
f8abc080 VK	243	pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
f8abc080 VK	244	goto err_prepare_enable_clk;
986435e3 VK	245	}
986435e3 VK	246
5019f0b1	247	spear_clockevent_init(irq);
986435e3 VK	248	spear_clocksource_init();
	249
	250	return;
	251
f8abc080	252	err_prepare_enable_clk:
5c881d9a	253	clk_put(gpt_clk);
986435e3 VK	254	err_iomap:
986435e3 VK	255	iounmap(gpt_base);
986435e3	256	}