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bc4e814e VK |
1 | /* |
2 | * arch/arm/mach-spear3xx/spear310.c | |
3 | * | |
4 | * SPEAr310 machine source file | |
5 | * | |
6 | * Copyright (C) 2009 ST Microelectronics | |
7 | * Viresh Kumar<viresh.kumar@st.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
5fb00f96 VK |
14 | #define pr_fmt(fmt) "SPEAr310: " fmt |
15 | ||
bc4e814e VK |
16 | #include <linux/ptrace.h> |
17 | #include <asm/irq.h> | |
410782be | 18 | #include <plat/shirq.h> |
bc4e814e | 19 | #include <mach/generic.h> |
02aa06bc | 20 | #include <mach/hardware.h> |
bc4e814e | 21 | |
70f4c0bf VK |
22 | /* pad multiplexing support */ |
23 | /* muxing registers */ | |
24 | #define PAD_MUX_CONFIG_REG 0x08 | |
25 | ||
26 | /* devices */ | |
6618c3ad | 27 | static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { |
70f4c0bf VK |
28 | { |
29 | .ids = 0x00, | |
30 | .mask = PMX_TIMER_3_4_MASK, | |
31 | }, | |
32 | }; | |
33 | ||
6618c3ad | 34 | struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { |
70f4c0bf VK |
35 | .name = "emi_cs_0_1_4_5", |
36 | .modes = pmx_emi_cs_0_1_4_5_modes, | |
37 | .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), | |
38 | .enb_on_reset = 1, | |
39 | }; | |
40 | ||
6618c3ad | 41 | static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { |
70f4c0bf VK |
42 | { |
43 | .ids = 0x00, | |
44 | .mask = PMX_TIMER_1_2_MASK, | |
45 | }, | |
46 | }; | |
47 | ||
6618c3ad | 48 | struct pmx_dev spear310_pmx_emi_cs_2_3 = { |
70f4c0bf VK |
49 | .name = "emi_cs_2_3", |
50 | .modes = pmx_emi_cs_2_3_modes, | |
51 | .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), | |
52 | .enb_on_reset = 1, | |
53 | }; | |
54 | ||
6618c3ad | 55 | static struct pmx_dev_mode pmx_uart1_modes[] = { |
70f4c0bf VK |
56 | { |
57 | .ids = 0x00, | |
58 | .mask = PMX_FIRDA_MASK, | |
59 | }, | |
60 | }; | |
61 | ||
6618c3ad | 62 | struct pmx_dev spear310_pmx_uart1 = { |
70f4c0bf VK |
63 | .name = "uart1", |
64 | .modes = pmx_uart1_modes, | |
65 | .mode_count = ARRAY_SIZE(pmx_uart1_modes), | |
66 | .enb_on_reset = 1, | |
67 | }; | |
68 | ||
6618c3ad | 69 | static struct pmx_dev_mode pmx_uart2_modes[] = { |
70f4c0bf VK |
70 | { |
71 | .ids = 0x00, | |
72 | .mask = PMX_TIMER_1_2_MASK, | |
73 | }, | |
74 | }; | |
75 | ||
6618c3ad | 76 | struct pmx_dev spear310_pmx_uart2 = { |
70f4c0bf VK |
77 | .name = "uart2", |
78 | .modes = pmx_uart2_modes, | |
79 | .mode_count = ARRAY_SIZE(pmx_uart2_modes), | |
80 | .enb_on_reset = 1, | |
81 | }; | |
82 | ||
6618c3ad | 83 | static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { |
70f4c0bf VK |
84 | { |
85 | .ids = 0x00, | |
86 | .mask = PMX_UART0_MODEM_MASK, | |
87 | }, | |
88 | }; | |
89 | ||
6618c3ad | 90 | struct pmx_dev spear310_pmx_uart3_4_5 = { |
70f4c0bf VK |
91 | .name = "uart3_4_5", |
92 | .modes = pmx_uart3_4_5_modes, | |
93 | .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), | |
94 | .enb_on_reset = 1, | |
95 | }; | |
96 | ||
6618c3ad | 97 | static struct pmx_dev_mode pmx_fsmc_modes[] = { |
70f4c0bf VK |
98 | { |
99 | .ids = 0x00, | |
100 | .mask = PMX_SSP_CS_MASK, | |
101 | }, | |
102 | }; | |
103 | ||
6618c3ad | 104 | struct pmx_dev spear310_pmx_fsmc = { |
70f4c0bf VK |
105 | .name = "fsmc", |
106 | .modes = pmx_fsmc_modes, | |
107 | .mode_count = ARRAY_SIZE(pmx_fsmc_modes), | |
108 | .enb_on_reset = 1, | |
109 | }; | |
110 | ||
6618c3ad | 111 | static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { |
70f4c0bf VK |
112 | { |
113 | .ids = 0x00, | |
114 | .mask = PMX_MII_MASK, | |
115 | }, | |
116 | }; | |
117 | ||
6618c3ad | 118 | struct pmx_dev spear310_pmx_rs485_0_1 = { |
70f4c0bf VK |
119 | .name = "rs485_0_1", |
120 | .modes = pmx_rs485_0_1_modes, | |
121 | .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), | |
122 | .enb_on_reset = 1, | |
123 | }; | |
124 | ||
6618c3ad | 125 | static struct pmx_dev_mode pmx_tdm0_modes[] = { |
70f4c0bf VK |
126 | { |
127 | .ids = 0x00, | |
128 | .mask = PMX_MII_MASK, | |
129 | }, | |
130 | }; | |
131 | ||
6618c3ad | 132 | struct pmx_dev spear310_pmx_tdm0 = { |
70f4c0bf VK |
133 | .name = "tdm0", |
134 | .modes = pmx_tdm0_modes, | |
135 | .mode_count = ARRAY_SIZE(pmx_tdm0_modes), | |
136 | .enb_on_reset = 1, | |
137 | }; | |
138 | ||
139 | /* pmx driver structure */ | |
6618c3ad | 140 | static struct pmx_driver pmx_driver = { |
70f4c0bf VK |
141 | .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, |
142 | }; | |
143 | ||
4c18e77f | 144 | /* spear3xx shared irq */ |
f6558bf9 | 145 | static struct shirq_dev_config shirq_ras1_config[] = { |
4c18e77f | 146 | { |
61e72bca RM |
147 | .virq = SPEAR310_VIRQ_SMII0, |
148 | .status_mask = SPEAR310_SMII0_IRQ_MASK, | |
4c18e77f | 149 | }, { |
61e72bca RM |
150 | .virq = SPEAR310_VIRQ_SMII1, |
151 | .status_mask = SPEAR310_SMII1_IRQ_MASK, | |
4c18e77f | 152 | }, { |
61e72bca RM |
153 | .virq = SPEAR310_VIRQ_SMII2, |
154 | .status_mask = SPEAR310_SMII2_IRQ_MASK, | |
4c18e77f | 155 | }, { |
61e72bca RM |
156 | .virq = SPEAR310_VIRQ_SMII3, |
157 | .status_mask = SPEAR310_SMII3_IRQ_MASK, | |
4c18e77f | 158 | }, { |
61e72bca RM |
159 | .virq = SPEAR310_VIRQ_WAKEUP_SMII0, |
160 | .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK, | |
4c18e77f | 161 | }, { |
61e72bca RM |
162 | .virq = SPEAR310_VIRQ_WAKEUP_SMII1, |
163 | .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK, | |
4c18e77f | 164 | }, { |
61e72bca RM |
165 | .virq = SPEAR310_VIRQ_WAKEUP_SMII2, |
166 | .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK, | |
4c18e77f | 167 | }, { |
61e72bca RM |
168 | .virq = SPEAR310_VIRQ_WAKEUP_SMII3, |
169 | .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK, | |
4c18e77f VK |
170 | }, |
171 | }; | |
172 | ||
f6558bf9 | 173 | static struct spear_shirq shirq_ras1 = { |
61e72bca | 174 | .irq = SPEAR3XX_IRQ_GEN_RAS_1, |
4c18e77f VK |
175 | .dev_config = shirq_ras1_config, |
176 | .dev_count = ARRAY_SIZE(shirq_ras1_config), | |
177 | .regs = { | |
178 | .enb_reg = -1, | |
61e72bca RM |
179 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
180 | .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK, | |
4c18e77f VK |
181 | .clear_reg = -1, |
182 | }, | |
183 | }; | |
184 | ||
f6558bf9 | 185 | static struct shirq_dev_config shirq_ras2_config[] = { |
4c18e77f | 186 | { |
61e72bca RM |
187 | .virq = SPEAR310_VIRQ_UART1, |
188 | .status_mask = SPEAR310_UART1_IRQ_MASK, | |
4c18e77f | 189 | }, { |
61e72bca RM |
190 | .virq = SPEAR310_VIRQ_UART2, |
191 | .status_mask = SPEAR310_UART2_IRQ_MASK, | |
4c18e77f | 192 | }, { |
61e72bca RM |
193 | .virq = SPEAR310_VIRQ_UART3, |
194 | .status_mask = SPEAR310_UART3_IRQ_MASK, | |
4c18e77f | 195 | }, { |
61e72bca RM |
196 | .virq = SPEAR310_VIRQ_UART4, |
197 | .status_mask = SPEAR310_UART4_IRQ_MASK, | |
4c18e77f | 198 | }, { |
61e72bca RM |
199 | .virq = SPEAR310_VIRQ_UART5, |
200 | .status_mask = SPEAR310_UART5_IRQ_MASK, | |
4c18e77f VK |
201 | }, |
202 | }; | |
203 | ||
f6558bf9 | 204 | static struct spear_shirq shirq_ras2 = { |
61e72bca | 205 | .irq = SPEAR3XX_IRQ_GEN_RAS_2, |
4c18e77f VK |
206 | .dev_config = shirq_ras2_config, |
207 | .dev_count = ARRAY_SIZE(shirq_ras2_config), | |
208 | .regs = { | |
209 | .enb_reg = -1, | |
61e72bca RM |
210 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
211 | .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK, | |
4c18e77f VK |
212 | .clear_reg = -1, |
213 | }, | |
214 | }; | |
215 | ||
f6558bf9 | 216 | static struct shirq_dev_config shirq_ras3_config[] = { |
4c18e77f | 217 | { |
61e72bca RM |
218 | .virq = SPEAR310_VIRQ_EMI, |
219 | .status_mask = SPEAR310_EMI_IRQ_MASK, | |
4c18e77f VK |
220 | }, |
221 | }; | |
222 | ||
f6558bf9 | 223 | static struct spear_shirq shirq_ras3 = { |
61e72bca | 224 | .irq = SPEAR3XX_IRQ_GEN_RAS_3, |
4c18e77f VK |
225 | .dev_config = shirq_ras3_config, |
226 | .dev_count = ARRAY_SIZE(shirq_ras3_config), | |
227 | .regs = { | |
228 | .enb_reg = -1, | |
61e72bca RM |
229 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
230 | .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK, | |
4c18e77f VK |
231 | .clear_reg = -1, |
232 | }, | |
233 | }; | |
234 | ||
f6558bf9 | 235 | static struct shirq_dev_config shirq_intrcomm_ras_config[] = { |
4c18e77f | 236 | { |
61e72bca RM |
237 | .virq = SPEAR310_VIRQ_TDM_HDLC, |
238 | .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK, | |
4c18e77f | 239 | }, { |
61e72bca RM |
240 | .virq = SPEAR310_VIRQ_RS485_0, |
241 | .status_mask = SPEAR310_RS485_0_IRQ_MASK, | |
4c18e77f | 242 | }, { |
61e72bca RM |
243 | .virq = SPEAR310_VIRQ_RS485_1, |
244 | .status_mask = SPEAR310_RS485_1_IRQ_MASK, | |
4c18e77f VK |
245 | }, |
246 | }; | |
247 | ||
f6558bf9 | 248 | static struct spear_shirq shirq_intrcomm_ras = { |
61e72bca | 249 | .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, |
4c18e77f VK |
250 | .dev_config = shirq_intrcomm_ras_config, |
251 | .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), | |
252 | .regs = { | |
253 | .enb_reg = -1, | |
61e72bca RM |
254 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
255 | .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK, | |
4c18e77f VK |
256 | .clear_reg = -1, |
257 | }, | |
258 | }; | |
259 | ||
c2c07831 VK |
260 | /* Add spear310 specific devices here */ |
261 | ||
70f4c0bf | 262 | /* spear310 routines */ |
6618c3ad RM |
263 | void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, |
264 | u8 pmx_dev_count) | |
bc4e814e | 265 | { |
4c18e77f VK |
266 | void __iomem *base; |
267 | int ret = 0; | |
268 | ||
bc4e814e VK |
269 | /* call spear3xx family common init function */ |
270 | spear3xx_init(); | |
4c18e77f | 271 | |
b595076a | 272 | /* shared irq registration */ |
53821162 | 273 | base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); |
4c18e77f VK |
274 | if (base) { |
275 | /* shirq 1 */ | |
276 | shirq_ras1.regs.base = base; | |
277 | ret = spear_shirq_register(&shirq_ras1); | |
278 | if (ret) | |
5fb00f96 | 279 | pr_err("Error registering Shared IRQ 1\n"); |
4c18e77f VK |
280 | |
281 | /* shirq 2 */ | |
282 | shirq_ras2.regs.base = base; | |
283 | ret = spear_shirq_register(&shirq_ras2); | |
284 | if (ret) | |
5fb00f96 | 285 | pr_err("Error registering Shared IRQ 2\n"); |
4c18e77f VK |
286 | |
287 | /* shirq 3 */ | |
288 | shirq_ras3.regs.base = base; | |
289 | ret = spear_shirq_register(&shirq_ras3); | |
290 | if (ret) | |
5fb00f96 | 291 | pr_err("Error registering Shared IRQ 3\n"); |
4c18e77f VK |
292 | |
293 | /* shirq 4 */ | |
294 | shirq_intrcomm_ras.regs.base = base; | |
295 | ret = spear_shirq_register(&shirq_intrcomm_ras); | |
296 | if (ret) | |
5fb00f96 | 297 | pr_err("Error registering Shared IRQ 4\n"); |
4c18e77f | 298 | } |
70f4c0bf | 299 | |
53688c51 VK |
300 | /* pmx initialization */ |
301 | pmx_driver.base = base; | |
6618c3ad RM |
302 | pmx_driver.mode = pmx_mode; |
303 | pmx_driver.devs = pmx_devs; | |
304 | pmx_driver.devs_count = pmx_dev_count; | |
305 | ||
53688c51 VK |
306 | ret = pmx_register(&pmx_driver); |
307 | if (ret) | |
5fb00f96 | 308 | pr_err("padmux: registration failed. err no: %d\n", ret); |
70f4c0bf | 309 | } |