[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-spear3xx / spear320.c

/*
 * arch/arm/mach-spear3xx/spear320.c
 *
 * SPEAr320 machine source file
 *
 * Copyright (C) 2009 ST Microelectronics
 * Viresh Kumar<viresh.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/ptrace.h>
#include <asm/irq.h>
#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/hardware.h>
#include <mach/spear.h>

/* pad multiplexing support */
/* muxing registers */
#define PAD_MUX_CONFIG_REG	0x0C
#define MODE_CONFIG_REG		0x10

/* modes */
#define AUTO_NET_SMII_MODE	(1 << 0)
#define AUTO_NET_MII_MODE	(1 << 1)
#define AUTO_EXP_MODE		(1 << 2)
#define SMALL_PRINTERS_MODE	(1 << 3)
#define ALL_MODES		0xF

struct pmx_mode spear320_auto_net_smii_mode = {
	.id = AUTO_NET_SMII_MODE,
	.name = "Automation Networking SMII Mode",
	.mask = 0x00,
};

struct pmx_mode spear320_auto_net_mii_mode = {
	.id = AUTO_NET_MII_MODE,
	.name = "Automation Networking MII Mode",
	.mask = 0x01,
};

struct pmx_mode spear320_auto_exp_mode = {
	.id = AUTO_EXP_MODE,
	.name = "Automation Expanded Mode",
	.mask = 0x02,
};

struct pmx_mode spear320_small_printers_mode = {
	.id = SMALL_PRINTERS_MODE,
	.name = "Small Printers Mode",
	.mask = 0x03,
};

/* devices */
static struct pmx_dev_mode pmx_clcd_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE,
		.mask = 0x0,
	},
};

struct pmx_dev spear320_pmx_clcd = {
	.name = "clcd",
	.modes = pmx_clcd_modes,
	.mode_count = ARRAY_SIZE(pmx_clcd_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_emi_modes[] = {
	{
		.ids = AUTO_EXP_MODE,
		.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
	},
};

struct pmx_dev spear320_pmx_emi = {
	.name = "emi",
	.modes = pmx_emi_modes,
	.mode_count = ARRAY_SIZE(pmx_emi_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_fsmc_modes[] = {
	{
		.ids = ALL_MODES,
		.mask = 0x0,
	},
};

struct pmx_dev spear320_pmx_fsmc = {
	.name = "fsmc",
	.modes = pmx_fsmc_modes,
	.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_spp_modes[] = {
	{
		.ids = SMALL_PRINTERS_MODE,
		.mask = 0x0,
	},
};

struct pmx_dev spear320_pmx_spp = {
	.name = "spp",
	.modes = pmx_spp_modes,
	.mode_count = ARRAY_SIZE(pmx_spp_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_sdhci_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
			SMALL_PRINTERS_MODE,
		.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
	},
};

struct pmx_dev spear320_pmx_sdhci = {
	.name = "sdhci",
	.modes = pmx_sdhci_modes,
	.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_i2s_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
		.mask = PMX_UART0_MODEM_MASK,
	},
};

struct pmx_dev spear320_pmx_i2s = {
	.name = "i2s",
	.modes = pmx_i2s_modes,
	.mode_count = ARRAY_SIZE(pmx_i2s_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_uart1_modes[] = {
	{
		.ids = ALL_MODES,
		.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
	},
};

struct pmx_dev spear320_pmx_uart1 = {
	.name = "uart1",
	.modes = pmx_uart1_modes,
	.mode_count = ARRAY_SIZE(pmx_uart1_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
	{
		.ids = AUTO_EXP_MODE,
		.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
			PMX_SSP_CS_MASK,
	}, {
		.ids = SMALL_PRINTERS_MODE,
		.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
			PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
	},
};

struct pmx_dev spear320_pmx_uart1_modem = {
	.name = "uart1_modem",
	.modes = pmx_uart1_modem_modes,
	.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_uart2_modes[] = {
	{
		.ids = ALL_MODES,
		.mask = PMX_FIRDA_MASK,
	},
};

struct pmx_dev spear320_pmx_uart2 = {
	.name = "uart2",
	.modes = pmx_uart2_modes,
	.mode_count = ARRAY_SIZE(pmx_uart2_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_touchscreen_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE,
		.mask = PMX_SSP_CS_MASK,
	},
};

struct pmx_dev spear320_pmx_touchscreen = {
	.name = "touchscreen",
	.modes = pmx_touchscreen_modes,
	.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_can_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
		.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
			PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
	},
};

struct pmx_dev spear320_pmx_can = {
	.name = "can",
	.modes = pmx_can_modes,
	.mode_count = ARRAY_SIZE(pmx_can_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
		.mask = PMX_SSP_CS_MASK,
	},
};

struct pmx_dev spear320_pmx_sdhci_led = {
	.name = "sdhci_led",
	.modes = pmx_sdhci_led_modes,
	.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_pwm0_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
		.mask = PMX_UART0_MODEM_MASK,
	}, {
		.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev spear320_pmx_pwm0 = {
	.name = "pwm0",
	.modes = pmx_pwm0_modes,
	.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_pwm1_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
		.mask = PMX_UART0_MODEM_MASK,
	}, {
		.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev spear320_pmx_pwm1 = {
	.name = "pwm1",
	.modes = pmx_pwm1_modes,
	.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_pwm2_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
		.mask = PMX_SSP_CS_MASK,
	}, {
		.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev spear320_pmx_pwm2 = {
	.name = "pwm2",
	.modes = pmx_pwm2_modes,
	.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_pwm3_modes[] = {
	{
		.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev spear320_pmx_pwm3 = {
	.name = "pwm3",
	.modes = pmx_pwm3_modes,
	.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_ssp1_modes[] = {
	{
		.ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev spear320_pmx_ssp1 = {
	.name = "ssp1",
	.modes = pmx_ssp1_modes,
	.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_ssp2_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev spear320_pmx_ssp2 = {
	.name = "ssp2",
	.modes = pmx_ssp2_modes,
	.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_mii1_modes[] = {
	{
		.ids = AUTO_NET_MII_MODE,
		.mask = 0x0,
	},
};

struct pmx_dev spear320_pmx_mii1 = {
	.name = "mii1",
	.modes = pmx_mii1_modes,
	.mode_count = ARRAY_SIZE(pmx_mii1_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_smii0_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev spear320_pmx_smii0 = {
	.name = "smii0",
	.modes = pmx_smii0_modes,
	.mode_count = ARRAY_SIZE(pmx_smii0_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_smii1_modes[] = {
	{
		.ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev spear320_pmx_smii1 = {
	.name = "smii1",
	.modes = pmx_smii1_modes,
	.mode_count = ARRAY_SIZE(pmx_smii1_modes),
	.enb_on_reset = 1,
};

static struct pmx_dev_mode pmx_i2c1_modes[] = {
	{
		.ids = AUTO_EXP_MODE,
		.mask = 0x0,
	},
};

struct pmx_dev spear320_pmx_i2c1 = {
	.name = "i2c1",
	.modes = pmx_i2c1_modes,
	.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
	.enb_on_reset = 1,
};

/* pmx driver structure */
static struct pmx_driver pmx_driver = {
	.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
};

/* spear3xx shared irq */
static struct shirq_dev_config shirq_ras1_config[] = {
	{
		.virq = SPEAR320_VIRQ_EMI,
		.status_mask = SPEAR320_EMI_IRQ_MASK,
		.clear_mask = SPEAR320_EMI_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_CLCD,
		.status_mask = SPEAR320_CLCD_IRQ_MASK,
		.clear_mask = SPEAR320_CLCD_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_SPP,
		.status_mask = SPEAR320_SPP_IRQ_MASK,
		.clear_mask = SPEAR320_SPP_IRQ_MASK,
	},
};

static struct spear_shirq shirq_ras1 = {
	.irq = SPEAR3XX_IRQ_GEN_RAS_1,
	.dev_config = shirq_ras1_config,
	.dev_count = ARRAY_SIZE(shirq_ras1_config),
	.regs = {
		.enb_reg = -1,
		.status_reg = SPEAR320_INT_STS_MASK_REG,
		.status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
		.reset_to_clear = 1,
	},
};

static struct shirq_dev_config shirq_ras3_config[] = {
	{
		.virq = SPEAR320_VIRQ_PLGPIO,
		.enb_mask = SPEAR320_GPIO_IRQ_MASK,
		.status_mask = SPEAR320_GPIO_IRQ_MASK,
		.clear_mask = SPEAR320_GPIO_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_I2S_PLAY,
		.enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
		.status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
		.clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_I2S_REC,
		.enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
		.status_mask = SPEAR320_I2S_REC_IRQ_MASK,
		.clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
	},
};

static struct spear_shirq shirq_ras3 = {
	.irq = SPEAR3XX_IRQ_GEN_RAS_3,
	.dev_config = shirq_ras3_config,
	.dev_count = ARRAY_SIZE(shirq_ras3_config),
	.regs = {
		.enb_reg = SPEAR320_INT_ENB_MASK_REG,
		.reset_to_enb = 1,
		.status_reg = SPEAR320_INT_STS_MASK_REG,
		.status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
		.reset_to_clear = 1,
	},
};

static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
	{
		.virq = SPEAR320_VIRQ_CANU,
		.status_mask = SPEAR320_CAN_U_IRQ_MASK,
		.clear_mask = SPEAR320_CAN_U_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_CANL,
		.status_mask = SPEAR320_CAN_L_IRQ_MASK,
		.clear_mask = SPEAR320_CAN_L_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_UART1,
		.status_mask = SPEAR320_UART1_IRQ_MASK,
		.clear_mask = SPEAR320_UART1_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_UART2,
		.status_mask = SPEAR320_UART2_IRQ_MASK,
		.clear_mask = SPEAR320_UART2_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_SSP1,
		.status_mask = SPEAR320_SSP1_IRQ_MASK,
		.clear_mask = SPEAR320_SSP1_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_SSP2,
		.status_mask = SPEAR320_SSP2_IRQ_MASK,
		.clear_mask = SPEAR320_SSP2_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_SMII0,
		.status_mask = SPEAR320_SMII0_IRQ_MASK,
		.clear_mask = SPEAR320_SMII0_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_MII1_SMII1,
		.status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
		.clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_WAKEUP_SMII0,
		.status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
		.clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
		.status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
		.clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
	}, {
		.virq = SPEAR320_VIRQ_I2C1,
		.status_mask = SPEAR320_I2C1_IRQ_MASK,
		.clear_mask = SPEAR320_I2C1_IRQ_MASK,
	},
};

static struct spear_shirq shirq_intrcomm_ras = {
	.irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
	.dev_config = shirq_intrcomm_ras_config,
	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
	.regs = {
		.enb_reg = -1,
		.status_reg = SPEAR320_INT_STS_MASK_REG,
		.status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
		.reset_to_clear = 1,
	},
};

/* Add spear320 specific devices here */

/* spear320 routines */
void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
		u8 pmx_dev_count)
{
	void __iomem *base;
	int ret = 0;

	/* call spear3xx family common init function */
	spear3xx_init();

	/* shared irq registration */
	base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
	if (base) {
		/* shirq 1 */
		shirq_ras1.regs.base = base;
		ret = spear_shirq_register(&shirq_ras1);
		if (ret)
			printk(KERN_ERR "Error registering Shared IRQ 1\n");

		/* shirq 3 */
		shirq_ras3.regs.base = base;
		ret = spear_shirq_register(&shirq_ras3);
		if (ret)
			printk(KERN_ERR "Error registering Shared IRQ 3\n");

		/* shirq 4 */
		shirq_intrcomm_ras.regs.base = base;
		ret = spear_shirq_register(&shirq_intrcomm_ras);
		if (ret)
			printk(KERN_ERR "Error registering Shared IRQ 4\n");
	}

	/* pmx initialization */
	pmx_driver.base = base;
	pmx_driver.mode = pmx_mode;
	pmx_driver.devs = pmx_devs;
	pmx_driver.devs_count = pmx_dev_count;

	ret = pmx_register(&pmx_driver);
	if (ret)
		printk(KERN_ERR "padmux: registration failed. err no: %d\n",
				ret);
}
Commit	Line	Data
bc4e814e VK	1	/*
	2	* arch/arm/mach-spear3xx/spear320.c
	3	*
	4	* SPEAr320 machine source file
	5	*
	6	* Copyright (C) 2009 ST Microelectronics
	7	* Viresh Kumar<viresh.kumar@st.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include <linux/ptrace.h>
	15	#include <asm/irq.h>
410782be	16	#include <plat/shirq.h>
bc4e814e	17	#include <mach/generic.h>
02aa06bc	18	#include <mach/hardware.h>
5df33a62	19	#include <mach/spear.h>
bc4e814e	20
70f4c0bf VK	21	/* pad multiplexing support */
	22	/* muxing registers */
	23	#define PAD_MUX_CONFIG_REG 0x0C
	24	#define MODE_CONFIG_REG 0x10
	25
	26	/* modes */
	27	#define AUTO_NET_SMII_MODE (1 << 0)
	28	#define AUTO_NET_MII_MODE (1 << 1)
	29	#define AUTO_EXP_MODE (1 << 2)
	30	#define SMALL_PRINTERS_MODE (1 << 3)
	31	#define ALL_MODES 0xF
	32
6618c3ad	33	struct pmx_mode spear320_auto_net_smii_mode = {
70f4c0bf VK	34	.id = AUTO_NET_SMII_MODE,
	35	.name = "Automation Networking SMII Mode",
	36	.mask = 0x00,
	37	};
	38
6618c3ad	39	struct pmx_mode spear320_auto_net_mii_mode = {
70f4c0bf VK	40	.id = AUTO_NET_MII_MODE,
	41	.name = "Automation Networking MII Mode",
	42	.mask = 0x01,
	43	};
	44
6618c3ad	45	struct pmx_mode spear320_auto_exp_mode = {
70f4c0bf VK	46	.id = AUTO_EXP_MODE,
	47	.name = "Automation Expanded Mode",
	48	.mask = 0x02,
	49	};
	50
6618c3ad	51	struct pmx_mode spear320_small_printers_mode = {
70f4c0bf VK	52	.id = SMALL_PRINTERS_MODE,
	53	.name = "Small Printers Mode",
	54	.mask = 0x03,
	55	};
	56
	57	/* devices */
6618c3ad	58	static struct pmx_dev_mode pmx_clcd_modes[] = {
70f4c0bf VK	59	{
	60	.ids = AUTO_NET_SMII_MODE,
	61	.mask = 0x0,
	62	},
	63	};
	64
6618c3ad	65	struct pmx_dev spear320_pmx_clcd = {
70f4c0bf VK	66	.name = "clcd",
	67	.modes = pmx_clcd_modes,
	68	.mode_count = ARRAY_SIZE(pmx_clcd_modes),
	69	.enb_on_reset = 1,
	70	};
	71
6618c3ad	72	static struct pmx_dev_mode pmx_emi_modes[] = {
70f4c0bf VK	73	{
	74	.ids = AUTO_EXP_MODE,
	75	.mask = PMX_TIMER_1_2_MASK \| PMX_TIMER_3_4_MASK,
	76	},
	77	};
	78
6618c3ad	79	struct pmx_dev spear320_pmx_emi = {
70f4c0bf VK	80	.name = "emi",
	81	.modes = pmx_emi_modes,
	82	.mode_count = ARRAY_SIZE(pmx_emi_modes),
	83	.enb_on_reset = 1,
	84	};
	85
6618c3ad	86	static struct pmx_dev_mode pmx_fsmc_modes[] = {
70f4c0bf VK	87	{
	88	.ids = ALL_MODES,
	89	.mask = 0x0,
	90	},
	91	};
	92
6618c3ad	93	struct pmx_dev spear320_pmx_fsmc = {
70f4c0bf VK	94	.name = "fsmc",
	95	.modes = pmx_fsmc_modes,
	96	.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
	97	.enb_on_reset = 1,
	98	};
	99
6618c3ad	100	static struct pmx_dev_mode pmx_spp_modes[] = {
70f4c0bf VK	101	{
	102	.ids = SMALL_PRINTERS_MODE,
	103	.mask = 0x0,
	104	},
	105	};
	106
6618c3ad	107	struct pmx_dev spear320_pmx_spp = {
70f4c0bf VK	108	.name = "spp",
	109	.modes = pmx_spp_modes,
	110	.mode_count = ARRAY_SIZE(pmx_spp_modes),
	111	.enb_on_reset = 1,
	112	};
	113
6618c3ad	114	static struct pmx_dev_mode pmx_sdhci_modes[] = {
70f4c0bf VK	115	{
	116	.ids = AUTO_NET_SMII_MODE \| AUTO_NET_MII_MODE \|
	117	SMALL_PRINTERS_MODE,
	118	.mask = PMX_TIMER_1_2_MASK \| PMX_TIMER_3_4_MASK,
	119	},
	120	};
	121
6618c3ad	122	struct pmx_dev spear320_pmx_sdhci = {
069580b8 VK	123	.name = "sdhci",
	124	.modes = pmx_sdhci_modes,
	125	.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
70f4c0bf VK	126	.enb_on_reset = 1,
	127	};
	128
6618c3ad	129	static struct pmx_dev_mode pmx_i2s_modes[] = {
70f4c0bf VK	130	{
	131	.ids = AUTO_NET_SMII_MODE \| AUTO_NET_MII_MODE,
	132	.mask = PMX_UART0_MODEM_MASK,
	133	},
	134	};
	135
6618c3ad	136	struct pmx_dev spear320_pmx_i2s = {
70f4c0bf VK	137	.name = "i2s",
	138	.modes = pmx_i2s_modes,
	139	.mode_count = ARRAY_SIZE(pmx_i2s_modes),
	140	.enb_on_reset = 1,
	141	};
	142
6618c3ad	143	static struct pmx_dev_mode pmx_uart1_modes[] = {
70f4c0bf VK	144	{
	145	.ids = ALL_MODES,
	146	.mask = PMX_GPIO_PIN0_MASK \| PMX_GPIO_PIN1_MASK,
	147	},
	148	};
	149
6618c3ad	150	struct pmx_dev spear320_pmx_uart1 = {
70f4c0bf VK	151	.name = "uart1",
	152	.modes = pmx_uart1_modes,
	153	.mode_count = ARRAY_SIZE(pmx_uart1_modes),
	154	.enb_on_reset = 1,
	155	};
	156
6618c3ad	157	static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
70f4c0bf VK	158	{
	159	.ids = AUTO_EXP_MODE,
	160	.mask = PMX_TIMER_1_2_MASK \| PMX_TIMER_3_4_MASK \|
	161	PMX_SSP_CS_MASK,
	162	}, {
	163	.ids = SMALL_PRINTERS_MODE,
	164	.mask = PMX_GPIO_PIN3_MASK \| PMX_GPIO_PIN4_MASK \|
	165	PMX_GPIO_PIN5_MASK \| PMX_SSP_CS_MASK,
	166	},
	167	};
	168
6618c3ad	169	struct pmx_dev spear320_pmx_uart1_modem = {
70f4c0bf VK	170	.name = "uart1_modem",
	171	.modes = pmx_uart1_modem_modes,
	172	.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
	173	.enb_on_reset = 1,
	174	};
	175
6618c3ad	176	static struct pmx_dev_mode pmx_uart2_modes[] = {
70f4c0bf VK	177	{
	178	.ids = ALL_MODES,
	179	.mask = PMX_FIRDA_MASK,
	180	},
	181	};
	182
6618c3ad	183	struct pmx_dev spear320_pmx_uart2 = {
70f4c0bf VK	184	.name = "uart2",
	185	.modes = pmx_uart2_modes,
	186	.mode_count = ARRAY_SIZE(pmx_uart2_modes),
	187	.enb_on_reset = 1,
	188	};
	189
6618c3ad	190	static struct pmx_dev_mode pmx_touchscreen_modes[] = {
70f4c0bf VK	191	{
	192	.ids = AUTO_NET_SMII_MODE,
	193	.mask = PMX_SSP_CS_MASK,
	194	},
	195	};
	196
6618c3ad	197	struct pmx_dev spear320_pmx_touchscreen = {
70f4c0bf VK	198	.name = "touchscreen",
	199	.modes = pmx_touchscreen_modes,
	200	.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
	201	.enb_on_reset = 1,
	202	};
	203
6618c3ad	204	static struct pmx_dev_mode pmx_can_modes[] = {
70f4c0bf VK	205	{
	206	.ids = AUTO_NET_SMII_MODE \| AUTO_NET_MII_MODE \| AUTO_EXP_MODE,
	207	.mask = PMX_GPIO_PIN2_MASK \| PMX_GPIO_PIN3_MASK \|
	208	PMX_GPIO_PIN4_MASK \| PMX_GPIO_PIN5_MASK,
	209	},
	210	};
	211
6618c3ad	212	struct pmx_dev spear320_pmx_can = {
70f4c0bf VK	213	.name = "can",
	214	.modes = pmx_can_modes,
	215	.mode_count = ARRAY_SIZE(pmx_can_modes),
	216	.enb_on_reset = 1,
	217	};
	218
6618c3ad	219	static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
70f4c0bf VK	220	{
	221	.ids = AUTO_NET_SMII_MODE \| AUTO_NET_MII_MODE,
	222	.mask = PMX_SSP_CS_MASK,
	223	},
	224	};
	225
6618c3ad	226	struct pmx_dev spear320_pmx_sdhci_led = {
069580b8 VK	227	.name = "sdhci_led",
	228	.modes = pmx_sdhci_led_modes,
	229	.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
70f4c0bf VK	230	.enb_on_reset = 1,
	231	};
	232
6618c3ad	233	static struct pmx_dev_mode pmx_pwm0_modes[] = {
70f4c0bf VK	234	{
	235	.ids = AUTO_NET_SMII_MODE \| AUTO_NET_MII_MODE,
	236	.mask = PMX_UART0_MODEM_MASK,
	237	}, {
	238	.ids = AUTO_EXP_MODE \| SMALL_PRINTERS_MODE,
	239	.mask = PMX_MII_MASK,
	240	},
	241	};
	242
6618c3ad	243	struct pmx_dev spear320_pmx_pwm0 = {
70f4c0bf VK	244	.name = "pwm0",
	245	.modes = pmx_pwm0_modes,
	246	.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
	247	.enb_on_reset = 1,
	248	};
	249
6618c3ad	250	static struct pmx_dev_mode pmx_pwm1_modes[] = {
70f4c0bf VK	251	{
	252	.ids = AUTO_NET_SMII_MODE \| AUTO_NET_MII_MODE,
	253	.mask = PMX_UART0_MODEM_MASK,
	254	}, {
	255	.ids = AUTO_EXP_MODE \| SMALL_PRINTERS_MODE,
	256	.mask = PMX_MII_MASK,
	257	},
	258	};
	259
6618c3ad	260	struct pmx_dev spear320_pmx_pwm1 = {
70f4c0bf VK	261	.name = "pwm1",
	262	.modes = pmx_pwm1_modes,
	263	.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
	264	.enb_on_reset = 1,
	265	};
	266
6618c3ad	267	static struct pmx_dev_mode pmx_pwm2_modes[] = {
70f4c0bf VK	268	{
	269	.ids = AUTO_NET_SMII_MODE \| AUTO_NET_MII_MODE,
	270	.mask = PMX_SSP_CS_MASK,
	271	}, {
	272	.ids = AUTO_EXP_MODE \| SMALL_PRINTERS_MODE,
	273	.mask = PMX_MII_MASK,
	274	},
	275	};
	276
6618c3ad	277	struct pmx_dev spear320_pmx_pwm2 = {
70f4c0bf VK	278	.name = "pwm2",
	279	.modes = pmx_pwm2_modes,
	280	.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
	281	.enb_on_reset = 1,
	282	};
	283
6618c3ad	284	static struct pmx_dev_mode pmx_pwm3_modes[] = {
70f4c0bf VK	285	{
	286	.ids = AUTO_EXP_MODE \| SMALL_PRINTERS_MODE \| AUTO_NET_SMII_MODE,
	287	.mask = PMX_MII_MASK,
	288	},
	289	};
	290
6618c3ad	291	struct pmx_dev spear320_pmx_pwm3 = {
70f4c0bf VK	292	.name = "pwm3",
	293	.modes = pmx_pwm3_modes,
	294	.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
	295	.enb_on_reset = 1,
	296	};
	297
6618c3ad	298	static struct pmx_dev_mode pmx_ssp1_modes[] = {
70f4c0bf VK	299	{
	300	.ids = SMALL_PRINTERS_MODE \| AUTO_NET_SMII_MODE,
	301	.mask = PMX_MII_MASK,
	302	},
	303	};
	304
6618c3ad	305	struct pmx_dev spear320_pmx_ssp1 = {
70f4c0bf VK	306	.name = "ssp1",
	307	.modes = pmx_ssp1_modes,
	308	.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
	309	.enb_on_reset = 1,
	310	};
	311
6618c3ad	312	static struct pmx_dev_mode pmx_ssp2_modes[] = {
70f4c0bf VK	313	{
	314	.ids = AUTO_NET_SMII_MODE,
	315	.mask = PMX_MII_MASK,
	316	},
	317	};
	318
6618c3ad	319	struct pmx_dev spear320_pmx_ssp2 = {
70f4c0bf VK	320	.name = "ssp2",
	321	.modes = pmx_ssp2_modes,
	322	.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
	323	.enb_on_reset = 1,
	324	};
	325
6618c3ad	326	static struct pmx_dev_mode pmx_mii1_modes[] = {
70f4c0bf VK	327	{
	328	.ids = AUTO_NET_MII_MODE,
	329	.mask = 0x0,
	330	},
	331	};
	332
6618c3ad	333	struct pmx_dev spear320_pmx_mii1 = {
70f4c0bf VK	334	.name = "mii1",
	335	.modes = pmx_mii1_modes,
	336	.mode_count = ARRAY_SIZE(pmx_mii1_modes),
	337	.enb_on_reset = 1,
	338	};
	339
6618c3ad	340	static struct pmx_dev_mode pmx_smii0_modes[] = {
70f4c0bf VK	341	{
	342	.ids = AUTO_NET_SMII_MODE \| AUTO_EXP_MODE \| SMALL_PRINTERS_MODE,
	343	.mask = PMX_MII_MASK,
	344	},
	345	};
	346
6618c3ad	347	struct pmx_dev spear320_pmx_smii0 = {
70f4c0bf VK	348	.name = "smii0",
	349	.modes = pmx_smii0_modes,
	350	.mode_count = ARRAY_SIZE(pmx_smii0_modes),
	351	.enb_on_reset = 1,
	352	};
	353
6618c3ad	354	static struct pmx_dev_mode pmx_smii1_modes[] = {
70f4c0bf VK	355	{
	356	.ids = AUTO_NET_SMII_MODE \| SMALL_PRINTERS_MODE,
	357	.mask = PMX_MII_MASK,
	358	},
	359	};
	360
6618c3ad	361	struct pmx_dev spear320_pmx_smii1 = {
70f4c0bf VK	362	.name = "smii1",
	363	.modes = pmx_smii1_modes,
	364	.mode_count = ARRAY_SIZE(pmx_smii1_modes),
	365	.enb_on_reset = 1,
	366	};
	367
6618c3ad	368	static struct pmx_dev_mode pmx_i2c1_modes[] = {
70f4c0bf VK	369	{
	370	.ids = AUTO_EXP_MODE,
	371	.mask = 0x0,
	372	},
	373	};
	374
6618c3ad	375	struct pmx_dev spear320_pmx_i2c1 = {
70f4c0bf VK	376	.name = "i2c1",
	377	.modes = pmx_i2c1_modes,
	378	.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
	379	.enb_on_reset = 1,
	380	};
	381
	382	/* pmx driver structure */
6618c3ad	383	static struct pmx_driver pmx_driver = {
70f4c0bf VK	384	.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
	385	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
	386	};
	387
4c18e77f	388	/* spear3xx shared irq */
f6558bf9	389	static struct shirq_dev_config shirq_ras1_config[] = {
4c18e77f	390	{
61e72bca RM	391	.virq = SPEAR320_VIRQ_EMI,
	392	.status_mask = SPEAR320_EMI_IRQ_MASK,
	393	.clear_mask = SPEAR320_EMI_IRQ_MASK,
4c18e77f	394	}, {
61e72bca RM	395	.virq = SPEAR320_VIRQ_CLCD,
	396	.status_mask = SPEAR320_CLCD_IRQ_MASK,
	397	.clear_mask = SPEAR320_CLCD_IRQ_MASK,
4c18e77f	398	}, {
61e72bca RM	399	.virq = SPEAR320_VIRQ_SPP,
	400	.status_mask = SPEAR320_SPP_IRQ_MASK,
	401	.clear_mask = SPEAR320_SPP_IRQ_MASK,
4c18e77f VK	402	},
	403	};
	404
f6558bf9	405	static struct spear_shirq shirq_ras1 = {
61e72bca	406	.irq = SPEAR3XX_IRQ_GEN_RAS_1,
4c18e77f VK	407	.dev_config = shirq_ras1_config,
	408	.dev_count = ARRAY_SIZE(shirq_ras1_config),
	409	.regs = {
	410	.enb_reg = -1,
61e72bca RM	411	.status_reg = SPEAR320_INT_STS_MASK_REG,
	412	.status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
	413	.clear_reg = SPEAR320_INT_CLR_MASK_REG,
4c18e77f VK	414	.reset_to_clear = 1,
	415	},
	416	};
	417
f6558bf9	418	static struct shirq_dev_config shirq_ras3_config[] = {
4c18e77f	419	{
61e72bca RM	420	.virq = SPEAR320_VIRQ_PLGPIO,
	421	.enb_mask = SPEAR320_GPIO_IRQ_MASK,
	422	.status_mask = SPEAR320_GPIO_IRQ_MASK,
	423	.clear_mask = SPEAR320_GPIO_IRQ_MASK,
4c18e77f	424	}, {
61e72bca RM	425	.virq = SPEAR320_VIRQ_I2S_PLAY,
	426	.enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
	427	.status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
	428	.clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
4c18e77f	429	}, {
61e72bca RM	430	.virq = SPEAR320_VIRQ_I2S_REC,
	431	.enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
	432	.status_mask = SPEAR320_I2S_REC_IRQ_MASK,
	433	.clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
4c18e77f VK	434	},
	435	};
	436
f6558bf9	437	static struct spear_shirq shirq_ras3 = {
61e72bca	438	.irq = SPEAR3XX_IRQ_GEN_RAS_3,
4c18e77f VK	439	.dev_config = shirq_ras3_config,
	440	.dev_count = ARRAY_SIZE(shirq_ras3_config),
	441	.regs = {
61e72bca	442	.enb_reg = SPEAR320_INT_ENB_MASK_REG,
4c18e77f	443	.reset_to_enb = 1,
61e72bca RM	444	.status_reg = SPEAR320_INT_STS_MASK_REG,
	445	.status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
	446	.clear_reg = SPEAR320_INT_CLR_MASK_REG,
4c18e77f VK	447	.reset_to_clear = 1,
	448	},
	449	};
	450
f6558bf9	451	static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
4c18e77f	452	{
61e72bca RM	453	.virq = SPEAR320_VIRQ_CANU,
	454	.status_mask = SPEAR320_CAN_U_IRQ_MASK,
	455	.clear_mask = SPEAR320_CAN_U_IRQ_MASK,
4c18e77f	456	}, {
61e72bca RM	457	.virq = SPEAR320_VIRQ_CANL,
	458	.status_mask = SPEAR320_CAN_L_IRQ_MASK,
	459	.clear_mask = SPEAR320_CAN_L_IRQ_MASK,
4c18e77f	460	}, {
61e72bca RM	461	.virq = SPEAR320_VIRQ_UART1,
	462	.status_mask = SPEAR320_UART1_IRQ_MASK,
	463	.clear_mask = SPEAR320_UART1_IRQ_MASK,
4c18e77f	464	}, {
61e72bca RM	465	.virq = SPEAR320_VIRQ_UART2,
	466	.status_mask = SPEAR320_UART2_IRQ_MASK,
	467	.clear_mask = SPEAR320_UART2_IRQ_MASK,
4c18e77f	468	}, {
61e72bca RM	469	.virq = SPEAR320_VIRQ_SSP1,
	470	.status_mask = SPEAR320_SSP1_IRQ_MASK,
	471	.clear_mask = SPEAR320_SSP1_IRQ_MASK,
4c18e77f	472	}, {
61e72bca RM	473	.virq = SPEAR320_VIRQ_SSP2,
	474	.status_mask = SPEAR320_SSP2_IRQ_MASK,
	475	.clear_mask = SPEAR320_SSP2_IRQ_MASK,
4c18e77f	476	}, {
61e72bca RM	477	.virq = SPEAR320_VIRQ_SMII0,
	478	.status_mask = SPEAR320_SMII0_IRQ_MASK,
	479	.clear_mask = SPEAR320_SMII0_IRQ_MASK,
4c18e77f	480	}, {
61e72bca RM	481	.virq = SPEAR320_VIRQ_MII1_SMII1,
	482	.status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
	483	.clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
4c18e77f	484	}, {
61e72bca RM	485	.virq = SPEAR320_VIRQ_WAKEUP_SMII0,
	486	.status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
	487	.clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
4c18e77f	488	}, {
61e72bca RM	489	.virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
	490	.status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
	491	.clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
4c18e77f	492	}, {
61e72bca RM	493	.virq = SPEAR320_VIRQ_I2C1,
	494	.status_mask = SPEAR320_I2C1_IRQ_MASK,
	495	.clear_mask = SPEAR320_I2C1_IRQ_MASK,
4c18e77f VK	496	},
	497	};
	498
f6558bf9	499	static struct spear_shirq shirq_intrcomm_ras = {
61e72bca	500	.irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
4c18e77f VK	501	.dev_config = shirq_intrcomm_ras_config,
	502	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
	503	.regs = {
	504	.enb_reg = -1,
61e72bca RM	505	.status_reg = SPEAR320_INT_STS_MASK_REG,
	506	.status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
	507	.clear_reg = SPEAR320_INT_CLR_MASK_REG,
4c18e77f VK	508	.reset_to_clear = 1,
	509	},
	510	};
	511
c2c07831 VK	512	/* Add spear320 specific devices here */
c2c07831 VK	513
70f4c0bf	514	/* spear320 routines */
6618c3ad RM	515	void __init spear320_init(struct pmx_mode pmx_mode, struct pmx_dev *pmx_devs,
6618c3ad RM	516	u8 pmx_dev_count)
bc4e814e	517	{
4c18e77f VK	518	void __iomem *base;
	519	int ret = 0;
	520
bc4e814e VK	521	/* call spear3xx family common init function */
bc4e814e VK	522	spear3xx_init();
4c18e77f	523
b595076a	524	/* shared irq registration */
53821162	525	base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
4c18e77f VK	526	if (base) {
	527	/* shirq 1 */
	528	shirq_ras1.regs.base = base;
	529	ret = spear_shirq_register(&shirq_ras1);
	530	if (ret)
	531	printk(KERN_ERR "Error registering Shared IRQ 1\n");
	532
	533	/* shirq 3 */
	534	shirq_ras3.regs.base = base;
	535	ret = spear_shirq_register(&shirq_ras3);
	536	if (ret)
	537	printk(KERN_ERR "Error registering Shared IRQ 3\n");
	538
	539	/* shirq 4 */
	540	shirq_intrcomm_ras.regs.base = base;
	541	ret = spear_shirq_register(&shirq_intrcomm_ras);
	542	if (ret)
	543	printk(KERN_ERR "Error registering Shared IRQ 4\n");
	544	}
70f4c0bf	545
53688c51 VK	546	/* pmx initialization */
53688c51 VK	547	pmx_driver.base = base;
6618c3ad RM	548	pmx_driver.mode = pmx_mode;
	549	pmx_driver.devs = pmx_devs;
	550	pmx_driver.devs_count = pmx_dev_count;
	551
53688c51 VK	552	ret = pmx_register(&pmx_driver);
53688c51 VK	553	if (ret)
15b9cf6d	554	printk(KERN_ERR "padmux: registration failed. err no: %d\n",
53688c51	555	ret);
70f4c0bf	556	}