[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-spear6xx / clock.c

/*
 * arch/arm/mach-spear6xx/clock.c
 *
 * SPEAr6xx machines clock framework source file
 *
 * Copyright (C) 2009 ST Microelectronics
 * Viresh Kumar<viresh.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <plat/clock.h>
#include <mach/misc_regs.h>

/* root clks */
/* 32 KHz oscillator clock */
static struct clk osc_32k_clk = {
	.flags = ALWAYS_ENABLED,
	.rate = 32000,
};

/* 30 MHz oscillator clock */
static struct clk osc_30m_clk = {
	.flags = ALWAYS_ENABLED,
	.rate = 30000000,
};

/* clock derived from 32 KHz osc clk */
/* rtc clock */
static struct clk rtc_clk = {
	.pclk = &osc_32k_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = RTC_CLK_ENB,
	.recalc = &follow_parent,
};

/* clock derived from 30 MHz osc clk */
/* pll masks structure */
static struct pll_clk_masks pll1_masks = {
	.mode_mask = PLL_MODE_MASK,
	.mode_shift = PLL_MODE_SHIFT,
	.norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
	.norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
	.dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
	.dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
	.div_p_mask = PLL_DIV_P_MASK,
	.div_p_shift = PLL_DIV_P_SHIFT,
	.div_n_mask = PLL_DIV_N_MASK,
	.div_n_shift = PLL_DIV_N_SHIFT,
};

/* pll1 configuration structure */
static struct pll_clk_config pll1_config = {
	.mode_reg = PLL1_CTR,
	.cfg_reg = PLL1_FRQ,
	.masks = &pll1_masks,
};

/* pll rate configuration table, in ascending order of rates */
struct pll_rate_tbl pll_rtbl[] = {
	{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
	{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
};

/* PLL1 clock */
static struct clk pll1_clk = {
	.flags = ENABLED_ON_INIT,
	.pclk = &osc_30m_clk,
	.en_reg = PLL1_CTR,
	.en_reg_bit = PLL_ENABLE,
	.calc_rate = &pll_calc_rate,
	.recalc = &pll_clk_recalc,
	.set_rate = &pll_clk_set_rate,
	.rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
	.private_data = &pll1_config,
};

/* PLL3 48 MHz clock */
static struct clk pll3_48m_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &osc_30m_clk,
	.rate = 48000000,
};

/* watch dog timer clock */
static struct clk wdt_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &osc_30m_clk,
	.recalc = &follow_parent,
};

/* clock derived from pll1 clk */
/* cpu clock */
static struct clk cpu_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &pll1_clk,
	.recalc = &follow_parent,
};

/* ahb masks structure */
static struct bus_clk_masks ahb_masks = {
	.mask = PLL_HCLK_RATIO_MASK,
	.shift = PLL_HCLK_RATIO_SHIFT,
};

/* ahb configuration structure */
static struct bus_clk_config ahb_config = {
	.reg = CORE_CLK_CFG,
	.masks = &ahb_masks,
};

/* ahb rate configuration table, in ascending order of rates */
struct bus_rate_tbl bus_rtbl[] = {
	{.div = 3}, /* == parent divided by 4 */
	{.div = 2}, /* == parent divided by 3 */
	{.div = 1}, /* == parent divided by 2 */
	{.div = 0}, /* == parent divided by 1 */
};

/* ahb clock */
static struct clk ahb_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &pll1_clk,
	.calc_rate = &bus_calc_rate,
	.recalc = &bus_clk_recalc,
	.set_rate = &bus_clk_set_rate,
	.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
	.private_data = &ahb_config,
};

/* auxiliary synthesizers masks */
static struct aux_clk_masks aux_masks = {
	.eq_sel_mask = AUX_EQ_SEL_MASK,
	.eq_sel_shift = AUX_EQ_SEL_SHIFT,
	.eq1_mask = AUX_EQ1_SEL,
	.eq2_mask = AUX_EQ2_SEL,
	.xscale_sel_mask = AUX_XSCALE_MASK,
	.xscale_sel_shift = AUX_XSCALE_SHIFT,
	.yscale_sel_mask = AUX_YSCALE_MASK,
	.yscale_sel_shift = AUX_YSCALE_SHIFT,
};

/* uart configurations */
static struct aux_clk_config uart_synth_config = {
	.synth_reg = UART_CLK_SYNT,
	.masks = &aux_masks,
};

/* aux rate configuration table, in ascending order of rates */
struct aux_rate_tbl aux_rtbl[] = {
	/* For PLL1 = 332 MHz */
	{.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
	{.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
	{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
};

/* uart synth clock */
static struct clk uart_synth_clk = {
	.en_reg = UART_CLK_SYNT,
	.en_reg_bit = AUX_SYNT_ENB,
	.pclk = &pll1_clk,
	.calc_rate = &aux_calc_rate,
	.recalc = &aux_clk_recalc,
	.set_rate = &aux_clk_set_rate,
	.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
	.private_data = &uart_synth_config,
};

/* uart parents */
static struct pclk_info uart_pclk_info[] = {
	{
		.pclk = &uart_synth_clk,
		.pclk_val = AUX_CLK_PLL1_VAL,
	}, {
		.pclk = &pll3_48m_clk,
		.pclk_val = AUX_CLK_PLL3_VAL,
	},
};

/* uart parent select structure */
static struct pclk_sel uart_pclk_sel = {
	.pclk_info = uart_pclk_info,
	.pclk_count = ARRAY_SIZE(uart_pclk_info),
	.pclk_sel_reg = PERIP_CLK_CFG,
	.pclk_sel_mask = UART_CLK_MASK,
};

/* uart0 clock */
static struct clk uart0_clk = {
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = UART0_CLK_ENB,
	.pclk_sel = &uart_pclk_sel,
	.pclk_sel_shift = UART_CLK_SHIFT,
	.recalc = &follow_parent,
};

/* uart1 clock */
static struct clk uart1_clk = {
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = UART1_CLK_ENB,
	.pclk_sel = &uart_pclk_sel,
	.pclk_sel_shift = UART_CLK_SHIFT,
	.recalc = &follow_parent,
};

/* firda configurations */
static struct aux_clk_config firda_synth_config = {
	.synth_reg = FIRDA_CLK_SYNT,
	.masks = &aux_masks,
};

/* firda synth clock */
static struct clk firda_synth_clk = {
	.en_reg = FIRDA_CLK_SYNT,
	.en_reg_bit = AUX_SYNT_ENB,
	.pclk = &pll1_clk,
	.calc_rate = &aux_calc_rate,
	.recalc = &aux_clk_recalc,
	.set_rate = &aux_clk_set_rate,
	.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
	.private_data = &firda_synth_config,
};

/* firda parents */
static struct pclk_info firda_pclk_info[] = {
	{
		.pclk = &firda_synth_clk,
		.pclk_val = AUX_CLK_PLL1_VAL,
	}, {
		.pclk = &pll3_48m_clk,
		.pclk_val = AUX_CLK_PLL3_VAL,
	},
};

/* firda parent select structure */
static struct pclk_sel firda_pclk_sel = {
	.pclk_info = firda_pclk_info,
	.pclk_count = ARRAY_SIZE(firda_pclk_info),
	.pclk_sel_reg = PERIP_CLK_CFG,
	.pclk_sel_mask = FIRDA_CLK_MASK,
};

/* firda clock */
static struct clk firda_clk = {
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = FIRDA_CLK_ENB,
	.pclk_sel = &firda_pclk_sel,
	.pclk_sel_shift = FIRDA_CLK_SHIFT,
	.recalc = &follow_parent,
};

/* clcd configurations */
static struct aux_clk_config clcd_synth_config = {
	.synth_reg = CLCD_CLK_SYNT,
	.masks = &aux_masks,
};

/* firda synth clock */
static struct clk clcd_synth_clk = {
	.en_reg = CLCD_CLK_SYNT,
	.en_reg_bit = AUX_SYNT_ENB,
	.pclk = &pll1_clk,
	.calc_rate = &aux_calc_rate,
	.recalc = &aux_clk_recalc,
	.set_rate = &aux_clk_set_rate,
	.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
	.private_data = &clcd_synth_config,
};

/* clcd parents */
static struct pclk_info clcd_pclk_info[] = {
	{
		.pclk = &clcd_synth_clk,
		.pclk_val = AUX_CLK_PLL1_VAL,
	}, {
		.pclk = &pll3_48m_clk,
		.pclk_val = AUX_CLK_PLL3_VAL,
	},
};

/* clcd parent select structure */
static struct pclk_sel clcd_pclk_sel = {
	.pclk_info = clcd_pclk_info,
	.pclk_count = ARRAY_SIZE(clcd_pclk_info),
	.pclk_sel_reg = PERIP_CLK_CFG,
	.pclk_sel_mask = CLCD_CLK_MASK,
};

/* clcd clock */
static struct clk clcd_clk = {
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = CLCD_CLK_ENB,
	.pclk_sel = &clcd_pclk_sel,
	.pclk_sel_shift = CLCD_CLK_SHIFT,
	.recalc = &follow_parent,
};

/* gpt synthesizer masks */
static struct gpt_clk_masks gpt_masks = {
	.mscale_sel_mask = GPT_MSCALE_MASK,
	.mscale_sel_shift = GPT_MSCALE_SHIFT,
	.nscale_sel_mask = GPT_NSCALE_MASK,
	.nscale_sel_shift = GPT_NSCALE_SHIFT,
};

/* gpt rate configuration table, in ascending order of rates */
struct gpt_rate_tbl gpt_rtbl[] = {
	/* For pll1 = 332 MHz */
	{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
	{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
	{.mscale = 1, .nscale = 0}, /* 83 MHz */
};

/* gpt0 synth clk config*/
static struct gpt_clk_config gpt0_synth_config = {
	.synth_reg = PRSC1_CLK_CFG,
	.masks = &gpt_masks,
};

/* gpt synth clock */
static struct clk gpt0_synth_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &pll1_clk,
	.calc_rate = &gpt_calc_rate,
	.recalc = &gpt_clk_recalc,
	.set_rate = &gpt_clk_set_rate,
	.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
	.private_data = &gpt0_synth_config,
};

/* gpt parents */
static struct pclk_info gpt0_pclk_info[] = {
	{
		.pclk = &gpt0_synth_clk,
		.pclk_val = AUX_CLK_PLL1_VAL,
	}, {
		.pclk = &pll3_48m_clk,
		.pclk_val = AUX_CLK_PLL3_VAL,
	},
};

/* gpt parent select structure */
static struct pclk_sel gpt0_pclk_sel = {
	.pclk_info = gpt0_pclk_info,
	.pclk_count = ARRAY_SIZE(gpt0_pclk_info),
	.pclk_sel_reg = PERIP_CLK_CFG,
	.pclk_sel_mask = GPT_CLK_MASK,
};

/* gpt0 ARM1 subsystem timer clock */
static struct clk gpt0_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk_sel = &gpt0_pclk_sel,
	.pclk_sel_shift = GPT0_CLK_SHIFT,
	.recalc = &follow_parent,
};


/* Note: gpt0 and gpt1 share same parent clocks */
/* gpt parent select structure */
static struct pclk_sel gpt1_pclk_sel = {
	.pclk_info = gpt0_pclk_info,
	.pclk_count = ARRAY_SIZE(gpt0_pclk_info),
	.pclk_sel_reg = PERIP_CLK_CFG,
	.pclk_sel_mask = GPT_CLK_MASK,
};

/* gpt1 timer clock */
static struct clk gpt1_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk_sel = &gpt1_pclk_sel,
	.pclk_sel_shift = GPT1_CLK_SHIFT,
	.recalc = &follow_parent,
};

/* gpt2 synth clk config*/
static struct gpt_clk_config gpt2_synth_config = {
	.synth_reg = PRSC2_CLK_CFG,
	.masks = &gpt_masks,
};

/* gpt synth clock */
static struct clk gpt2_synth_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &pll1_clk,
	.calc_rate = &gpt_calc_rate,
	.recalc = &gpt_clk_recalc,
	.set_rate = &gpt_clk_set_rate,
	.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
	.private_data = &gpt2_synth_config,
};

/* gpt parents */
static struct pclk_info gpt2_pclk_info[] = {
	{
		.pclk = &gpt2_synth_clk,
		.pclk_val = AUX_CLK_PLL1_VAL,
	}, {
		.pclk = &pll3_48m_clk,
		.pclk_val = AUX_CLK_PLL3_VAL,
	},
};

/* gpt parent select structure */
static struct pclk_sel gpt2_pclk_sel = {
	.pclk_info = gpt2_pclk_info,
	.pclk_count = ARRAY_SIZE(gpt2_pclk_info),
	.pclk_sel_reg = PERIP_CLK_CFG,
	.pclk_sel_mask = GPT_CLK_MASK,
};

/* gpt2 timer clock */
static struct clk gpt2_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk_sel = &gpt2_pclk_sel,
	.pclk_sel_shift = GPT2_CLK_SHIFT,
	.recalc = &follow_parent,
};

/* gpt3 synth clk config*/
static struct gpt_clk_config gpt3_synth_config = {
	.synth_reg = PRSC3_CLK_CFG,
	.masks = &gpt_masks,
};

/* gpt synth clock */
static struct clk gpt3_synth_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &pll1_clk,
	.calc_rate = &gpt_calc_rate,
	.recalc = &gpt_clk_recalc,
	.set_rate = &gpt_clk_set_rate,
	.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
	.private_data = &gpt3_synth_config,
};

/* gpt parents */
static struct pclk_info gpt3_pclk_info[] = {
	{
		.pclk = &gpt3_synth_clk,
		.pclk_val = AUX_CLK_PLL1_VAL,
	}, {
		.pclk = &pll3_48m_clk,
		.pclk_val = AUX_CLK_PLL3_VAL,
	},
};

/* gpt parent select structure */
static struct pclk_sel gpt3_pclk_sel = {
	.pclk_info = gpt3_pclk_info,
	.pclk_count = ARRAY_SIZE(gpt3_pclk_info),
	.pclk_sel_reg = PERIP_CLK_CFG,
	.pclk_sel_mask = GPT_CLK_MASK,
};

/* gpt3 timer clock */
static struct clk gpt3_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk_sel = &gpt3_pclk_sel,
	.pclk_sel_shift = GPT3_CLK_SHIFT,
	.recalc = &follow_parent,
};

/* clock derived from pll3 clk */
/* usbh0 clock */
static struct clk usbh0_clk = {
	.pclk = &pll3_48m_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = USBH0_CLK_ENB,
	.recalc = &follow_parent,
};

/* usbh1 clock */
static struct clk usbh1_clk = {
	.pclk = &pll3_48m_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = USBH1_CLK_ENB,
	.recalc = &follow_parent,
};

/* usbd clock */
static struct clk usbd_clk = {
	.pclk = &pll3_48m_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = USBD_CLK_ENB,
	.recalc = &follow_parent,
};

/* clock derived from ahb clk */
/* apb masks structure */
static struct bus_clk_masks apb_masks = {
	.mask = HCLK_PCLK_RATIO_MASK,
	.shift = HCLK_PCLK_RATIO_SHIFT,
};

/* apb configuration structure */
static struct bus_clk_config apb_config = {
	.reg = CORE_CLK_CFG,
	.masks = &apb_masks,
};

/* apb clock */
static struct clk apb_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &ahb_clk,
	.calc_rate = &bus_calc_rate,
	.recalc = &bus_clk_recalc,
	.set_rate = &bus_clk_set_rate,
	.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
	.private_data = &apb_config,
};

/* i2c clock */
static struct clk i2c_clk = {
	.pclk = &ahb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = I2C_CLK_ENB,
	.recalc = &follow_parent,
};

/* dma clock */
static struct clk dma_clk = {
	.pclk = &ahb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = DMA_CLK_ENB,
	.recalc = &follow_parent,
};

/* jpeg clock */
static struct clk jpeg_clk = {
	.pclk = &ahb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = JPEG_CLK_ENB,
	.recalc = &follow_parent,
};

/* gmac clock */
static struct clk gmac_clk = {
	.pclk = &ahb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = GMAC_CLK_ENB,
	.recalc = &follow_parent,
};

/* smi clock */
static struct clk smi_clk = {
	.pclk = &ahb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = SMI_CLK_ENB,
	.recalc = &follow_parent,
};

/* fsmc clock */
static struct clk fsmc_clk = {
	.pclk = &ahb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = FSMC_CLK_ENB,
	.recalc = &follow_parent,
};

/* clock derived from apb clk */
/* adc clock */
static struct clk adc_clk = {
	.pclk = &apb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = ADC_CLK_ENB,
	.recalc = &follow_parent,
};

/* ssp0 clock */
static struct clk ssp0_clk = {
	.pclk = &apb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = SSP0_CLK_ENB,
	.recalc = &follow_parent,
};

/* ssp1 clock */
static struct clk ssp1_clk = {
	.pclk = &apb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = SSP1_CLK_ENB,
	.recalc = &follow_parent,
};

/* ssp2 clock */
static struct clk ssp2_clk = {
	.pclk = &apb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = SSP2_CLK_ENB,
	.recalc = &follow_parent,
};

/* gpio0 ARM subsystem clock */
static struct clk gpio0_clk = {
	.flags = ALWAYS_ENABLED,
	.pclk = &apb_clk,
	.recalc = &follow_parent,
};

/* gpio1 clock */
static struct clk gpio1_clk = {
	.pclk = &apb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = GPIO1_CLK_ENB,
	.recalc = &follow_parent,
};

/* gpio2 clock */
static struct clk gpio2_clk = {
	.pclk = &apb_clk,
	.en_reg = PERIP1_CLK_ENB,
	.en_reg_bit = GPIO2_CLK_ENB,
	.recalc = &follow_parent,
};

static struct clk dummy_apb_pclk;

/* array of all spear 6xx clock lookups */
static struct clk_lookup spear_clk_lookups[] = {
	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
	/* root clks */
	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
	{ .con_id = "osc_30m_clk",	.clk = &osc_30m_clk},
	/* clock derived from 32 KHz os		 clk */
	{ .dev_id = "rtc-spear",	.clk = &rtc_clk},
	/* clock derived from 30 MHz os		 clk */
	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
	{ .dev_id = "wdt",		.clk = &wdt_clk},
	/* clock derived from pll1 clk */
	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
	{ .con_id = "uart_synth_clk",	.clk = &uart_synth_clk},
	{ .con_id = "firda_synth_clk",	.clk = &firda_synth_clk},
	{ .con_id = "clcd_synth_clk",	.clk = &clcd_synth_clk},
	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
	{ .dev_id = "firda",		.clk = &firda_clk},
	{ .dev_id = "clcd",		.clk = &clcd_clk},
	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
	{ .dev_id = "gpt3",		.clk = &gpt3_clk},
	/* clock derived from pll3 clk */
	{ .dev_id = "designware_udc",	.clk = &usbd_clk},
	{ .con_id = "usbh.0_clk",	.clk = &usbh0_clk},
	{ .con_id = "usbh.1_clk",	.clk = &usbh1_clk},
	/* clock derived from ahb clk */
	{ .con_id = "apb_clk",		.clk = &apb_clk},
	{ .dev_id = "d0200000.i2c",	.clk = &i2c_clk},
	{ .dev_id = "dma",		.clk = &dma_clk},
	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
	{ .dev_id = "gmac",		.clk = &gmac_clk},
	{ .dev_id = "smi",		.clk = &smi_clk},
	{ .dev_id = "fsmc-nand",	.clk = &fsmc_clk},
	/* clock derived from apb clk */
	{ .dev_id = "adc",		.clk = &adc_clk},
	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
	{ .dev_id = "f0100000.gpio",	.clk = &gpio0_clk},
	{ .dev_id = "fc980000.gpio",	.clk = &gpio1_clk},
	{ .dev_id = "d8100000.gpio",	.clk = &gpio2_clk},
};

void __init spear6xx_clk_init(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
		clk_register(&spear_clk_lookups[i]);

	clk_init();
}
Commit	Line	Data
8c0236fc VK	1	/*
	2	* arch/arm/mach-spear6xx/clock.c
	3	*
	4	* SPEAr6xx machines clock framework source file
	5	*
	6	* Copyright (C) 2009 ST Microelectronics
	7	* Viresh Kumar<viresh.kumar@st.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include <linux/init.h>
6f6f6a70	15	#include <linux/io.h>
8c0236fc	16	#include <linux/kernel.h>
8c0236fc	17	#include <plat/clock.h>
410782be	18	#include <mach/misc_regs.h>
8c0236fc VK	19
	20	/* root clks */
	21	/* 32 KHz oscillator clock */
	22	static struct clk osc_32k_clk = {
	23	.flags = ALWAYS_ENABLED,
	24	.rate = 32000,
	25	};
	26
	27	/* 30 MHz oscillator clock */
	28	static struct clk osc_30m_clk = {
	29	.flags = ALWAYS_ENABLED,
	30	.rate = 30000000,
	31	};
	32
	33	/* clock derived from 32 KHz osc clk */
	34	/* rtc clock */
	35	static struct clk rtc_clk = {
	36	.pclk = &osc_32k_clk,
	37	.en_reg = PERIP1_CLK_ENB,
	38	.en_reg_bit = RTC_CLK_ENB,
	39	.recalc = &follow_parent,
	40	};
	41
	42	/* clock derived from 30 MHz osc clk */
cf285434 VK	43	/* pll masks structure */
	44	static struct pll_clk_masks pll1_masks = {
	45	.mode_mask = PLL_MODE_MASK,
	46	.mode_shift = PLL_MODE_SHIFT,
	47	.norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
	48	.norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
	49	.dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
	50	.dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
	51	.div_p_mask = PLL_DIV_P_MASK,
	52	.div_p_shift = PLL_DIV_P_SHIFT,
	53	.div_n_mask = PLL_DIV_N_MASK,
	54	.div_n_shift = PLL_DIV_N_SHIFT,
	55	};
	56
8c0236fc VK	57	/* pll1 configuration structure */
	58	static struct pll_clk_config pll1_config = {
	59	.mode_reg = PLL1_CTR,
	60	.cfg_reg = PLL1_FRQ,
cf285434	61	.masks = &pll1_masks,
8c0236fc VK	62	};
8c0236fc VK	63
af89fd81 VK	64	/* pll rate configuration table, in ascending order of rates */
	65	struct pll_rate_tbl pll_rtbl[] = {
	66	{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
	67	{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
	68	};
	69
8c0236fc VK	70	/* PLL1 clock */
8c0236fc VK	71	static struct clk pll1_clk = {
af89fd81	72	.flags = ENABLED_ON_INIT,
8c0236fc VK	73	.pclk = &osc_30m_clk,
	74	.en_reg = PLL1_CTR,
	75	.en_reg_bit = PLL_ENABLE,
af89fd81	76	.calc_rate = &pll_calc_rate,
cf285434	77	.recalc = &pll_clk_recalc,
af89fd81 VK	78	.set_rate = &pll_clk_set_rate,
af89fd81 VK	79	.rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
8c0236fc VK	80	.private_data = &pll1_config,
	81	};
	82
	83	/* PLL3 48 MHz clock */
	84	static struct clk pll3_48m_clk = {
	85	.flags = ALWAYS_ENABLED,
	86	.pclk = &osc_30m_clk,
	87	.rate = 48000000,
	88	};
	89
	90	/* watch dog timer clock */
	91	static struct clk wdt_clk = {
	92	.flags = ALWAYS_ENABLED,
	93	.pclk = &osc_30m_clk,
	94	.recalc = &follow_parent,
	95	};
	96
	97	/* clock derived from pll1 clk */
	98	/* cpu clock */
	99	static struct clk cpu_clk = {
	100	.flags = ALWAYS_ENABLED,
	101	.pclk = &pll1_clk,
	102	.recalc = &follow_parent,
	103	};
	104
cf285434 VK	105	/* ahb masks structure */
	106	static struct bus_clk_masks ahb_masks = {
	107	.mask = PLL_HCLK_RATIO_MASK,
	108	.shift = PLL_HCLK_RATIO_SHIFT,
	109	};
	110
8c0236fc VK	111	/* ahb configuration structure */
	112	static struct bus_clk_config ahb_config = {
	113	.reg = CORE_CLK_CFG,
cf285434	114	.masks = &ahb_masks,
8c0236fc VK	115	};
8c0236fc VK	116
af89fd81 VK	117	/* ahb rate configuration table, in ascending order of rates */
	118	struct bus_rate_tbl bus_rtbl[] = {
	119	{.div = 3}, /* == parent divided by 4 */
	120	{.div = 2}, /* == parent divided by 3 */
	121	{.div = 1}, /* == parent divided by 2 */
	122	{.div = 0}, /* == parent divided by 1 */
	123	};
	124
8c0236fc VK	125	/* ahb clock */
	126	static struct clk ahb_clk = {
	127	.flags = ALWAYS_ENABLED,
	128	.pclk = &pll1_clk,
af89fd81	129	.calc_rate = &bus_calc_rate,
8c0236fc	130	.recalc = &bus_clk_recalc,
af89fd81 VK	131	.set_rate = &bus_clk_set_rate,
af89fd81 VK	132	.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
8c0236fc VK	133	.private_data = &ahb_config,
	134	};
	135
cf285434 VK	136	/* auxiliary synthesizers masks */
	137	static struct aux_clk_masks aux_masks = {
	138	.eq_sel_mask = AUX_EQ_SEL_MASK,
	139	.eq_sel_shift = AUX_EQ_SEL_SHIFT,
	140	.eq1_mask = AUX_EQ1_SEL,
	141	.eq2_mask = AUX_EQ2_SEL,
	142	.xscale_sel_mask = AUX_XSCALE_MASK,
	143	.xscale_sel_shift = AUX_XSCALE_SHIFT,
	144	.yscale_sel_mask = AUX_YSCALE_MASK,
	145	.yscale_sel_shift = AUX_YSCALE_SHIFT,
	146	};
	147
8c0236fc	148	/* uart configurations */
af89fd81	149	static struct aux_clk_config uart_synth_config = {
8c0236fc	150	.synth_reg = UART_CLK_SYNT,
cf285434	151	.masks = &aux_masks,
8c0236fc VK	152	};
8c0236fc VK	153
af89fd81 VK	154	/* aux rate configuration table, in ascending order of rates */
	155	struct aux_rate_tbl aux_rtbl[] = {
	156	/* For PLL1 = 332 MHz */
	157	{.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
	158	{.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
	159	{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
	160	};
	161
	162	/* uart synth clock */
	163	static struct clk uart_synth_clk = {
	164	.en_reg = UART_CLK_SYNT,
	165	.en_reg_bit = AUX_SYNT_ENB,
	166	.pclk = &pll1_clk,
	167	.calc_rate = &aux_calc_rate,
	168	.recalc = &aux_clk_recalc,
	169	.set_rate = &aux_clk_set_rate,
	170	.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
	171	.private_data = &uart_synth_config,
	172	};
	173
	174	/* uart parents */
	175	static struct pclk_info uart_pclk_info[] = {
	176	{
	177	.pclk = &uart_synth_clk,
	178	.pclk_val = AUX_CLK_PLL1_VAL,
	179	}, {
	180	.pclk = &pll3_48m_clk,
	181	.pclk_val = AUX_CLK_PLL3_VAL,
	182	},
	183	};
	184
	185	/* uart parent select structure */
	186	static struct pclk_sel uart_pclk_sel = {
	187	.pclk_info = uart_pclk_info,
	188	.pclk_count = ARRAY_SIZE(uart_pclk_info),
	189	.pclk_sel_reg = PERIP_CLK_CFG,
	190	.pclk_sel_mask = UART_CLK_MASK,
	191	};
	192
8c0236fc VK	193	/* uart0 clock */
	194	static struct clk uart0_clk = {
	195	.en_reg = PERIP1_CLK_ENB,
	196	.en_reg_bit = UART0_CLK_ENB,
	197	.pclk_sel = &uart_pclk_sel,
	198	.pclk_sel_shift = UART_CLK_SHIFT,
af89fd81	199	.recalc = &follow_parent,
8c0236fc VK	200	};
	201
	202	/* uart1 clock */
	203	static struct clk uart1_clk = {
	204	.en_reg = PERIP1_CLK_ENB,
	205	.en_reg_bit = UART1_CLK_ENB,
	206	.pclk_sel = &uart_pclk_sel,
	207	.pclk_sel_shift = UART_CLK_SHIFT,
af89fd81	208	.recalc = &follow_parent,
8c0236fc VK	209	};
	210
	211	/* firda configurations */
af89fd81	212	static struct aux_clk_config firda_synth_config = {
8c0236fc	213	.synth_reg = FIRDA_CLK_SYNT,
cf285434	214	.masks = &aux_masks,
8c0236fc VK	215	};
8c0236fc VK	216
af89fd81 VK	217	/* firda synth clock */
	218	static struct clk firda_synth_clk = {
	219	.en_reg = FIRDA_CLK_SYNT,
	220	.en_reg_bit = AUX_SYNT_ENB,
	221	.pclk = &pll1_clk,
	222	.calc_rate = &aux_calc_rate,
	223	.recalc = &aux_clk_recalc,
	224	.set_rate = &aux_clk_set_rate,
	225	.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
	226	.private_data = &firda_synth_config,
	227	};
	228
8c0236fc VK	229	/* firda parents */
	230	static struct pclk_info firda_pclk_info[] = {
	231	{
af89fd81 VK	232	.pclk = &firda_synth_clk,
af89fd81 VK	233	.pclk_val = AUX_CLK_PLL1_VAL,
8c0236fc VK	234	}, {
8c0236fc VK	235	.pclk = &pll3_48m_clk,
af89fd81	236	.pclk_val = AUX_CLK_PLL3_VAL,
8c0236fc VK	237	},
	238	};
	239
	240	/* firda parent select structure */
	241	static struct pclk_sel firda_pclk_sel = {
	242	.pclk_info = firda_pclk_info,
	243	.pclk_count = ARRAY_SIZE(firda_pclk_info),
	244	.pclk_sel_reg = PERIP_CLK_CFG,
	245	.pclk_sel_mask = FIRDA_CLK_MASK,
	246	};
	247
	248	/* firda clock */
	249	static struct clk firda_clk = {
	250	.en_reg = PERIP1_CLK_ENB,
	251	.en_reg_bit = FIRDA_CLK_ENB,
	252	.pclk_sel = &firda_pclk_sel,
	253	.pclk_sel_shift = FIRDA_CLK_SHIFT,
af89fd81	254	.recalc = &follow_parent,
8c0236fc VK	255	};
	256
	257	/* clcd configurations */
af89fd81	258	static struct aux_clk_config clcd_synth_config = {
8c0236fc	259	.synth_reg = CLCD_CLK_SYNT,
cf285434	260	.masks = &aux_masks,
8c0236fc VK	261	};
8c0236fc VK	262
af89fd81 VK	263	/* firda synth clock */
	264	static struct clk clcd_synth_clk = {
	265	.en_reg = CLCD_CLK_SYNT,
	266	.en_reg_bit = AUX_SYNT_ENB,
	267	.pclk = &pll1_clk,
	268	.calc_rate = &aux_calc_rate,
	269	.recalc = &aux_clk_recalc,
	270	.set_rate = &aux_clk_set_rate,
	271	.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
	272	.private_data = &clcd_synth_config,
	273	};
	274
8c0236fc VK	275	/* clcd parents */
	276	static struct pclk_info clcd_pclk_info[] = {
	277	{
af89fd81 VK	278	.pclk = &clcd_synth_clk,
af89fd81 VK	279	.pclk_val = AUX_CLK_PLL1_VAL,
8c0236fc VK	280	}, {
8c0236fc VK	281	.pclk = &pll3_48m_clk,
af89fd81	282	.pclk_val = AUX_CLK_PLL3_VAL,
8c0236fc VK	283	},
	284	};
	285
	286	/* clcd parent select structure */
	287	static struct pclk_sel clcd_pclk_sel = {
	288	.pclk_info = clcd_pclk_info,
	289	.pclk_count = ARRAY_SIZE(clcd_pclk_info),
	290	.pclk_sel_reg = PERIP_CLK_CFG,
	291	.pclk_sel_mask = CLCD_CLK_MASK,
	292	};
	293
	294	/* clcd clock */
	295	static struct clk clcd_clk = {
	296	.en_reg = PERIP1_CLK_ENB,
	297	.en_reg_bit = CLCD_CLK_ENB,
	298	.pclk_sel = &clcd_pclk_sel,
	299	.pclk_sel_shift = CLCD_CLK_SHIFT,
af89fd81	300	.recalc = &follow_parent,
8c0236fc VK	301	};
8c0236fc VK	302
cf285434 VK	303	/* gpt synthesizer masks */
	304	static struct gpt_clk_masks gpt_masks = {
	305	.mscale_sel_mask = GPT_MSCALE_MASK,
	306	.mscale_sel_shift = GPT_MSCALE_SHIFT,
	307	.nscale_sel_mask = GPT_NSCALE_MASK,
	308	.nscale_sel_shift = GPT_NSCALE_SHIFT,
	309	};
	310
af89fd81 VK	311	/* gpt rate configuration table, in ascending order of rates */
	312	struct gpt_rate_tbl gpt_rtbl[] = {
	313	/* For pll1 = 332 MHz */
	314	{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
	315	{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
	316	{.mscale = 1, .nscale = 0}, /* 83 MHz */
	317	};
	318
	319	/* gpt0 synth clk config*/
	320	static struct gpt_clk_config gpt0_synth_config = {
8c0236fc	321	.synth_reg = PRSC1_CLK_CFG,
cf285434	322	.masks = &gpt_masks,
8c0236fc VK	323	};
8c0236fc VK	324
af89fd81 VK	325	/* gpt synth clock */
	326	static struct clk gpt0_synth_clk = {
	327	.flags = ALWAYS_ENABLED,
	328	.pclk = &pll1_clk,
	329	.calc_rate = &gpt_calc_rate,
	330	.recalc = &gpt_clk_recalc,
	331	.set_rate = &gpt_clk_set_rate,
	332	.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
	333	.private_data = &gpt0_synth_config,
	334	};
	335
	336	/* gpt parents */
	337	static struct pclk_info gpt0_pclk_info[] = {
	338	{
	339	.pclk = &gpt0_synth_clk,
	340	.pclk_val = AUX_CLK_PLL1_VAL,
	341	}, {
	342	.pclk = &pll3_48m_clk,
	343	.pclk_val = AUX_CLK_PLL3_VAL,
	344	},
	345	};
	346
	347	/* gpt parent select structure */
	348	static struct pclk_sel gpt0_pclk_sel = {
	349	.pclk_info = gpt0_pclk_info,
	350	.pclk_count = ARRAY_SIZE(gpt0_pclk_info),
	351	.pclk_sel_reg = PERIP_CLK_CFG,
	352	.pclk_sel_mask = GPT_CLK_MASK,
	353	};
	354
8c0236fc VK	355	/* gpt0 ARM1 subsystem timer clock */
	356	static struct clk gpt0_clk = {
	357	.flags = ALWAYS_ENABLED,
af89fd81	358	.pclk_sel = &gpt0_pclk_sel,
8c0236fc	359	.pclk_sel_shift = GPT0_CLK_SHIFT,
af89fd81 VK	360	.recalc = &follow_parent,
	361	};
	362
	363
	364	/* Note: gpt0 and gpt1 share same parent clocks */
	365	/* gpt parent select structure */
	366	static struct pclk_sel gpt1_pclk_sel = {
	367	.pclk_info = gpt0_pclk_info,
	368	.pclk_count = ARRAY_SIZE(gpt0_pclk_info),
	369	.pclk_sel_reg = PERIP_CLK_CFG,
	370	.pclk_sel_mask = GPT_CLK_MASK,
8c0236fc VK	371	};
	372
	373	/* gpt1 timer clock */
	374	static struct clk gpt1_clk = {
	375	.flags = ALWAYS_ENABLED,
af89fd81	376	.pclk_sel = &gpt1_pclk_sel,
8c0236fc	377	.pclk_sel_shift = GPT1_CLK_SHIFT,
af89fd81	378	.recalc = &follow_parent,
8c0236fc VK	379	};
8c0236fc VK	380
af89fd81 VK	381	/* gpt2 synth clk config*/
af89fd81 VK	382	static struct gpt_clk_config gpt2_synth_config = {
8c0236fc	383	.synth_reg = PRSC2_CLK_CFG,
cf285434	384	.masks = &gpt_masks,
8c0236fc VK	385	};
8c0236fc VK	386
af89fd81 VK	387	/* gpt synth clock */
	388	static struct clk gpt2_synth_clk = {
	389	.flags = ALWAYS_ENABLED,
	390	.pclk = &pll1_clk,
	391	.calc_rate = &gpt_calc_rate,
	392	.recalc = &gpt_clk_recalc,
	393	.set_rate = &gpt_clk_set_rate,
	394	.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
	395	.private_data = &gpt2_synth_config,
	396	};
	397
	398	/* gpt parents */
	399	static struct pclk_info gpt2_pclk_info[] = {
	400	{
	401	.pclk = &gpt2_synth_clk,
	402	.pclk_val = AUX_CLK_PLL1_VAL,
	403	}, {
	404	.pclk = &pll3_48m_clk,
	405	.pclk_val = AUX_CLK_PLL3_VAL,
	406	},
	407	};
	408
	409	/* gpt parent select structure */
	410	static struct pclk_sel gpt2_pclk_sel = {
	411	.pclk_info = gpt2_pclk_info,
	412	.pclk_count = ARRAY_SIZE(gpt2_pclk_info),
	413	.pclk_sel_reg = PERIP_CLK_CFG,
	414	.pclk_sel_mask = GPT_CLK_MASK,
	415	};
	416
8c0236fc VK	417	/* gpt2 timer clock */
8c0236fc VK	418	static struct clk gpt2_clk = {
af89fd81 VK	419	.flags = ALWAYS_ENABLED,
af89fd81 VK	420	.pclk_sel = &gpt2_pclk_sel,
8c0236fc	421	.pclk_sel_shift = GPT2_CLK_SHIFT,
af89fd81	422	.recalc = &follow_parent,
8c0236fc VK	423	};
8c0236fc VK	424
af89fd81 VK	425	/* gpt3 synth clk config*/
af89fd81 VK	426	static struct gpt_clk_config gpt3_synth_config = {
8c0236fc	427	.synth_reg = PRSC3_CLK_CFG,
cf285434	428	.masks = &gpt_masks,
8c0236fc VK	429	};
8c0236fc VK	430
af89fd81 VK	431	/* gpt synth clock */
	432	static struct clk gpt3_synth_clk = {
	433	.flags = ALWAYS_ENABLED,
	434	.pclk = &pll1_clk,
	435	.calc_rate = &gpt_calc_rate,
	436	.recalc = &gpt_clk_recalc,
	437	.set_rate = &gpt_clk_set_rate,
	438	.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
	439	.private_data = &gpt3_synth_config,
	440	};
	441
	442	/* gpt parents */
	443	static struct pclk_info gpt3_pclk_info[] = {
	444	{
	445	.pclk = &gpt3_synth_clk,
	446	.pclk_val = AUX_CLK_PLL1_VAL,
	447	}, {
	448	.pclk = &pll3_48m_clk,
	449	.pclk_val = AUX_CLK_PLL3_VAL,
	450	},
	451	};
	452
	453	/* gpt parent select structure */
	454	static struct pclk_sel gpt3_pclk_sel = {
	455	.pclk_info = gpt3_pclk_info,
	456	.pclk_count = ARRAY_SIZE(gpt3_pclk_info),
	457	.pclk_sel_reg = PERIP_CLK_CFG,
	458	.pclk_sel_mask = GPT_CLK_MASK,
	459	};
	460
8c0236fc VK	461	/* gpt3 timer clock */
8c0236fc VK	462	static struct clk gpt3_clk = {
af89fd81 VK	463	.flags = ALWAYS_ENABLED,
af89fd81 VK	464	.pclk_sel = &gpt3_pclk_sel,
8c0236fc	465	.pclk_sel_shift = GPT3_CLK_SHIFT,
af89fd81	466	.recalc = &follow_parent,
8c0236fc VK	467	};
	468
	469	/* clock derived from pll3 clk */
	470	/* usbh0 clock */
	471	static struct clk usbh0_clk = {
	472	.pclk = &pll3_48m_clk,
	473	.en_reg = PERIP1_CLK_ENB,
	474	.en_reg_bit = USBH0_CLK_ENB,
	475	.recalc = &follow_parent,
	476	};
	477
	478	/* usbh1 clock */
	479	static struct clk usbh1_clk = {
	480	.pclk = &pll3_48m_clk,
	481	.en_reg = PERIP1_CLK_ENB,
	482	.en_reg_bit = USBH1_CLK_ENB,
	483	.recalc = &follow_parent,
	484	};
	485
	486	/* usbd clock */
	487	static struct clk usbd_clk = {
	488	.pclk = &pll3_48m_clk,
	489	.en_reg = PERIP1_CLK_ENB,
	490	.en_reg_bit = USBD_CLK_ENB,
	491	.recalc = &follow_parent,
	492	};
	493
	494	/* clock derived from ahb clk */
cf285434 VK	495	/* apb masks structure */
	496	static struct bus_clk_masks apb_masks = {
	497	.mask = HCLK_PCLK_RATIO_MASK,
	498	.shift = HCLK_PCLK_RATIO_SHIFT,
	499	};
	500
8c0236fc VK	501	/* apb configuration structure */
	502	static struct bus_clk_config apb_config = {
	503	.reg = CORE_CLK_CFG,
cf285434	504	.masks = &apb_masks,
8c0236fc VK	505	};
	506
	507	/* apb clock */
	508	static struct clk apb_clk = {
	509	.flags = ALWAYS_ENABLED,
	510	.pclk = &ahb_clk,
af89fd81	511	.calc_rate = &bus_calc_rate,
8c0236fc	512	.recalc = &bus_clk_recalc,
af89fd81 VK	513	.set_rate = &bus_clk_set_rate,
af89fd81 VK	514	.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
8c0236fc VK	515	.private_data = &apb_config,
	516	};
	517
	518	/* i2c clock */
	519	static struct clk i2c_clk = {
	520	.pclk = &ahb_clk,
	521	.en_reg = PERIP1_CLK_ENB,
	522	.en_reg_bit = I2C_CLK_ENB,
	523	.recalc = &follow_parent,
	524	};
	525
	526	/* dma clock */
	527	static struct clk dma_clk = {
	528	.pclk = &ahb_clk,
	529	.en_reg = PERIP1_CLK_ENB,
	530	.en_reg_bit = DMA_CLK_ENB,
	531	.recalc = &follow_parent,
	532	};
	533
	534	/* jpeg clock */
	535	static struct clk jpeg_clk = {
	536	.pclk = &ahb_clk,
	537	.en_reg = PERIP1_CLK_ENB,
	538	.en_reg_bit = JPEG_CLK_ENB,
	539	.recalc = &follow_parent,
	540	};
	541
	542	/* gmac clock */
	543	static struct clk gmac_clk = {
	544	.pclk = &ahb_clk,
	545	.en_reg = PERIP1_CLK_ENB,
	546	.en_reg_bit = GMAC_CLK_ENB,
	547	.recalc = &follow_parent,
	548	};
	549
	550	/* smi clock */
	551	static struct clk smi_clk = {
	552	.pclk = &ahb_clk,
	553	.en_reg = PERIP1_CLK_ENB,
	554	.en_reg_bit = SMI_CLK_ENB,
	555	.recalc = &follow_parent,
	556	};
	557
	558	/* fsmc clock */
	559	static struct clk fsmc_clk = {
	560	.pclk = &ahb_clk,
	561	.en_reg = PERIP1_CLK_ENB,
	562	.en_reg_bit = FSMC_CLK_ENB,
	563	.recalc = &follow_parent,
	564	};
	565
	566	/* clock derived from apb clk */
	567	/* adc clock */
	568	static struct clk adc_clk = {
	569	.pclk = &apb_clk,
	570	.en_reg = PERIP1_CLK_ENB,
	571	.en_reg_bit = ADC_CLK_ENB,
	572	.recalc = &follow_parent,
	573	};
	574
	575	/* ssp0 clock */
	576	static struct clk ssp0_clk = {
	577	.pclk = &apb_clk,
	578	.en_reg = PERIP1_CLK_ENB,
579	.en_reg_bit = SSP0_CLK_ENB,
580	.recalc = &follow_parent,
581	};
582
583	/* ssp1 clock */
584	static struct clk ssp1_clk = {
585	.pclk = &apb_clk,
586	.en_reg = PERIP1_CLK_ENB,
587	.en_reg_bit = SSP1_CLK_ENB,
588	.recalc = &follow_parent,
589	};
590
591	/* ssp2 clock */
592	static struct clk ssp2_clk = {
593	.pclk = &apb_clk,
594	.en_reg = PERIP1_CLK_ENB,
595	.en_reg_bit = SSP2_CLK_ENB,
596	.recalc = &follow_parent,
597	};
598
599	/* gpio0 ARM subsystem clock */
600	static struct clk gpio0_clk = {
601	.flags = ALWAYS_ENABLED,
602	.pclk = &apb_clk,
603	.recalc = &follow_parent,
604	};
605
606	/* gpio1 clock */
607	static struct clk gpio1_clk = {
608	.pclk = &apb_clk,
609	.en_reg = PERIP1_CLK_ENB,
610	.en_reg_bit = GPIO1_CLK_ENB,
611	.recalc = &follow_parent,
612	};
613
614	/* gpio2 clock */
615	static struct clk gpio2_clk = {
616	.pclk = &apb_clk,
617	.en_reg = PERIP1_CLK_ENB,
618	.en_reg_bit = GPIO2_CLK_ENB,
619	.recalc = &follow_parent,
620	};
621
3126c7bc RK	622	static struct clk dummy_apb_pclk;
3126c7bc RK	623
8c0236fc VK	624	/* array of all spear 6xx clock lookups */
8c0236fc VK	625	static struct clk_lookup spear_clk_lookups[] = {
b5761371	626	{ .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
8c0236fc VK	627	/* root clks */
	628	{ .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
	629	{ .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
	630	/* clock derived from 32 KHz os clk */
af89fd81	631	{ .dev_id = "rtc-spear", .clk = &rtc_clk},
8c0236fc VK	632	/* clock derived from 30 MHz os clk */
	633	{ .con_id = "pll1_clk", .clk = &pll1_clk},
	634	{ .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
	635	{ .dev_id = "wdt", .clk = &wdt_clk},
	636	/* clock derived from pll1 clk */
	637	{ .con_id = "cpu_clk", .clk = &cpu_clk},
	638	{ .con_id = "ahb_clk", .clk = &ahb_clk},
af89fd81 VK	639	{ .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
	640	{ .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
	641	{ .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
	642	{ .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
	643	{ .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
	644	{ .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk},
9652e8bd SR	645	{ .dev_id = "d0000000.serial", .clk = &uart0_clk},
9652e8bd SR	646	{ .dev_id = "d0080000.serial", .clk = &uart1_clk},
8c0236fc VK	647	{ .dev_id = "firda", .clk = &firda_clk},
	648	{ .dev_id = "clcd", .clk = &clcd_clk},
	649	{ .dev_id = "gpt0", .clk = &gpt0_clk},
	650	{ .dev_id = "gpt1", .clk = &gpt1_clk},
	651	{ .dev_id = "gpt2", .clk = &gpt2_clk},
	652	{ .dev_id = "gpt3", .clk = &gpt3_clk},
	653	/* clock derived from pll3 clk */
b5761371	654	{ .dev_id = "designware_udc", .clk = &usbd_clk},
af89fd81 VK	655	{ .con_id = "usbh.0_clk", .clk = &usbh0_clk},
af89fd81 VK	656	{ .con_id = "usbh.1_clk", .clk = &usbh1_clk},
8c0236fc VK	657	/* clock derived from ahb clk */
8c0236fc VK	658	{ .con_id = "apb_clk", .clk = &apb_clk},
9652e8bd	659	{ .dev_id = "d0200000.i2c", .clk = &i2c_clk},
8c0236fc VK	660	{ .dev_id = "dma", .clk = &dma_clk},
	661	{ .dev_id = "jpeg", .clk = &jpeg_clk},
	662	{ .dev_id = "gmac", .clk = &gmac_clk},
	663	{ .dev_id = "smi", .clk = &smi_clk},
9652e8bd	664	{ .dev_id = "fsmc-nand", .clk = &fsmc_clk},
8c0236fc VK	665	/* clock derived from apb clk */
8c0236fc VK	666	{ .dev_id = "adc", .clk = &adc_clk},
af89fd81 VK	667	{ .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
	668	{ .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
	669	{ .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
9652e8bd SR	670	{ .dev_id = "f0100000.gpio", .clk = &gpio0_clk},
	671	{ .dev_id = "fc980000.gpio", .clk = &gpio1_clk},
	672	{ .dev_id = "d8100000.gpio", .clk = &gpio2_clk},
8c0236fc VK	673	};
8c0236fc VK	674
b997f6e2	675	void __init spear6xx_clk_init(void)
8c0236fc VK	676	{
	677	int i;
	678
	679	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
	680	clk_register(&spear_clk_lookups[i]);
	681
b997f6e2	682	clk_init();
8c0236fc	683	}