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8e267f3d GL |
1 | /* |
2 | * nVidia Tegra device tree board support | |
3 | * | |
4 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. | |
5 | * Copyright (C) 2010 Google, Inc. | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/serial_8250.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/irqdomain.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_fdt.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/pda_power.h> | |
bab53ce3 | 31 | #include <linux/platform_data/tegra_usb.h> |
8e267f3d GL |
32 | #include <linux/io.h> |
33 | #include <linux/i2c.h> | |
34 | #include <linux/i2c-tegra.h> | |
bab53ce3 | 35 | #include <linux/usb/tegra_usb_phy.h> |
8e267f3d | 36 | |
afed2a26 | 37 | #include <asm/hardware/gic.h> |
8e267f3d GL |
38 | #include <asm/mach-types.h> |
39 | #include <asm/mach/arch.h> | |
40 | #include <asm/mach/time.h> | |
41 | #include <asm/setup.h> | |
42 | ||
8e267f3d | 43 | #include "board.h" |
8e267f3d | 44 | #include "clock.h" |
a1725732 | 45 | #include "common.h" |
2be39c07 | 46 | #include "iomap.h" |
bab53ce3 SW |
47 | |
48 | struct tegra_ehci_platform_data tegra_ehci1_pdata = { | |
49 | .operating_mode = TEGRA_USB_OTG, | |
50 | .power_down_on_bus_suspend = 1, | |
51 | .vbus_gpio = -1, | |
52 | }; | |
53 | ||
54 | struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { | |
55 | .reset_gpio = -1, | |
56 | .clk = "cdev2", | |
57 | }; | |
58 | ||
59 | struct tegra_ehci_platform_data tegra_ehci2_pdata = { | |
60 | .phy_config = &tegra_ehci2_ulpi_phy_config, | |
61 | .operating_mode = TEGRA_USB_HOST, | |
62 | .power_down_on_bus_suspend = 1, | |
63 | .vbus_gpio = -1, | |
64 | }; | |
65 | ||
66 | struct tegra_ehci_platform_data tegra_ehci3_pdata = { | |
67 | .operating_mode = TEGRA_USB_HOST, | |
68 | .power_down_on_bus_suspend = 1, | |
69 | .vbus_gpio = -1, | |
70 | }; | |
8e267f3d | 71 | |
8e267f3d GL |
72 | struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { |
73 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), | |
74 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), | |
75 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), | |
76 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL), | |
77 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL), | |
78 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL), | |
79 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), | |
0bc2ecb6 | 80 | OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), |
896637ac SW |
81 | OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL), |
82 | OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL), | |
83 | OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL), | |
4a53f4e6 | 84 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0", |
8c3ec841 | 85 | &tegra_ehci1_pdata), |
4a53f4e6 | 86 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1", |
8c3ec841 | 87 | &tegra_ehci2_pdata), |
4a53f4e6 | 88 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", |
8c3ec841 | 89 | &tegra_ehci3_pdata), |
9ec97169 | 90 | OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL), |
140fd977 | 91 | OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), |
e245f54a | 92 | OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL), |
ffa05e45 LD |
93 | OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL), |
94 | OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL), | |
95 | OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL), | |
96 | OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL), | |
35de7bfe TR |
97 | OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL), |
98 | OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL), | |
99 | OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL), | |
100 | OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL), | |
101 | OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL), | |
102 | OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL), | |
8e267f3d GL |
103 | {} |
104 | }; | |
105 | ||
106 | static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { | |
107 | /* name parent rate enabled */ | |
37c241ed | 108 | { "uarta", "pll_p", 216000000, true }, |
8e267f3d | 109 | { "uartd", "pll_p", 216000000, true }, |
4a53f4e6 OJ |
110 | { "usbd", "clk_m", 12000000, false }, |
111 | { "usb2", "clk_m", 12000000, false }, | |
112 | { "usb3", "clk_m", 12000000, false }, | |
586187e2 SW |
113 | { "pll_a", "pll_p_out1", 56448000, true }, |
114 | { "pll_a_out0", "pll_a", 11289600, true }, | |
115 | { "cdev1", NULL, 0, true }, | |
25804d81 | 116 | { "blink", "clk_32k", 32768, true }, |
586187e2 SW |
117 | { "i2s1", "pll_a_out0", 11289600, false}, |
118 | { "i2s2", "pll_a_out0", 11289600, false}, | |
25804d81 WN |
119 | { "sdmmc1", "pll_p", 48000000, false}, |
120 | { "sdmmc3", "pll_p", 48000000, false}, | |
121 | { "sdmmc4", "pll_p", 48000000, false}, | |
e245f54a | 122 | { "spi", "pll_p", 20000000, false }, |
ffa05e45 LD |
123 | { "sbc1", "pll_p", 100000000, false }, |
124 | { "sbc2", "pll_p", 100000000, false }, | |
125 | { "sbc3", "pll_p", 100000000, false }, | |
126 | { "sbc4", "pll_p", 100000000, false }, | |
35de7bfe TR |
127 | { "host1x", "pll_c", 150000000, false }, |
128 | { "disp1", "pll_p", 600000000, false }, | |
129 | { "disp2", "pll_p", 600000000, false }, | |
8e267f3d GL |
130 | { NULL, NULL, 0, 0}, |
131 | }; | |
132 | ||
8e267f3d GL |
133 | static void __init tegra_dt_init(void) |
134 | { | |
8e267f3d GL |
135 | tegra_clk_init_from_table(tegra_dt_clk_init_table); |
136 | ||
a58116f3 SW |
137 | /* |
138 | * Finished with the static registrations now; fill in the missing | |
139 | * devices | |
140 | */ | |
2553dcc6 | 141 | of_platform_populate(NULL, of_default_bus_match_table, |
a58116f3 | 142 | tegra20_auxdata_lookup, NULL); |
8e267f3d GL |
143 | } |
144 | ||
c554dee3 SW |
145 | static void __init trimslice_init(void) |
146 | { | |
be6a9194 | 147 | #ifdef CONFIG_TEGRA_PCI |
c554dee3 SW |
148 | int ret; |
149 | ||
150 | ret = tegra_pcie_init(true, true); | |
151 | if (ret) | |
152 | pr_err("tegra_pci_init() failed: %d\n", ret); | |
c554dee3 | 153 | #endif |
be6a9194 | 154 | } |
c554dee3 | 155 | |
a12c0efc SW |
156 | static void __init harmony_init(void) |
157 | { | |
3cc404de | 158 | #ifdef CONFIG_TEGRA_PCI |
a12c0efc SW |
159 | int ret; |
160 | ||
a12c0efc SW |
161 | ret = harmony_pcie_init(); |
162 | if (ret) | |
163 | pr_err("harmony_pcie_init() failed: %d\n", ret); | |
a12c0efc | 164 | #endif |
bb25af81 | 165 | } |
a12c0efc | 166 | |
b64a02c6 SW |
167 | static void __init paz00_init(void) |
168 | { | |
169 | tegra_paz00_wifikill_init(); | |
170 | } | |
b64a02c6 | 171 | |
c554dee3 SW |
172 | static struct { |
173 | char *machine; | |
174 | void (*init)(void); | |
175 | } board_init_funcs[] = { | |
c554dee3 | 176 | { "compulab,trimslice", trimslice_init }, |
a12c0efc | 177 | { "nvidia,harmony", harmony_init }, |
b64a02c6 | 178 | { "compal,paz00", paz00_init }, |
c554dee3 SW |
179 | }; |
180 | ||
181 | static void __init tegra_dt_init_late(void) | |
182 | { | |
183 | int i; | |
184 | ||
185 | tegra_init_late(); | |
186 | ||
187 | for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { | |
188 | if (of_machine_is_compatible(board_init_funcs[i].machine)) { | |
189 | board_init_funcs[i].init(); | |
190 | break; | |
191 | } | |
192 | } | |
193 | } | |
194 | ||
c37c07dd | 195 | static const char *tegra20_dt_board_compat[] = { |
c5444f39 | 196 | "nvidia,tegra20", |
8e267f3d GL |
197 | NULL |
198 | }; | |
199 | ||
c37c07dd | 200 | DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") |
8e267f3d | 201 | .map_io = tegra_map_common_io, |
a1725732 | 202 | .smp = smp_ops(tegra_smp_ops), |
c37c07dd | 203 | .init_early = tegra20_init_early, |
0d4f7479 | 204 | .init_irq = tegra_dt_init_irq, |
afed2a26 | 205 | .handle_irq = gic_handle_irq, |
6bb27d73 | 206 | .init_time = tegra_init_timer, |
8e267f3d | 207 | .init_machine = tegra_dt_init, |
c554dee3 | 208 | .init_late = tegra_dt_init_late, |
abea3f2c | 209 | .restart = tegra_assert_system_reset, |
c37c07dd | 210 | .dt_compat = tegra20_dt_board_compat, |
8e267f3d | 211 | MACHINE_END |