[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-tegra / cpu-tegra.c

/*
 * arch/arm/mach-tegra/cpu-tegra.c
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *	Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/suspend.h>

/* Frequency table index must be sequential starting at 0 */
static struct cpufreq_frequency_table freq_table[] = {
	{ 0, 216000 },
	{ 1, 312000 },
	{ 2, 456000 },
	{ 3, 608000 },
	{ 4, 760000 },
	{ 5, 816000 },
	{ 6, 912000 },
	{ 7, 1000000 },
	{ 8, CPUFREQ_TABLE_END },
};

#define NUM_CPUS	2

static struct clk *cpu_clk;
static struct clk *pll_x_clk;
static struct clk *pll_p_clk;
static struct clk *emc_clk;

static unsigned long target_cpu_speed[NUM_CPUS];
static DEFINE_MUTEX(tegra_cpu_lock);
static bool is_suspended;

static int tegra_verify_speed(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, freq_table);
}

static unsigned int tegra_getspeed(unsigned int cpu)
{
	unsigned long rate;

	if (cpu >= NUM_CPUS)
		return 0;

	rate = clk_get_rate(cpu_clk) / 1000;
	return rate;
}

static int tegra_cpu_clk_set_rate(unsigned long rate)
{
	int ret;

	/*
	 * Take an extra reference to the main pll so it doesn't turn
	 * off when we move the cpu off of it
	 */
	clk_prepare_enable(pll_x_clk);

	ret = clk_set_parent(cpu_clk, pll_p_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_p\n");
		goto out;
	}

	if (rate == clk_get_rate(pll_p_clk))
		goto out;

	ret = clk_set_rate(pll_x_clk, rate);
	if (ret) {
		pr_err("Failed to change pll_x to %lu\n", rate);
		goto out;
	}

	ret = clk_set_parent(cpu_clk, pll_x_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_x\n");
		goto out;
	}

out:
	clk_disable_unprepare(pll_x_clk);
	return ret;
}

static int tegra_update_cpu_speed(unsigned long rate)
{
	int ret = 0;
	struct cpufreq_freqs freqs;

	freqs.old = tegra_getspeed(0);
	freqs.new = rate;

	if (freqs.old == freqs.new)
		return ret;

	/*
	 * Vote on memory bus frequency based on cpu frequency
	 * This sets the minimum frequency, display or avp may request higher
	 */
	if (rate >= 816000)
		clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	else if (rate >= 456000)
		clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	else
		clk_set_rate(emc_clk, 100000000);  /* emc 50Mhz */

	for_each_online_cpu(freqs.cpu)
		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);

#ifdef CONFIG_CPU_FREQ_DEBUG
	printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
	       freqs.old, freqs.new);
#endif

	ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
	if (ret) {
		pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
			freqs.new);
		return ret;
	}

	for_each_online_cpu(freqs.cpu)
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);

	return 0;
}

static unsigned long tegra_cpu_highest_speed(void)
{
	unsigned long rate = 0;
	int i;

	for_each_online_cpu(i)
		rate = max(rate, target_cpu_speed[i]);
	return rate;
}

static int tegra_target(struct cpufreq_policy *policy,
		       unsigned int target_freq,
		       unsigned int relation)
{
	unsigned int idx;
	unsigned int freq;
	int ret = 0;

	mutex_lock(&tegra_cpu_lock);

	if (is_suspended) {
		ret = -EBUSY;
		goto out;
	}

	cpufreq_frequency_table_target(policy, freq_table, target_freq,
		relation, &idx);

	freq = freq_table[idx].frequency;

	target_cpu_speed[policy->cpu] = freq;

	ret = tegra_update_cpu_speed(tegra_cpu_highest_speed());

out:
	mutex_unlock(&tegra_cpu_lock);
	return ret;
}

static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
	void *dummy)
{
	mutex_lock(&tegra_cpu_lock);
	if (event == PM_SUSPEND_PREPARE) {
		is_suspended = true;
		pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
			freq_table[0].frequency);
		tegra_update_cpu_speed(freq_table[0].frequency);
	} else if (event == PM_POST_SUSPEND) {
		is_suspended = false;
	}
	mutex_unlock(&tegra_cpu_lock);

	return NOTIFY_OK;
}

static struct notifier_block tegra_cpu_pm_notifier = {
	.notifier_call = tegra_pm_notify,
};

static int tegra_cpu_init(struct cpufreq_policy *policy)
{
	if (policy->cpu >= NUM_CPUS)
		return -EINVAL;

	cpu_clk = clk_get_sys(NULL, "cpu");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	pll_x_clk = clk_get_sys(NULL, "pll_x");
	if (IS_ERR(pll_x_clk))
		return PTR_ERR(pll_x_clk);

	pll_p_clk = clk_get_sys(NULL, "pll_p");
	if (IS_ERR(pll_p_clk))
		return PTR_ERR(pll_p_clk);

	emc_clk = clk_get_sys("cpu", "emc");
	if (IS_ERR(emc_clk)) {
		clk_put(cpu_clk);
		return PTR_ERR(emc_clk);
	}

	clk_prepare_enable(emc_clk);
	clk_prepare_enable(cpu_clk);

	cpufreq_frequency_table_cpuinfo(policy, freq_table);
	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
	policy->cur = tegra_getspeed(policy->cpu);
	target_cpu_speed[policy->cpu] = policy->cur;

	/* FIXME: what's the actual transition time? */
	policy->cpuinfo.transition_latency = 300 * 1000;

	policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
	cpumask_copy(policy->related_cpus, cpu_possible_mask);

	if (policy->cpu == 0)
		register_pm_notifier(&tegra_cpu_pm_notifier);

	return 0;
}

static int tegra_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_cpuinfo(policy, freq_table);
	clk_disable_unprepare(emc_clk);
	clk_put(emc_clk);
	clk_put(cpu_clk);
	return 0;
}

static struct freq_attr *tegra_cpufreq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver tegra_cpufreq_driver = {
	.verify		= tegra_verify_speed,
	.target		= tegra_target,
	.get		= tegra_getspeed,
	.init		= tegra_cpu_init,
	.exit		= tegra_cpu_exit,
	.name		= "tegra",
	.attr		= tegra_cpufreq_attr,
};

static int __init tegra_cpufreq_init(void)
{
	return cpufreq_register_driver(&tegra_cpufreq_driver);
}

static void __exit tegra_cpufreq_exit(void)
{
        cpufreq_unregister_driver(&tegra_cpufreq_driver);
}


MODULE_AUTHOR("Colin Cross <ccross@android.com>");
MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
MODULE_LICENSE("GPL");
module_init(tegra_cpufreq_init);
module_exit(tegra_cpufreq_exit);
Commit	Line	Data
7056d423 CC	1	/*
	2	* arch/arm/mach-tegra/cpu-tegra.c
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	*
	6	* Author:
	7	* Colin Cross <ccross@google.com>
	8	* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
	9	*
	10	* This software is licensed under the terms of the GNU General Public
	11	* License version 2, as published by the Free Software Foundation, and
	12	* may be copied, distributed, and modified under those terms.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	*/
	20
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/types.h>
	24	#include <linux/sched.h>
	25	#include <linux/cpufreq.h>
	26	#include <linux/delay.h>
	27	#include <linux/init.h>
	28	#include <linux/err.h>
	29	#include <linux/clk.h>
	30	#include <linux/io.h>
1eb2ecf1	31	#include <linux/suspend.h>
7056d423	32
7056d423 CC	33	/* Frequency table index must be sequential starting at 0 */
7056d423 CC	34	static struct cpufreq_frequency_table freq_table[] = {
1eb2ecf1 CC	35	{ 0, 216000 },
	36	{ 1, 312000 },
	37	{ 2, 456000 },
	38	{ 3, 608000 },
	39	{ 4, 760000 },
	40	{ 5, 816000 },
	41	{ 6, 912000 },
	42	{ 7, 1000000 },
	43	{ 8, CPUFREQ_TABLE_END },
7056d423 CC	44	};
	45
	46	#define NUM_CPUS 2
	47
	48	static struct clk *cpu_clk;
ce32ddaa SW	49	static struct clk *pll_x_clk;
ce32ddaa SW	50	static struct clk *pll_p_clk;
7a281284	51	static struct clk *emc_clk;
7056d423 CC	52
7056d423 CC	53	static unsigned long target_cpu_speed[NUM_CPUS];
1eb2ecf1 CC	54	static DEFINE_MUTEX(tegra_cpu_lock);
1eb2ecf1 CC	55	static bool is_suspended;
7056d423	56
6686c733	57	static int tegra_verify_speed(struct cpufreq_policy *policy)
7056d423 CC	58	{
	59	return cpufreq_frequency_table_verify(policy, freq_table);
	60	}
	61
6686c733	62	static unsigned int tegra_getspeed(unsigned int cpu)
7056d423 CC	63	{
	64	unsigned long rate;
	65
	66	if (cpu >= NUM_CPUS)
	67	return 0;
	68
	69	rate = clk_get_rate(cpu_clk) / 1000;
	70	return rate;
	71	}
	72
ce32ddaa SW	73	static int tegra_cpu_clk_set_rate(unsigned long rate)
	74	{
	75	int ret;
	76
	77	/*
	78	* Take an extra reference to the main pll so it doesn't turn
	79	* off when we move the cpu off of it
	80	*/
	81	clk_prepare_enable(pll_x_clk);
	82
	83	ret = clk_set_parent(cpu_clk, pll_p_clk);
	84	if (ret) {
	85	pr_err("Failed to switch cpu to clock pll_p\n");
	86	goto out;
	87	}
	88
	89	if (rate == clk_get_rate(pll_p_clk))
	90	goto out;
	91
	92	ret = clk_set_rate(pll_x_clk, rate);
	93	if (ret) {
	94	pr_err("Failed to change pll_x to %lu\n", rate);
	95	goto out;
	96	}
	97
	98	ret = clk_set_parent(cpu_clk, pll_x_clk);
	99	if (ret) {
	100	pr_err("Failed to switch cpu to clock pll_x\n");
	101	goto out;
	102	}
	103
	104	out:
	105	clk_disable_unprepare(pll_x_clk);
	106	return ret;
	107	}
	108
1eb2ecf1	109	static int tegra_update_cpu_speed(unsigned long rate)
7056d423	110	{
7056d423 CC	111	int ret = 0;
	112	struct cpufreq_freqs freqs;
	113
7056d423 CC	114	freqs.old = tegra_getspeed(0);
	115	freqs.new = rate;
	116
	117	if (freqs.old == freqs.new)
	118	return ret;
	119
7a281284 CC	120	/*
	121	* Vote on memory bus frequency based on cpu frequency
	122	* This sets the minimum frequency, display or avp may request higher
	123	*/
	124	if (rate >= 816000)
	125	clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	126	else if (rate >= 456000)
	127	clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	128	else
	129	clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
	130
7056d423 CC	131	for_each_online_cpu(freqs.cpu)
	132	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	133
	134	#ifdef CONFIG_CPU_FREQ_DEBUG
	135	printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
	136	freqs.old, freqs.new);
	137	#endif
	138
ce32ddaa	139	ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
7056d423 CC	140	if (ret) {
	141	pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
	142	freqs.new);
	143	return ret;
	144	}
	145
	146	for_each_online_cpu(freqs.cpu)
	147	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	148
	149	return 0;
	150	}
	151
1eb2ecf1 CC	152	static unsigned long tegra_cpu_highest_speed(void)
	153	{
	154	unsigned long rate = 0;
	155	int i;
	156
	157	for_each_online_cpu(i)
	158	rate = max(rate, target_cpu_speed[i]);
	159	return rate;
	160	}
	161
7056d423 CC	162	static int tegra_target(struct cpufreq_policy *policy,
	163	unsigned int target_freq,
	164	unsigned int relation)
	165	{
fdb684ac	166	unsigned int idx;
7056d423	167	unsigned int freq;
1eb2ecf1 CC	168	int ret = 0;
	169
	170	mutex_lock(&tegra_cpu_lock);
	171
	172	if (is_suspended) {
	173	ret = -EBUSY;
	174	goto out;
	175	}
7056d423 CC	176
	177	cpufreq_frequency_table_target(policy, freq_table, target_freq,
	178	relation, &idx);
	179
	180	freq = freq_table[idx].frequency;
	181
	182	target_cpu_speed[policy->cpu] = freq;
	183
1eb2ecf1 CC	184	ret = tegra_update_cpu_speed(tegra_cpu_highest_speed());
	185
	186	out:
	187	mutex_unlock(&tegra_cpu_lock);
	188	return ret;
7056d423 CC	189	}
7056d423 CC	190
1eb2ecf1 CC	191	static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
	192	void *dummy)
	193	{
	194	mutex_lock(&tegra_cpu_lock);
	195	if (event == PM_SUSPEND_PREPARE) {
	196	is_suspended = true;
	197	pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
	198	freq_table[0].frequency);
	199	tegra_update_cpu_speed(freq_table[0].frequency);
	200	} else if (event == PM_POST_SUSPEND) {
	201	is_suspended = false;
	202	}
	203	mutex_unlock(&tegra_cpu_lock);
	204
	205	return NOTIFY_OK;
	206	}
	207
	208	static struct notifier_block tegra_cpu_pm_notifier = {
	209	.notifier_call = tegra_pm_notify,
	210	};
	211
7056d423 CC	212	static int tegra_cpu_init(struct cpufreq_policy *policy)
	213	{
	214	if (policy->cpu >= NUM_CPUS)
	215	return -EINVAL;
	216
	217	cpu_clk = clk_get_sys(NULL, "cpu");
	218	if (IS_ERR(cpu_clk))
	219	return PTR_ERR(cpu_clk);
	220
ce32ddaa SW	221	pll_x_clk = clk_get_sys(NULL, "pll_x");
	222	if (IS_ERR(pll_x_clk))
	223	return PTR_ERR(pll_x_clk);
	224
	225	pll_p_clk = clk_get_sys(NULL, "pll_p");
	226	if (IS_ERR(pll_p_clk))
	227	return PTR_ERR(pll_p_clk);
	228
7a281284 CC	229	emc_clk = clk_get_sys("cpu", "emc");
	230	if (IS_ERR(emc_clk)) {
	231	clk_put(cpu_clk);
	232	return PTR_ERR(emc_clk);
	233	}
	234
6a5278d0 PG	235	clk_prepare_enable(emc_clk);
6a5278d0 PG	236	clk_prepare_enable(cpu_clk);
89a5fb84	237
7056d423 CC	238	cpufreq_frequency_table_cpuinfo(policy, freq_table);
	239	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
	240	policy->cur = tegra_getspeed(policy->cpu);
	241	target_cpu_speed[policy->cpu] = policy->cur;
	242
	243	/* FIXME: what's the actual transition time? */
	244	policy->cpuinfo.transition_latency = 300 * 1000;
	245
	246	policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
	247	cpumask_copy(policy->related_cpus, cpu_possible_mask);
	248
1eb2ecf1 CC	249	if (policy->cpu == 0)
	250	register_pm_notifier(&tegra_cpu_pm_notifier);
	251
7056d423 CC	252	return 0;
	253	}
	254
	255	static int tegra_cpu_exit(struct cpufreq_policy *policy)
	256	{
	257	cpufreq_frequency_table_cpuinfo(policy, freq_table);
6a5278d0	258	clk_disable_unprepare(emc_clk);
7a281284	259	clk_put(emc_clk);
7056d423 CC	260	clk_put(cpu_clk);
	261	return 0;
	262	}
	263
	264	static struct freq_attr *tegra_cpufreq_attr[] = {
	265	&cpufreq_freq_attr_scaling_available_freqs,
	266	NULL,
	267	};
	268
	269	static struct cpufreq_driver tegra_cpufreq_driver = {
	270	.verify = tegra_verify_speed,
	271	.target = tegra_target,
	272	.get = tegra_getspeed,
	273	.init = tegra_cpu_init,
	274	.exit = tegra_cpu_exit,
	275	.name = "tegra",
	276	.attr = tegra_cpufreq_attr,
	277	};
	278
	279	static int __init tegra_cpufreq_init(void)
	280	{
	281	return cpufreq_register_driver(&tegra_cpufreq_driver);
	282	}
	283
	284	static void __exit tegra_cpufreq_exit(void)
	285	{
	286	cpufreq_unregister_driver(&tegra_cpufreq_driver);
	287	}
	288
	289
	290	MODULE_AUTHOR("Colin Cross <ccross@android.com>");
	291	MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
	292	MODULE_LICENSE("GPL");
	293	module_init(tegra_cpufreq_init);
	294	module_exit(tegra_cpufreq_exit);