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0b25e25b JL |
1 | /* |
2 | * CPU idle driver for Tegra CPUs | |
3 | * | |
4 | * Copyright (c) 2010-2012, NVIDIA Corporation. | |
5 | * Copyright (c) 2011 Google, Inc. | |
6 | * Author: Colin Cross <ccross@android.com> | |
7 | * Gary King <gking@nvidia.com> | |
8 | * | |
9 | * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/cpuidle.h> | |
5c1350bd JL |
25 | #include <linux/cpu_pm.h> |
26 | #include <linux/clockchips.h> | |
1d328606 | 27 | #include <linux/clk/tegra.h> |
0b25e25b JL |
28 | |
29 | #include <asm/cpuidle.h> | |
5c1350bd JL |
30 | #include <asm/proc-fns.h> |
31 | #include <asm/suspend.h> | |
32 | #include <asm/smp_plat.h> | |
33 | ||
34 | #include "pm.h" | |
35 | #include "sleep.h" | |
1d328606 JL |
36 | #include "iomap.h" |
37 | #include "irq.h" | |
38 | #include "flowctrl.h" | |
5c1350bd JL |
39 | |
40 | #ifdef CONFIG_PM_SLEEP | |
1d328606 JL |
41 | static bool abort_flag; |
42 | static atomic_t abort_barrier; | |
43 | static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, | |
44 | struct cpuidle_driver *drv, | |
45 | int index); | |
14ad7a11 DL |
46 | #define TEGRA20_MAX_STATES 2 |
47 | #else | |
48 | #define TEGRA20_MAX_STATES 1 | |
5c1350bd JL |
49 | #endif |
50 | ||
0b25e25b JL |
51 | static struct cpuidle_driver tegra_idle_driver = { |
52 | .name = "tegra_idle", | |
53 | .owner = THIS_MODULE, | |
14ad7a11 DL |
54 | .states = { |
55 | ARM_CPUIDLE_WFI_STATE_PWR(600), | |
56 | #ifdef CONFIG_PM_SLEEP | |
57 | { | |
58 | .enter = tegra20_idle_lp2_coupled, | |
59 | .exit_latency = 5000, | |
60 | .target_residency = 10000, | |
61 | .power_usage = 0, | |
62 | .flags = CPUIDLE_FLAG_TIME_VALID | | |
63 | CPUIDLE_FLAG_COUPLED, | |
64 | .name = "powered-down", | |
65 | .desc = "CPU power gated", | |
66 | }, | |
67 | #endif | |
68 | }, | |
69 | .state_count = TEGRA20_MAX_STATES, | |
70 | .safe_state_index = 0, | |
0b25e25b JL |
71 | }; |
72 | ||
73 | static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device); | |
74 | ||
5c1350bd | 75 | #ifdef CONFIG_PM_SLEEP |
1d328606 JL |
76 | #ifdef CONFIG_SMP |
77 | static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); | |
78 | ||
79 | static int tegra20_reset_sleeping_cpu_1(void) | |
80 | { | |
81 | int ret = 0; | |
82 | ||
83 | tegra_pen_lock(); | |
84 | ||
85 | if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE) | |
86 | tegra20_cpu_shutdown(1); | |
87 | else | |
88 | ret = -EINVAL; | |
89 | ||
90 | tegra_pen_unlock(); | |
91 | ||
92 | return ret; | |
93 | } | |
94 | ||
95 | static void tegra20_wake_cpu1_from_reset(void) | |
96 | { | |
97 | tegra_pen_lock(); | |
98 | ||
99 | tegra20_cpu_clear_resettable(); | |
100 | ||
101 | /* enable cpu clock on cpu */ | |
102 | tegra_enable_cpu_clock(1); | |
103 | ||
104 | /* take the CPU out of reset */ | |
105 | tegra_cpu_out_of_reset(1); | |
106 | ||
107 | /* unhalt the cpu */ | |
108 | flowctrl_write_cpu_halt(1, 0); | |
109 | ||
110 | tegra_pen_unlock(); | |
111 | } | |
112 | ||
113 | static int tegra20_reset_cpu_1(void) | |
114 | { | |
115 | if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1()) | |
116 | return 0; | |
117 | ||
118 | tegra20_wake_cpu1_from_reset(); | |
119 | return -EBUSY; | |
120 | } | |
121 | #else | |
122 | static inline void tegra20_wake_cpu1_from_reset(void) | |
123 | { | |
124 | } | |
125 | ||
126 | static inline int tegra20_reset_cpu_1(void) | |
127 | { | |
128 | return 0; | |
129 | } | |
130 | #endif | |
131 | ||
132 | static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, | |
133 | struct cpuidle_driver *drv, | |
134 | int index) | |
135 | { | |
136 | struct cpuidle_state *state = &drv->states[index]; | |
137 | u32 cpu_on_time = state->exit_latency; | |
138 | u32 cpu_off_time = state->target_residency - state->exit_latency; | |
139 | ||
140 | while (tegra20_cpu_is_resettable_soon()) | |
141 | cpu_relax(); | |
142 | ||
143 | if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready()) | |
144 | return false; | |
145 | ||
146 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); | |
147 | ||
148 | tegra_idle_lp2_last(cpu_on_time, cpu_off_time); | |
149 | ||
150 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); | |
151 | ||
152 | if (cpu_online(1)) | |
153 | tegra20_wake_cpu1_from_reset(); | |
154 | ||
155 | return true; | |
156 | } | |
157 | ||
5c1350bd JL |
158 | #ifdef CONFIG_SMP |
159 | static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, | |
160 | struct cpuidle_driver *drv, | |
161 | int index) | |
162 | { | |
163 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); | |
164 | ||
165 | cpu_suspend(0, tegra20_sleep_cpu_secondary_finish); | |
166 | ||
167 | tegra20_cpu_clear_resettable(); | |
168 | ||
169 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); | |
170 | ||
171 | return true; | |
172 | } | |
173 | #else | |
174 | static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, | |
175 | struct cpuidle_driver *drv, | |
176 | int index) | |
177 | { | |
178 | return true; | |
179 | } | |
180 | #endif | |
181 | ||
1d328606 JL |
182 | static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, |
183 | struct cpuidle_driver *drv, | |
184 | int index) | |
5c1350bd JL |
185 | { |
186 | u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu; | |
187 | bool entered_lp2 = false; | |
188 | ||
1d328606 JL |
189 | if (tegra_pending_sgi()) |
190 | ACCESS_ONCE(abort_flag) = true; | |
191 | ||
192 | cpuidle_coupled_parallel_barrier(dev, &abort_barrier); | |
193 | ||
194 | if (abort_flag) { | |
195 | cpuidle_coupled_parallel_barrier(dev, &abort_barrier); | |
196 | abort_flag = false; /* clean flag for next coming */ | |
197 | return -EINTR; | |
198 | } | |
199 | ||
5c1350bd JL |
200 | local_fiq_disable(); |
201 | ||
202 | tegra_set_cpu_in_lp2(cpu); | |
203 | cpu_pm_enter(); | |
204 | ||
205 | if (cpu == 0) | |
1d328606 | 206 | entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index); |
5c1350bd JL |
207 | else |
208 | entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); | |
209 | ||
210 | cpu_pm_exit(); | |
211 | tegra_clear_cpu_in_lp2(cpu); | |
212 | ||
213 | local_fiq_enable(); | |
214 | ||
215 | smp_rmb(); | |
216 | ||
217 | return entered_lp2 ? index : 0; | |
218 | } | |
219 | #endif | |
220 | ||
0b25e25b JL |
221 | int __init tegra20_cpuidle_init(void) |
222 | { | |
223 | int ret; | |
224 | unsigned int cpu; | |
225 | struct cpuidle_device *dev; | |
226 | struct cpuidle_driver *drv = &tegra_idle_driver; | |
227 | ||
1d328606 JL |
228 | #ifdef CONFIG_PM_SLEEP |
229 | tegra_tear_down_cpu = tegra20_tear_down_cpu; | |
230 | #endif | |
231 | ||
0b25e25b JL |
232 | ret = cpuidle_register_driver(&tegra_idle_driver); |
233 | if (ret) { | |
234 | pr_err("CPUidle driver registration failed\n"); | |
235 | return ret; | |
236 | } | |
237 | ||
238 | for_each_possible_cpu(cpu) { | |
239 | dev = &per_cpu(tegra_idle_device, cpu); | |
240 | dev->cpu = cpu; | |
1d328606 JL |
241 | #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED |
242 | dev->coupled_cpus = *cpu_possible_mask; | |
243 | #endif | |
0b25e25b | 244 | |
0b25e25b JL |
245 | ret = cpuidle_register_device(dev); |
246 | if (ret) { | |
247 | pr_err("CPU%u: CPUidle device registration failed\n", | |
248 | cpu); | |
249 | return ret; | |
250 | } | |
251 | } | |
252 | return 0; | |
253 | } |