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73625e3e CC |
1 | /* |
2 | * arch/arm/mach-tegra/fuse.c | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@android.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/io.h> | |
34800598 | 22 | #include <linux/export.h> |
73625e3e | 23 | |
73625e3e | 24 | #include "fuse.h" |
2be39c07 | 25 | #include "iomap.h" |
d262f49d | 26 | #include "apbio.h" |
73625e3e CC |
27 | |
28 | #define FUSE_UID_LOW 0x108 | |
29 | #define FUSE_UID_HIGH 0x10c | |
30 | #define FUSE_SKU_INFO 0x110 | |
31 | #define FUSE_SPARE_BIT 0x200 | |
32 | ||
9a1086da OJ |
33 | int tegra_sku_id; |
34 | int tegra_cpu_process_id; | |
35 | int tegra_core_process_id; | |
4c4ad669 | 36 | int tegra_chip_id; |
9a1086da OJ |
37 | enum tegra_revision tegra_revision; |
38 | ||
dee47183 OJ |
39 | /* The BCT to use at boot is specified by board straps that can be read |
40 | * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs. | |
41 | */ | |
42 | int tegra_bct_strapping; | |
43 | ||
44 | #define STRAP_OPT 0x008 | |
45 | #define GMI_AD0 (1 << 4) | |
46 | #define GMI_AD1 (1 << 5) | |
47 | #define RAM_ID_MASK (GMI_AD0 | GMI_AD1) | |
48 | #define RAM_CODE_SHIFT 4 | |
49 | ||
9a1086da OJ |
50 | static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { |
51 | [TEGRA_REVISION_UNKNOWN] = "unknown", | |
52 | [TEGRA_REVISION_A01] = "A01", | |
53 | [TEGRA_REVISION_A02] = "A02", | |
54 | [TEGRA_REVISION_A03] = "A03", | |
55 | [TEGRA_REVISION_A03p] = "A03 prime", | |
56 | [TEGRA_REVISION_A04] = "A04", | |
57 | }; | |
58 | ||
d262f49d | 59 | static inline u32 tegra_fuse_readl(unsigned long offset) |
73625e3e | 60 | { |
d262f49d | 61 | return tegra_apb_readl(TEGRA_FUSE_BASE + offset); |
73625e3e CC |
62 | } |
63 | ||
9a1086da | 64 | static inline bool get_spare_fuse(int bit) |
73625e3e | 65 | { |
9a1086da | 66 | return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); |
73625e3e CC |
67 | } |
68 | ||
35b1498a | 69 | static enum tegra_revision tegra_get_revision(u32 id) |
73625e3e | 70 | { |
9a1086da | 71 | u32 minor_rev = (id >> 16) & 0xf; |
9a1086da OJ |
72 | |
73 | switch (minor_rev) { | |
74 | case 1: | |
75 | return TEGRA_REVISION_A01; | |
76 | case 2: | |
77 | return TEGRA_REVISION_A02; | |
78 | case 3: | |
35b1498a PDS |
79 | if (tegra_chip_id == TEGRA20 && |
80 | (get_spare_fuse(18) || get_spare_fuse(19))) | |
9a1086da OJ |
81 | return TEGRA_REVISION_A03p; |
82 | else | |
83 | return TEGRA_REVISION_A03; | |
84 | case 4: | |
85 | return TEGRA_REVISION_A04; | |
86 | default: | |
87 | return TEGRA_REVISION_UNKNOWN; | |
88 | } | |
73625e3e CC |
89 | } |
90 | ||
91 | void tegra_init_fuse(void) | |
92 | { | |
35b1498a PDS |
93 | u32 id; |
94 | ||
f8e798a9 | 95 | u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); |
73625e3e | 96 | reg |= 1 << 28; |
f8e798a9 | 97 | writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); |
73625e3e | 98 | |
9a1086da OJ |
99 | reg = tegra_fuse_readl(FUSE_SKU_INFO); |
100 | tegra_sku_id = reg & 0xFF; | |
101 | ||
102 | reg = tegra_fuse_readl(FUSE_SPARE_BIT); | |
103 | tegra_cpu_process_id = (reg >> 6) & 3; | |
104 | ||
105 | reg = tegra_fuse_readl(FUSE_SPARE_BIT); | |
106 | tegra_core_process_id = (reg >> 12) & 3; | |
107 | ||
dee47183 OJ |
108 | reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); |
109 | tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; | |
110 | ||
35b1498a PDS |
111 | id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); |
112 | tegra_chip_id = (id >> 8) & 0xff; | |
113 | ||
114 | tegra_revision = tegra_get_revision(id); | |
9a1086da OJ |
115 | |
116 | pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", | |
35b1498a | 117 | tegra_revision_name[tegra_revision], |
9a1086da OJ |
118 | tegra_sku_id, tegra_cpu_process_id, |
119 | tegra_core_process_id); | |
73625e3e CC |
120 | } |
121 | ||
122 | unsigned long long tegra_chip_uid(void) | |
123 | { | |
124 | unsigned long long lo, hi; | |
125 | ||
d262f49d OJ |
126 | lo = tegra_fuse_readl(FUSE_UID_LOW); |
127 | hi = tegra_fuse_readl(FUSE_UID_HIGH); | |
73625e3e CC |
128 | return (hi << 32ull) | lo; |
129 | } | |
e87e06cd | 130 | EXPORT_SYMBOL(tegra_chip_uid); |