[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-tegra / gpio.c

/*
 * arch/arm/mach-tegra/gpio.c
 *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>

#include <linux/io.h>
#include <linux/gpio.h>

#include <mach/iomap.h>
#include <mach/suspend.h>

#define GPIO_BANK(x)		((x) >> 5)
#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
#define GPIO_BIT(x)		((x) & 0x7)

#define GPIO_REG(x)		(IO_TO_VIRT(TEGRA_GPIO_BASE) +	\
				 GPIO_BANK(x) * 0x80 +		\
				 GPIO_PORT(x) * 4)

#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)

#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + 0x800)
#define GPIO_MSK_OE(x)		(GPIO_REG(x) + 0x810)
#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + 0X820)
#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + 0x840)
#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + 0x850)
#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + 0x860)

#define GPIO_INT_LVL_MASK		0x010101
#define GPIO_INT_LVL_EDGE_RISING	0x000101
#define GPIO_INT_LVL_EDGE_FALLING	0x000100
#define GPIO_INT_LVL_EDGE_BOTH		0x010100
#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
#define GPIO_INT_LVL_LEVEL_LOW		0x000000

struct tegra_gpio_bank {
	int bank;
	int irq;
	spinlock_t lvl_lock[4];
#ifdef CONFIG_PM
	u32 cnf[4];
	u32 out[4];
	u32 oe[4];
	u32 int_enb[4];
	u32 int_lvl[4];
#endif
};


static struct tegra_gpio_bank tegra_gpio_banks[] = {
	{.bank = 0, .irq = INT_GPIO1},
	{.bank = 1, .irq = INT_GPIO2},
	{.bank = 2, .irq = INT_GPIO3},
	{.bank = 3, .irq = INT_GPIO4},
	{.bank = 4, .irq = INT_GPIO5},
	{.bank = 5, .irq = INT_GPIO6},
	{.bank = 6, .irq = INT_GPIO7},
};

static int tegra_gpio_compose(int bank, int port, int bit)
{
	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}

static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
	u32 val;

	val = 0x100 << GPIO_BIT(gpio);
	if (value)
		val |= 1 << GPIO_BIT(gpio);
	__raw_writel(val, reg);
}

void tegra_gpio_enable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}

void tegra_gpio_disable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
}

static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}

static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	return 0;
}

static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	tegra_gpio_set(chip, offset, value);
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	return 0;
}


static struct gpio_chip tegra_gpio_chip = {
	.label			= "tegra-gpio",
	.direction_input	= tegra_gpio_direction_input,
	.get			= tegra_gpio_get,
	.direction_output	= tegra_gpio_direction_output,
	.set			= tegra_gpio_set,
	.base			= 0,
	.ngpio			= TEGRA_NR_GPIOS,
};

static void tegra_gpio_irq_ack(struct irq_data *d)
{
	int gpio = d->irq - INT_GPIO_BASE;

	__raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
}

static void tegra_gpio_irq_mask(struct irq_data *d)
{
	int gpio = d->irq - INT_GPIO_BASE;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
}

static void tegra_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = d->irq - INT_GPIO_BASE;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
}

static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	int gpio = d->irq - INT_GPIO_BASE;
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int port = GPIO_PORT(gpio);
	int lvl_type;
	int val;
	unsigned long flags;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_INT_LVL_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
		break;

	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&bank->lvl_lock[port], flags);

	val = __raw_readl(GPIO_INT_LVL(gpio));
	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	val |= lvl_type << GPIO_BIT(gpio);
	__raw_writel(val, GPIO_INT_LVL(gpio));

	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return 0;
}

static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct tegra_gpio_bank *bank;
	int port;
	int pin;
	int unmasked = 0;

	desc->irq_data.chip->irq_ack(&desc->irq_data);

	bank = irq_get_handler_data(irq);

	for (port = 0; port < 4; port++) {
		int gpio = tegra_gpio_compose(bank->bank, port, 0);
		unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
			__raw_readl(GPIO_INT_ENB(gpio));
		u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));

		for_each_set_bit(pin, &sta, 8) {
			__raw_writel(1 << pin, GPIO_INT_CLR(gpio));

			/* if gpio is edge triggered, clear condition
			 * before executing the hander so that we don't
			 * miss edges
			 */
			if (lvl & (0x100 << pin)) {
				unmasked = 1;
				desc->irq_data.chip->irq_unmask(&desc->irq_data);
			}

			generic_handle_irq(gpio_to_irq(gpio + pin));
		}
	}

	if (!unmasked)
		desc->irq_data.chip->irq_unmask(&desc->irq_data);

}

#ifdef CONFIG_PM
void tegra_gpio_resume(void)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);

	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			__raw_writel(bank->cnf[p], GPIO_CNF(gpio));
			__raw_writel(bank->out[p], GPIO_OUT(gpio));
			__raw_writel(bank->oe[p], GPIO_OE(gpio));
			__raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
			__raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
		}
	}

	local_irq_restore(flags);
}

void tegra_gpio_suspend(void)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);
	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
			bank->out[p] = __raw_readl(GPIO_OUT(gpio));
			bank->oe[p] = __raw_readl(GPIO_OE(gpio));
			bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
			bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
		}
	}
	local_irq_restore(flags);
}

static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	return irq_set_irq_wake(bank->irq, enable);
}
#endif

static struct irq_chip tegra_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= tegra_gpio_irq_ack,
	.irq_mask	= tegra_gpio_irq_mask,
	.irq_unmask	= tegra_gpio_irq_unmask,
	.irq_set_type	= tegra_gpio_irq_set_type,
#ifdef CONFIG_PM
	.irq_set_wake	= tegra_gpio_wake_enable,
#endif
};


/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int __init tegra_gpio_init(void)
{
	struct tegra_gpio_bank *bank;
	int i;
	int j;

	for (i = 0; i < 7; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			__raw_writel(0x00, GPIO_INT_ENB(gpio));
		}
	}

	gpiochip_add(&tegra_gpio_chip);

	for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
		bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];

		irq_set_lockdep_class(i, &gpio_lock_class);
		irq_set_chip_data(i, bank);
		irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
		bank = &tegra_gpio_banks[i];

		irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
		irq_set_handler_data(bank->irq, bank);

		for (j = 0; j < 4; j++)
			spin_lock_init(&bank->lvl_lock[j]);
	}

	return 0;
}

postcore_initcall(tegra_gpio_init);

void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
{
	int i;

	for (i = 0; i < num; i++) {
		int gpio = table[i].gpio;

		if (table[i].enable)
			tegra_gpio_enable(gpio);
		else
			tegra_gpio_disable(gpio);
	}
}

#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	int i;
	int j;

	for (i = 0; i < 7; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			seq_printf(s,
				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
				i, j,
				__raw_readl(GPIO_CNF(gpio)),
				__raw_readl(GPIO_OE(gpio)),
				__raw_readl(GPIO_OUT(gpio)),
				__raw_readl(GPIO_IN(gpio)),
				__raw_readl(GPIO_INT_STA(gpio)),
				__raw_readl(GPIO_INT_ENB(gpio)),
				__raw_readl(GPIO_INT_LVL(gpio)));
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, dbg_gpio_show, &inode->i_private);
}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init tegra_gpio_debuginit(void)
{
	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
	return 0;
}
late_initcall(tegra_gpio_debuginit);
#endif
Commit	Line	Data
3c92db9a EG	1	/*
	2	* arch/arm/mach-tegra/gpio.c
	3	*
	4	* Copyright (c) 2010 Google, Inc
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/irq.h>
2e47b8b3	22	#include <linux/interrupt.h>
3c92db9a EG	23
	24	#include <linux/io.h>
	25	#include <linux/gpio.h>
	26
	27	#include <mach/iomap.h>
2ea67fd1	28	#include <mach/suspend.h>
3c92db9a EG	29
	30	#define GPIO_BANK(x) ((x) >> 5)
	31	#define GPIO_PORT(x) (((x) >> 3) & 0x3)
	32	#define GPIO_BIT(x) ((x) & 0x7)
	33
	34	#define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \
	35	GPIO_BANK(x) * 0x80 + \
	36	GPIO_PORT(x) * 4)
	37
	38	#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
	39	#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
	40	#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
	41	#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
	42	#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
	43	#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
	44	#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
	45	#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
	46
	47	#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800)
	48	#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810)
	49	#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820)
	50	#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840)
	51	#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850)
	52	#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860)
	53
	54	#define GPIO_INT_LVL_MASK 0x010101
	55	#define GPIO_INT_LVL_EDGE_RISING 0x000101
	56	#define GPIO_INT_LVL_EDGE_FALLING 0x000100
	57	#define GPIO_INT_LVL_EDGE_BOTH 0x010100
	58	#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
	59	#define GPIO_INT_LVL_LEVEL_LOW 0x000000
	60
	61	struct tegra_gpio_bank {
	62	int bank;
	63	int irq;
	64	spinlock_t lvl_lock[4];
2e47b8b3 CC	65	#ifdef CONFIG_PM
	66	u32 cnf[4];
	67	u32 out[4];
	68	u32 oe[4];
	69	u32 int_enb[4];
	70	u32 int_lvl[4];
	71	#endif
3c92db9a EG	72	};
	73
	74
	75	static struct tegra_gpio_bank tegra_gpio_banks[] = {
	76	{.bank = 0, .irq = INT_GPIO1},
	77	{.bank = 1, .irq = INT_GPIO2},
	78	{.bank = 2, .irq = INT_GPIO3},
	79	{.bank = 3, .irq = INT_GPIO4},
	80	{.bank = 4, .irq = INT_GPIO5},
	81	{.bank = 5, .irq = INT_GPIO6},
	82	{.bank = 6, .irq = INT_GPIO7},
	83	};
	84
	85	static int tegra_gpio_compose(int bank, int port, int bit)
	86	{
	87	return (bank << 5) \| ((port & 0x3) << 3) \| (bit & 0x7);
	88	}
	89
	90	static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
	91	{
	92	u32 val;
	93
	94	val = 0x100 << GPIO_BIT(gpio);
	95	if (value)
	96	val \|= 1 << GPIO_BIT(gpio);
	97	__raw_writel(val, reg);
	98	}
	99
	100	void tegra_gpio_enable(int gpio)
	101	{
	102	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
	103	}
	104
	105	void tegra_gpio_disable(int gpio)
	106	{
	107	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
	108	}
	109
	110	static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	111	{
	112	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
	113	}
	114
	115	static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
	116	{
	117	return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
	118	}
	119
	120	static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	121	{
	122	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	123	return 0;
	124	}
	125
	126	static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	127	int value)
	128	{
	129	tegra_gpio_set(chip, offset, value);
	130	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	131	return 0;
	132	}
	133
	134
	135
136	static struct gpio_chip tegra_gpio_chip = {
137	.label = "tegra-gpio",
138	.direction_input = tegra_gpio_direction_input,
139	.get = tegra_gpio_get,
140	.direction_output = tegra_gpio_direction_output,
141	.set = tegra_gpio_set,
142	.base = 0,
2e47b8b3	143	.ngpio = TEGRA_NR_GPIOS,
3c92db9a EG	144	};
3c92db9a EG	145
37337a8d	146	static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a	147	{
37337a8d	148	int gpio = d->irq - INT_GPIO_BASE;
3c92db9a EG	149
	150	__raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
	151	}
	152
37337a8d	153	static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a	154	{
37337a8d	155	int gpio = d->irq - INT_GPIO_BASE;
3c92db9a EG	156
	157	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
	158	}
	159
37337a8d	160	static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a	161	{
37337a8d	162	int gpio = d->irq - INT_GPIO_BASE;
3c92db9a EG	163
	164	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
	165	}
	166
37337a8d	167	static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a	168	{
37337a8d LB	169	int gpio = d->irq - INT_GPIO_BASE;
37337a8d LB	170	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
3c92db9a EG	171	int port = GPIO_PORT(gpio);
	172	int lvl_type;
	173	int val;
	174	unsigned long flags;
	175
	176	switch (type & IRQ_TYPE_SENSE_MASK) {
	177	case IRQ_TYPE_EDGE_RISING:
	178	lvl_type = GPIO_INT_LVL_EDGE_RISING;
	179	break;
	180
	181	case IRQ_TYPE_EDGE_FALLING:
	182	lvl_type = GPIO_INT_LVL_EDGE_FALLING;
	183	break;
	184
	185	case IRQ_TYPE_EDGE_BOTH:
	186	lvl_type = GPIO_INT_LVL_EDGE_BOTH;
	187	break;
	188
	189	case IRQ_TYPE_LEVEL_HIGH:
	190	lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
	191	break;
	192
	193	case IRQ_TYPE_LEVEL_LOW:
	194	lvl_type = GPIO_INT_LVL_LEVEL_LOW;
	195	break;
	196
	197	default:
	198	return -EINVAL;
	199	}
	200
	201	spin_lock_irqsave(&bank->lvl_lock[port], flags);
	202
	203	val = __raw_readl(GPIO_INT_LVL(gpio));
	204	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	205	val \|= lvl_type << GPIO_BIT(gpio);
	206	__raw_writel(val, GPIO_INT_LVL(gpio));
	207
	208	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
	209
	210	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
6845664a	211	__irq_set_handler_locked(d->irq, handle_level_irq);
3c92db9a	212	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
6845664a	213	__irq_set_handler_locked(d->irq, handle_edge_irq);
3c92db9a EG	214
	215	return 0;
	216	}
	217
	218	static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	219	{
	220	struct tegra_gpio_bank *bank;
	221	int port;
	222	int pin;
	223	int unmasked = 0;
	224
37337a8d	225	desc->irq_data.chip->irq_ack(&desc->irq_data);
3c92db9a	226
6845664a	227	bank = irq_get_handler_data(irq);
3c92db9a EG	228
	229	for (port = 0; port < 4; port++) {
	230	int gpio = tegra_gpio_compose(bank->bank, port, 0);
	231	unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
	232	__raw_readl(GPIO_INT_ENB(gpio));
	233	u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
	234
	235	for_each_set_bit(pin, &sta, 8) {
	236	__raw_writel(1 << pin, GPIO_INT_CLR(gpio));
	237
	238	/* if gpio is edge triggered, clear condition
	239	* before executing the hander so that we don't
	240	* miss edges
	241	*/
	242	if (lvl & (0x100 << pin)) {
	243	unmasked = 1;
37337a8d	244	desc->irq_data.chip->irq_unmask(&desc->irq_data);
3c92db9a EG	245	}
	246
	247	generic_handle_irq(gpio_to_irq(gpio + pin));
	248	}
	249	}
	250
	251	if (!unmasked)
37337a8d	252	desc->irq_data.chip->irq_unmask(&desc->irq_data);
3c92db9a EG	253
	254	}
	255
2e47b8b3 CC	256	#ifdef CONFIG_PM
	257	void tegra_gpio_resume(void)
	258	{
	259	unsigned long flags;
c8309ef6 CC	260	int b;
c8309ef6 CC	261	int p;
2e47b8b3 CC	262
	263	local_irq_save(flags);
	264
	265	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
	266	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	267
	268	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	269	unsigned int gpio = (b<<5) \| (p<<3);
	270	__raw_writel(bank->cnf[p], GPIO_CNF(gpio));
	271	__raw_writel(bank->out[p], GPIO_OUT(gpio));
	272	__raw_writel(bank->oe[p], GPIO_OE(gpio));
	273	__raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
	274	__raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
	275	}
	276	}
	277
	278	local_irq_restore(flags);
2e47b8b3 CC	279	}
	280
	281	void tegra_gpio_suspend(void)
	282	{
	283	unsigned long flags;
c8309ef6 CC	284	int b;
c8309ef6 CC	285	int p;
2e47b8b3	286
2e47b8b3 CC	287	local_irq_save(flags);
	288	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
	289	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	290
	291	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	292	unsigned int gpio = (b<<5) \| (p<<3);
	293	bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
	294	bank->out[p] = __raw_readl(GPIO_OUT(gpio));
	295	bank->oe[p] = __raw_readl(GPIO_OE(gpio));
	296	bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
	297	bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
	298	}
	299	}
	300	local_irq_restore(flags);
	301	}
	302
37337a8d	303	static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
2e47b8b3	304	{
37337a8d	305	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
6845664a	306	return irq_set_irq_wake(bank->irq, enable);
2e47b8b3 CC	307	}
2e47b8b3 CC	308	#endif
3c92db9a EG	309
	310	static struct irq_chip tegra_gpio_irq_chip = {
	311	.name = "GPIO",
37337a8d LB	312	.irq_ack = tegra_gpio_irq_ack,
	313	.irq_mask = tegra_gpio_irq_mask,
	314	.irq_unmask = tegra_gpio_irq_unmask,
	315	.irq_set_type = tegra_gpio_irq_set_type,
2e47b8b3	316	#ifdef CONFIG_PM
37337a8d	317	.irq_set_wake = tegra_gpio_wake_enable,
2e47b8b3	318	#endif
3c92db9a EG	319	};
	320
	321
	322	/* This lock class tells lockdep that GPIO irqs are in a different
	323	* category than their parents, so it won't report false recursion.
	324	*/
	325	static struct lock_class_key gpio_lock_class;
	326
	327	static int __init tegra_gpio_init(void)
	328	{
	329	struct tegra_gpio_bank *bank;
	330	int i;
	331	int j;
	332
	333	for (i = 0; i < 7; i++) {
	334	for (j = 0; j < 4; j++) {
	335	int gpio = tegra_gpio_compose(i, j, 0);
	336	__raw_writel(0x00, GPIO_INT_ENB(gpio));
	337	}
	338	}
	339
	340	gpiochip_add(&tegra_gpio_chip);
	341
2e47b8b3	342	for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
3c92db9a EG	343	bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
3c92db9a EG	344
1475b85d	345	irq_set_lockdep_class(i, &gpio_lock_class);
6845664a	346	irq_set_chip_data(i, bank);
f38c02f3 TG	347	irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
f38c02f3 TG	348	handle_simple_irq);
3c92db9a EG	349	set_irq_flags(i, IRQF_VALID);
	350	}
	351
	352	for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
	353	bank = &tegra_gpio_banks[i];
	354
6845664a TG	355	irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
6845664a TG	356	irq_set_handler_data(bank->irq, bank);
3c92db9a EG	357
	358	for (j = 0; j < 4; j++)
	359	spin_lock_init(&bank->lvl_lock[j]);
	360	}
	361
	362	return 0;
	363	}
	364
	365	postcore_initcall(tegra_gpio_init);
	366
632095ea OJ	367	void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
	368	{
	369	int i;
	370
	371	for (i = 0; i < num; i++) {
	372	int gpio = table[i].gpio;
	373
	374	if (table[i].enable)
	375	tegra_gpio_enable(gpio);
	376	else
	377	tegra_gpio_disable(gpio);
	378	}
	379	}
	380
3c92db9a EG	381	#ifdef CONFIG_DEBUG_FS
	382
	383	#include <linux/debugfs.h>
	384	#include <linux/seq_file.h>
	385
	386	static int dbg_gpio_show(struct seq_file s, void unused)
	387	{
	388	int i;
	389	int j;
	390
	391	for (i = 0; i < 7; i++) {
	392	for (j = 0; j < 4; j++) {
	393	int gpio = tegra_gpio_compose(i, j, 0);
2e47b8b3 CC	394	seq_printf(s,
	395	"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
	396	i, j,
	397	__raw_readl(GPIO_CNF(gpio)),
	398	__raw_readl(GPIO_OE(gpio)),
	399	__raw_readl(GPIO_OUT(gpio)),
	400	__raw_readl(GPIO_IN(gpio)),
	401	__raw_readl(GPIO_INT_STA(gpio)),
	402	__raw_readl(GPIO_INT_ENB(gpio)),
	403	__raw_readl(GPIO_INT_LVL(gpio)));
3c92db9a EG	404	}
	405	}
	406	return 0;
	407	}
	408
	409	static int dbg_gpio_open(struct inode inode, struct file file)
	410	{
	411	return single_open(file, dbg_gpio_show, &inode->i_private);
	412	}
	413
	414	static const struct file_operations debug_fops = {
	415	.open = dbg_gpio_open,
	416	.read = seq_read,
	417	.llseek = seq_lseek,
	418	.release = single_release,
	419	};
	420
	421	static int __init tegra_gpio_debuginit(void)
	422	{
	423	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
	424	NULL, NULL, &debug_fops);
	425	return 0;
	426	}
	427	late_initcall(tegra_gpio_debuginit);
	428	#endif