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1 | /* |
2 | * arch/arm/mach-tegra/gpio.c | |
3 | * | |
4 | * Copyright (c) 2010 Google, Inc | |
5 | * | |
6 | * Author: | |
7 | * Erik Gilling <konkers@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/irq.h> | |
22 | ||
23 | #include <linux/io.h> | |
24 | #include <linux/gpio.h> | |
25 | ||
26 | #include <mach/iomap.h> | |
27 | ||
28 | #define GPIO_BANK(x) ((x) >> 5) | |
29 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | |
30 | #define GPIO_BIT(x) ((x) & 0x7) | |
31 | ||
32 | #define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \ | |
33 | GPIO_BANK(x) * 0x80 + \ | |
34 | GPIO_PORT(x) * 4) | |
35 | ||
36 | #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) | |
37 | #define GPIO_OE(x) (GPIO_REG(x) + 0x10) | |
38 | #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) | |
39 | #define GPIO_IN(x) (GPIO_REG(x) + 0x30) | |
40 | #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) | |
41 | #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) | |
42 | #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) | |
43 | #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) | |
44 | ||
45 | #define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800) | |
46 | #define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810) | |
47 | #define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820) | |
48 | #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840) | |
49 | #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850) | |
50 | #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860) | |
51 | ||
52 | #define GPIO_INT_LVL_MASK 0x010101 | |
53 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 | |
54 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 | |
55 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 | |
56 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 | |
57 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 | |
58 | ||
59 | struct tegra_gpio_bank { | |
60 | int bank; | |
61 | int irq; | |
62 | spinlock_t lvl_lock[4]; | |
63 | }; | |
64 | ||
65 | ||
66 | static struct tegra_gpio_bank tegra_gpio_banks[] = { | |
67 | {.bank = 0, .irq = INT_GPIO1}, | |
68 | {.bank = 1, .irq = INT_GPIO2}, | |
69 | {.bank = 2, .irq = INT_GPIO3}, | |
70 | {.bank = 3, .irq = INT_GPIO4}, | |
71 | {.bank = 4, .irq = INT_GPIO5}, | |
72 | {.bank = 5, .irq = INT_GPIO6}, | |
73 | {.bank = 6, .irq = INT_GPIO7}, | |
74 | }; | |
75 | ||
76 | static int tegra_gpio_compose(int bank, int port, int bit) | |
77 | { | |
78 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); | |
79 | } | |
80 | ||
81 | static void tegra_gpio_mask_write(u32 reg, int gpio, int value) | |
82 | { | |
83 | u32 val; | |
84 | ||
85 | val = 0x100 << GPIO_BIT(gpio); | |
86 | if (value) | |
87 | val |= 1 << GPIO_BIT(gpio); | |
88 | __raw_writel(val, reg); | |
89 | } | |
90 | ||
91 | void tegra_gpio_enable(int gpio) | |
92 | { | |
93 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); | |
94 | } | |
95 | ||
96 | void tegra_gpio_disable(int gpio) | |
97 | { | |
98 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); | |
99 | } | |
100 | ||
101 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
102 | { | |
103 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); | |
104 | } | |
105 | ||
106 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) | |
107 | { | |
108 | return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; | |
109 | } | |
110 | ||
111 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
112 | { | |
113 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); | |
114 | return 0; | |
115 | } | |
116 | ||
117 | static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
118 | int value) | |
119 | { | |
120 | tegra_gpio_set(chip, offset, value); | |
121 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); | |
122 | return 0; | |
123 | } | |
124 | ||
125 | ||
126 | ||
127 | static struct gpio_chip tegra_gpio_chip = { | |
128 | .label = "tegra-gpio", | |
129 | .direction_input = tegra_gpio_direction_input, | |
130 | .get = tegra_gpio_get, | |
131 | .direction_output = tegra_gpio_direction_output, | |
132 | .set = tegra_gpio_set, | |
133 | .base = 0, | |
134 | .ngpio = ARCH_NR_GPIOS, | |
135 | }; | |
136 | ||
137 | static void tegra_gpio_irq_ack(unsigned int irq) | |
138 | { | |
139 | int gpio = irq - INT_GPIO_BASE; | |
140 | ||
141 | __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); | |
142 | } | |
143 | ||
144 | static void tegra_gpio_irq_mask(unsigned int irq) | |
145 | { | |
146 | int gpio = irq - INT_GPIO_BASE; | |
147 | ||
148 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); | |
149 | } | |
150 | ||
151 | static void tegra_gpio_irq_unmask(unsigned int irq) | |
152 | { | |
153 | int gpio = irq - INT_GPIO_BASE; | |
154 | ||
155 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); | |
156 | } | |
157 | ||
158 | static int tegra_gpio_irq_set_type(unsigned int irq, unsigned int type) | |
159 | { | |
160 | int gpio = irq - INT_GPIO_BASE; | |
161 | struct tegra_gpio_bank *bank = get_irq_chip_data(irq); | |
162 | int port = GPIO_PORT(gpio); | |
163 | int lvl_type; | |
164 | int val; | |
165 | unsigned long flags; | |
166 | ||
167 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
168 | case IRQ_TYPE_EDGE_RISING: | |
169 | lvl_type = GPIO_INT_LVL_EDGE_RISING; | |
170 | break; | |
171 | ||
172 | case IRQ_TYPE_EDGE_FALLING: | |
173 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; | |
174 | break; | |
175 | ||
176 | case IRQ_TYPE_EDGE_BOTH: | |
177 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; | |
178 | break; | |
179 | ||
180 | case IRQ_TYPE_LEVEL_HIGH: | |
181 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; | |
182 | break; | |
183 | ||
184 | case IRQ_TYPE_LEVEL_LOW: | |
185 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; | |
186 | break; | |
187 | ||
188 | default: | |
189 | return -EINVAL; | |
190 | } | |
191 | ||
192 | spin_lock_irqsave(&bank->lvl_lock[port], flags); | |
193 | ||
194 | val = __raw_readl(GPIO_INT_LVL(gpio)); | |
195 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); | |
196 | val |= lvl_type << GPIO_BIT(gpio); | |
197 | __raw_writel(val, GPIO_INT_LVL(gpio)); | |
198 | ||
199 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | |
200 | ||
201 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
202 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
203 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
204 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
210 | { | |
211 | struct tegra_gpio_bank *bank; | |
212 | int port; | |
213 | int pin; | |
214 | int unmasked = 0; | |
215 | ||
216 | desc->chip->ack(irq); | |
217 | ||
218 | bank = get_irq_data(irq); | |
219 | ||
220 | for (port = 0; port < 4; port++) { | |
221 | int gpio = tegra_gpio_compose(bank->bank, port, 0); | |
222 | unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) & | |
223 | __raw_readl(GPIO_INT_ENB(gpio)); | |
224 | u32 lvl = __raw_readl(GPIO_INT_LVL(gpio)); | |
225 | ||
226 | for_each_set_bit(pin, &sta, 8) { | |
227 | __raw_writel(1 << pin, GPIO_INT_CLR(gpio)); | |
228 | ||
229 | /* if gpio is edge triggered, clear condition | |
230 | * before executing the hander so that we don't | |
231 | * miss edges | |
232 | */ | |
233 | if (lvl & (0x100 << pin)) { | |
234 | unmasked = 1; | |
235 | desc->chip->unmask(irq); | |
236 | } | |
237 | ||
238 | generic_handle_irq(gpio_to_irq(gpio + pin)); | |
239 | } | |
240 | } | |
241 | ||
242 | if (!unmasked) | |
243 | desc->chip->unmask(irq); | |
244 | ||
245 | } | |
246 | ||
247 | ||
248 | static struct irq_chip tegra_gpio_irq_chip = { | |
249 | .name = "GPIO", | |
250 | .ack = tegra_gpio_irq_ack, | |
251 | .mask = tegra_gpio_irq_mask, | |
252 | .unmask = tegra_gpio_irq_unmask, | |
253 | .set_type = tegra_gpio_irq_set_type, | |
254 | }; | |
255 | ||
256 | ||
257 | /* This lock class tells lockdep that GPIO irqs are in a different | |
258 | * category than their parents, so it won't report false recursion. | |
259 | */ | |
260 | static struct lock_class_key gpio_lock_class; | |
261 | ||
262 | static int __init tegra_gpio_init(void) | |
263 | { | |
264 | struct tegra_gpio_bank *bank; | |
265 | int i; | |
266 | int j; | |
267 | ||
268 | for (i = 0; i < 7; i++) { | |
269 | for (j = 0; j < 4; j++) { | |
270 | int gpio = tegra_gpio_compose(i, j, 0); | |
271 | __raw_writel(0x00, GPIO_INT_ENB(gpio)); | |
272 | } | |
273 | } | |
274 | ||
275 | gpiochip_add(&tegra_gpio_chip); | |
276 | ||
277 | for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + ARCH_NR_GPIOS); i++) { | |
278 | bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; | |
279 | ||
280 | lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class); | |
281 | set_irq_chip_data(i, bank); | |
282 | set_irq_chip(i, &tegra_gpio_irq_chip); | |
283 | set_irq_handler(i, handle_simple_irq); | |
284 | set_irq_flags(i, IRQF_VALID); | |
285 | } | |
286 | ||
287 | for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { | |
288 | bank = &tegra_gpio_banks[i]; | |
289 | ||
290 | set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); | |
291 | set_irq_data(bank->irq, bank); | |
292 | ||
293 | for (j = 0; j < 4; j++) | |
294 | spin_lock_init(&bank->lvl_lock[j]); | |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | postcore_initcall(tegra_gpio_init); | |
301 | ||
302 | #ifdef CONFIG_DEBUG_FS | |
303 | ||
304 | #include <linux/debugfs.h> | |
305 | #include <linux/seq_file.h> | |
306 | ||
307 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
308 | { | |
309 | int i; | |
310 | int j; | |
311 | ||
312 | for (i = 0; i < 7; i++) { | |
313 | for (j = 0; j < 4; j++) { | |
314 | int gpio = tegra_gpio_compose(i, j, 0); | |
315 | seq_printf(s, "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", | |
316 | i, j, | |
317 | __raw_readl(GPIO_CNF(gpio)), | |
318 | __raw_readl(GPIO_OE(gpio)), | |
319 | __raw_readl(GPIO_OUT(gpio)), | |
320 | __raw_readl(GPIO_IN(gpio)), | |
321 | __raw_readl(GPIO_INT_STA(gpio)), | |
322 | __raw_readl(GPIO_INT_ENB(gpio)), | |
323 | __raw_readl(GPIO_INT_LVL(gpio))); | |
324 | } | |
325 | } | |
326 | return 0; | |
327 | } | |
328 | ||
329 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
330 | { | |
331 | return single_open(file, dbg_gpio_show, &inode->i_private); | |
332 | } | |
333 | ||
334 | static const struct file_operations debug_fops = { | |
335 | .open = dbg_gpio_open, | |
336 | .read = seq_read, | |
337 | .llseek = seq_lseek, | |
338 | .release = single_release, | |
339 | }; | |
340 | ||
341 | static int __init tegra_gpio_debuginit(void) | |
342 | { | |
343 | (void) debugfs_create_file("tegra_gpio", S_IRUGO, | |
344 | NULL, NULL, &debug_fops); | |
345 | return 0; | |
346 | } | |
347 | late_initcall(tegra_gpio_debuginit); | |
348 | #endif |