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c5f80065 EG |
1 | /* |
2 | * arch/arm/mach-tegra/include/mach/iomap.h | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@google.com> | |
8 | * Erik Gilling <konkers@google.com> | |
9 | * | |
10 | * This software is licensed under the terms of the GNU General Public | |
11 | * License version 2, as published by the Free Software Foundation, and | |
12 | * may be copied, distributed, and modified under those terms. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | */ | |
20 | ||
21 | #ifndef __MACH_TEGRA_IOMAP_H | |
22 | #define __MACH_TEGRA_IOMAP_H | |
23 | ||
24 | #include <asm/sizes.h> | |
25 | ||
c231d697 CC |
26 | #define TEGRA_IRAM_BASE 0x40000000 |
27 | #define TEGRA_IRAM_SIZE SZ_256K | |
28 | ||
537f5af0 GK |
29 | #define TEGRA_HOST1X_BASE 0x50000000 |
30 | #define TEGRA_HOST1X_SIZE 0x24000 | |
31 | ||
c5f80065 EG |
32 | #define TEGRA_ARM_PERIF_BASE 0x50040000 |
33 | #define TEGRA_ARM_PERIF_SIZE SZ_8K | |
34 | ||
c231d697 CC |
35 | #define TEGRA_ARM_PL310_BASE 0x50043000 |
36 | #define TEGRA_ARM_PL310_SIZE SZ_4K | |
37 | ||
c5f80065 EG |
38 | #define TEGRA_ARM_INT_DIST_BASE 0x50041000 |
39 | #define TEGRA_ARM_INT_DIST_SIZE SZ_4K | |
40 | ||
537f5af0 GK |
41 | #define TEGRA_MPE_BASE 0x54040000 |
42 | #define TEGRA_MPE_SIZE SZ_256K | |
43 | ||
44 | #define TEGRA_VI_BASE 0x54080000 | |
45 | #define TEGRA_VI_SIZE SZ_256K | |
46 | ||
47 | #define TEGRA_ISP_BASE 0x54100000 | |
48 | #define TEGRA_ISP_SIZE SZ_256K | |
49 | ||
c5f80065 EG |
50 | #define TEGRA_DISPLAY_BASE 0x54200000 |
51 | #define TEGRA_DISPLAY_SIZE SZ_256K | |
52 | ||
53 | #define TEGRA_DISPLAY2_BASE 0x54240000 | |
54 | #define TEGRA_DISPLAY2_SIZE SZ_256K | |
55 | ||
537f5af0 GK |
56 | #define TEGRA_HDMI_BASE 0x54280000 |
57 | #define TEGRA_HDMI_SIZE SZ_256K | |
58 | ||
59 | #define TEGRA_GART_BASE 0x58000000 | |
60 | #define TEGRA_GART_SIZE SZ_32M | |
61 | ||
62 | #define TEGRA_RES_SEMA_BASE 0x60001000 | |
63 | #define TEGRA_RES_SEMA_SIZE SZ_4K | |
64 | ||
c5f80065 EG |
65 | #define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 |
66 | #define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 | |
67 | ||
68 | #define TEGRA_SECONDARY_ICTLR_BASE 0x60004100 | |
69 | #define TEGRA_SECONDARY_ICTLR_SIZE SZ_64 | |
70 | ||
71 | #define TEGRA_TERTIARY_ICTLR_BASE 0x60004200 | |
72 | #define TEGRA_TERTIARY_ICTLR_SIZE SZ_64 | |
73 | ||
74 | #define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300 | |
75 | #define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64 | |
76 | ||
caa4868e PDS |
77 | #define TEGRA_QUINARY_ICTLR_BASE 0x60004400 |
78 | #define TEGRA_QUINARY_ICTLR_SIZE SZ_64 | |
79 | ||
c5f80065 EG |
80 | #define TEGRA_TMR1_BASE 0x60005000 |
81 | #define TEGRA_TMR1_SIZE SZ_8 | |
82 | ||
83 | #define TEGRA_TMR2_BASE 0x60005008 | |
84 | #define TEGRA_TMR2_SIZE SZ_8 | |
85 | ||
86 | #define TEGRA_TMRUS_BASE 0x60005010 | |
87 | #define TEGRA_TMRUS_SIZE SZ_64 | |
88 | ||
89 | #define TEGRA_TMR3_BASE 0x60005050 | |
90 | #define TEGRA_TMR3_SIZE SZ_8 | |
91 | ||
92 | #define TEGRA_TMR4_BASE 0x60005058 | |
93 | #define TEGRA_TMR4_SIZE SZ_8 | |
94 | ||
95 | #define TEGRA_CLK_RESET_BASE 0x60006000 | |
96 | #define TEGRA_CLK_RESET_SIZE SZ_4K | |
97 | ||
98 | #define TEGRA_FLOW_CTRL_BASE 0x60007000 | |
99 | #define TEGRA_FLOW_CTRL_SIZE 20 | |
100 | ||
c231d697 CC |
101 | #define TEGRA_AHB_DMA_BASE 0x60008000 |
102 | #define TEGRA_AHB_DMA_SIZE SZ_4K | |
103 | ||
104 | #define TEGRA_AHB_DMA_CH0_BASE 0x60009000 | |
105 | #define TEGRA_AHB_DMA_CH0_SIZE 32 | |
106 | ||
107 | #define TEGRA_APB_DMA_BASE 0x6000A000 | |
108 | #define TEGRA_APB_DMA_SIZE SZ_4K | |
109 | ||
110 | #define TEGRA_APB_DMA_CH0_BASE 0x6000B000 | |
111 | #define TEGRA_APB_DMA_CH0_SIZE 32 | |
112 | ||
113 | #define TEGRA_AHB_GIZMO_BASE 0x6000C004 | |
114 | #define TEGRA_AHB_GIZMO_SIZE 0x10C | |
115 | ||
116 | #define TEGRA_STATMON_BASE 0x6000C400 | |
c5f80065 EG |
117 | #define TEGRA_STATMON_SIZE SZ_1K |
118 | ||
119 | #define TEGRA_GPIO_BASE 0x6000D000 | |
120 | #define TEGRA_GPIO_SIZE SZ_4K | |
121 | ||
122 | #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 | |
123 | #define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K | |
124 | ||
125 | #define TEGRA_APB_MISC_BASE 0x70000000 | |
126 | #define TEGRA_APB_MISC_SIZE SZ_4K | |
127 | ||
b9652c2d SW |
128 | #define TEGRA_APB_MISC_DAS_BASE 0x70000c00 |
129 | #define TEGRA_APB_MISC_DAS_SIZE SZ_128 | |
130 | ||
c5f80065 EG |
131 | #define TEGRA_AC97_BASE 0x70002000 |
132 | #define TEGRA_AC97_SIZE SZ_512 | |
133 | ||
134 | #define TEGRA_SPDIF_BASE 0x70002400 | |
135 | #define TEGRA_SPDIF_SIZE SZ_512 | |
136 | ||
137 | #define TEGRA_I2S1_BASE 0x70002800 | |
138 | #define TEGRA_I2S1_SIZE SZ_256 | |
139 | ||
140 | #define TEGRA_I2S2_BASE 0x70002A00 | |
141 | #define TEGRA_I2S2_SIZE SZ_256 | |
142 | ||
143 | #define TEGRA_UARTA_BASE 0x70006000 | |
144 | #define TEGRA_UARTA_SIZE SZ_64 | |
145 | ||
146 | #define TEGRA_UARTB_BASE 0x70006040 | |
147 | #define TEGRA_UARTB_SIZE SZ_64 | |
148 | ||
149 | #define TEGRA_UARTC_BASE 0x70006200 | |
150 | #define TEGRA_UARTC_SIZE SZ_256 | |
151 | ||
152 | #define TEGRA_UARTD_BASE 0x70006300 | |
153 | #define TEGRA_UARTD_SIZE SZ_256 | |
154 | ||
155 | #define TEGRA_UARTE_BASE 0x70006400 | |
156 | #define TEGRA_UARTE_SIZE SZ_256 | |
157 | ||
158 | #define TEGRA_NAND_BASE 0x70008000 | |
159 | #define TEGRA_NAND_SIZE SZ_256 | |
160 | ||
161 | #define TEGRA_HSMMC_BASE 0x70008500 | |
162 | #define TEGRA_HSMMC_SIZE SZ_256 | |
163 | ||
164 | #define TEGRA_SNOR_BASE 0x70009000 | |
165 | #define TEGRA_SNOR_SIZE SZ_4K | |
166 | ||
167 | #define TEGRA_PWFM_BASE 0x7000A000 | |
168 | #define TEGRA_PWFM_SIZE SZ_256 | |
169 | ||
537f5af0 GK |
170 | #define TEGRA_PWFM0_BASE 0x7000A000 |
171 | #define TEGRA_PWFM0_SIZE 4 | |
172 | ||
173 | #define TEGRA_PWFM1_BASE 0x7000A010 | |
174 | #define TEGRA_PWFM1_SIZE 4 | |
175 | ||
176 | #define TEGRA_PWFM2_BASE 0x7000A020 | |
177 | #define TEGRA_PWFM2_SIZE 4 | |
178 | ||
179 | #define TEGRA_PWFM3_BASE 0x7000A030 | |
180 | #define TEGRA_PWFM3_SIZE 4 | |
181 | ||
c5f80065 EG |
182 | #define TEGRA_MIPI_BASE 0x7000B000 |
183 | #define TEGRA_MIPI_SIZE SZ_256 | |
184 | ||
185 | #define TEGRA_I2C_BASE 0x7000C000 | |
186 | #define TEGRA_I2C_SIZE SZ_256 | |
187 | ||
188 | #define TEGRA_TWC_BASE 0x7000C100 | |
189 | #define TEGRA_TWC_SIZE SZ_256 | |
190 | ||
191 | #define TEGRA_SPI_BASE 0x7000C380 | |
192 | #define TEGRA_SPI_SIZE 48 | |
193 | ||
194 | #define TEGRA_I2C2_BASE 0x7000C400 | |
195 | #define TEGRA_I2C2_SIZE SZ_256 | |
196 | ||
197 | #define TEGRA_I2C3_BASE 0x7000C500 | |
198 | #define TEGRA_I2C3_SIZE SZ_256 | |
199 | ||
c231d697 | 200 | #define TEGRA_OWR_BASE 0x7000C600 |
c5f80065 EG |
201 | #define TEGRA_OWR_SIZE 80 |
202 | ||
203 | #define TEGRA_DVC_BASE 0x7000D000 | |
204 | #define TEGRA_DVC_SIZE SZ_512 | |
205 | ||
206 | #define TEGRA_SPI1_BASE 0x7000D400 | |
207 | #define TEGRA_SPI1_SIZE SZ_512 | |
208 | ||
209 | #define TEGRA_SPI2_BASE 0x7000D600 | |
210 | #define TEGRA_SPI2_SIZE SZ_512 | |
211 | ||
212 | #define TEGRA_SPI3_BASE 0x7000D800 | |
213 | #define TEGRA_SPI3_SIZE SZ_512 | |
214 | ||
215 | #define TEGRA_SPI4_BASE 0x7000DA00 | |
216 | #define TEGRA_SPI4_SIZE SZ_512 | |
217 | ||
218 | #define TEGRA_RTC_BASE 0x7000E000 | |
219 | #define TEGRA_RTC_SIZE SZ_256 | |
220 | ||
221 | #define TEGRA_KBC_BASE 0x7000E200 | |
222 | #define TEGRA_KBC_SIZE SZ_256 | |
223 | ||
224 | #define TEGRA_PMC_BASE 0x7000E400 | |
225 | #define TEGRA_PMC_SIZE SZ_256 | |
226 | ||
227 | #define TEGRA_MC_BASE 0x7000F000 | |
228 | #define TEGRA_MC_SIZE SZ_1K | |
229 | ||
230 | #define TEGRA_EMC_BASE 0x7000F400 | |
231 | #define TEGRA_EMC_SIZE SZ_1K | |
232 | ||
233 | #define TEGRA_FUSE_BASE 0x7000F800 | |
234 | #define TEGRA_FUSE_SIZE SZ_1K | |
235 | ||
236 | #define TEGRA_KFUSE_BASE 0x7000FC00 | |
237 | #define TEGRA_KFUSE_SIZE SZ_1K | |
238 | ||
239 | #define TEGRA_CSITE_BASE 0x70040000 | |
240 | #define TEGRA_CSITE_SIZE SZ_256K | |
241 | ||
242 | #define TEGRA_USB_BASE 0xC5000000 | |
243 | #define TEGRA_USB_SIZE SZ_16K | |
244 | ||
c231d697 | 245 | #define TEGRA_USB2_BASE 0xC5004000 |
c5f80065 EG |
246 | #define TEGRA_USB2_SIZE SZ_16K |
247 | ||
c231d697 CC |
248 | #define TEGRA_USB3_BASE 0xC5008000 |
249 | #define TEGRA_USB3_SIZE SZ_16K | |
250 | ||
c5f80065 EG |
251 | #define TEGRA_SDMMC1_BASE 0xC8000000 |
252 | #define TEGRA_SDMMC1_SIZE SZ_512 | |
253 | ||
254 | #define TEGRA_SDMMC2_BASE 0xC8000200 | |
255 | #define TEGRA_SDMMC2_SIZE SZ_512 | |
256 | ||
257 | #define TEGRA_SDMMC3_BASE 0xC8000400 | |
258 | #define TEGRA_SDMMC3_SIZE SZ_512 | |
259 | ||
260 | #define TEGRA_SDMMC4_BASE 0xC8000600 | |
261 | #define TEGRA_SDMMC4_SIZE SZ_512 | |
262 | ||
d377eb0d CC |
263 | #if defined(CONFIG_TEGRA_DEBUG_UART_NONE) |
264 | # define TEGRA_DEBUG_UART_BASE 0 | |
265 | #elif defined(CONFIG_TEGRA_DEBUG_UARTA) | |
266 | # define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE | |
267 | #elif defined(CONFIG_TEGRA_DEBUG_UARTB) | |
268 | # define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE | |
269 | #elif defined(CONFIG_TEGRA_DEBUG_UARTC) | |
270 | # define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE | |
271 | #elif defined(CONFIG_TEGRA_DEBUG_UARTD) | |
272 | # define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE | |
273 | #elif defined(CONFIG_TEGRA_DEBUG_UARTE) | |
274 | # define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE | |
275 | #endif | |
276 | ||
c5f80065 | 277 | #endif |