[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-tegra / reset.c

/*
 * arch/arm/mach-tegra/reset.c
 *
 * Copyright (C) 2011,2012 NVIDIA Corporation.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/bitops.h>
#include <linux/cpumask.h>
#include <linux/init.h>
#include <linux/io.h>

#include <linux/firmware/trusted_foundations.h>

#include <soc/tegra/fuse.h>

#include <asm/cacheflush.h>
#include <asm/firmware.h>
#include <asm/hardware/cache-l2x0.h>

#include "iomap.h"
#include "irammap.h"
#include "reset.h"
#include "sleep.h"

#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
				TEGRA_IRAM_RESET_HANDLER_OFFSET)

static bool is_enabled;

static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
{
	void __iomem *evp_cpu_reset =
		IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
	void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
	u32 reg;

	/*
	 * NOTE: This must be the one and only write to the EVP CPU reset
	 *       vector in the entire system.
	 */
	writel(reset_address, evp_cpu_reset);
	wmb();
	reg = readl(evp_cpu_reset);

	/*
	 * Prevent further modifications to the physical reset vector.
	 *  NOTE: Has no effect on chips prior to Tegra30.
	 */
	reg = readl(sb_ctrl);
	reg |= 2;
	writel(reg, sb_ctrl);
	wmb();
}

static void __init tegra_cpu_reset_handler_enable(void)
{
	void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
	const u32 reset_address = TEGRA_IRAM_RESET_BASE +
						tegra_cpu_reset_handler_offset;
	int err;

	BUG_ON(is_enabled);
	BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);

	memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
			tegra_cpu_reset_handler_size);

	err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);
	switch (err) {
	case -ENOSYS:
		tegra_cpu_reset_handler_set(reset_address);
		/* pass-through */
	case 0:
		is_enabled = true;
		break;
	default:
		pr_crit("Cannot set CPU reset handler: %d\n", err);
		BUG();
	}
}

void __init tegra_cpu_reset_handler_init(void)
{
	__tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] =
		trusted_foundations_registered();

#ifdef CONFIG_SMP
	__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
		*((u32 *)cpu_possible_mask);
	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
		__pa_symbol((void *)secondary_startup);
#endif

#ifdef CONFIG_PM_SLEEP
	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
		TEGRA_IRAM_LPx_RESUME_AREA;
	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
		__pa_symbol((void *)tegra_resume);
#endif

	tegra_cpu_reset_handler_enable();
}
Commit	Line	Data
b36ab975 PDS	1	/*
	2	* arch/arm/mach-tegra/reset.c
	3	*
	4	* Copyright (C) 2011,2012 NVIDIA Corporation.
	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
a0524acc TR	17	#include <linux/bitops.h>
a0524acc TR	18	#include <linux/cpumask.h>
b36ab975 PDS	19	#include <linux/init.h>
b36ab975 PDS	20	#include <linux/io.h>
b36ab975	21
4cb5d9ec TR	22	#include <linux/firmware/trusted_foundations.h>
4cb5d9ec TR	23
304664ea TR	24	#include <soc/tegra/fuse.h>
304664ea TR	25
b36ab975	26	#include <asm/cacheflush.h>
265c89c9	27	#include <asm/firmware.h>
a0524acc	28	#include <asm/hardware/cache-l2x0.h>
b36ab975	29
2be39c07	30	#include "iomap.h"
bb1de887	31	#include "irammap.h"
b36ab975	32	#include "reset.h"
d3f29365	33	#include "sleep.h"
b36ab975 PDS	34
	35	#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
	36	TEGRA_IRAM_RESET_HANDLER_OFFSET)
	37
	38	static bool is_enabled;
	39
ad14ecee	40	static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
b36ab975	41	{
b36ab975 PDS	42	void __iomem *evp_cpu_reset =
	43	IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
	44	void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
	45	u32 reg;
	46
b36ab975 PDS	47	/*
	48	* NOTE: This must be the one and only write to the EVP CPU reset
	49	* vector in the entire system.
	50	*/
ad14ecee	51	writel(reset_address, evp_cpu_reset);
b36ab975 PDS	52	wmb();
	53	reg = readl(evp_cpu_reset);
	54
	55	/*
	56	* Prevent further modifications to the physical reset vector.
	57	* NOTE: Has no effect on chips prior to Tegra30.
	58	*/
c090e111 TR	59	reg = readl(sb_ctrl);
	60	reg \|= 2;
	61	writel(reg, sb_ctrl);
	62	wmb();
ad14ecee AC	63	}
	64
	65	static void __init tegra_cpu_reset_handler_enable(void)
	66	{
	67	void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
	68	const u32 reset_address = TEGRA_IRAM_RESET_BASE +
	69	tegra_cpu_reset_handler_offset;
265c89c9	70	int err;
ad14ecee AC	71
	72	BUG_ON(is_enabled);
	73	BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
	74
	75	memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
	76	tegra_cpu_reset_handler_size);
	77
265c89c9 AC	78	err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);
	79	switch (err) {
	80	case -ENOSYS:
	81	tegra_cpu_reset_handler_set(reset_address);
	82	/* pass-through */
	83	case 0:
	84	is_enabled = true;
	85	break;
	86	default:
	87	pr_crit("Cannot set CPU reset handler: %d\n", err);
	88	BUG();
	89	}
b36ab975 PDS	90	}
	91
	92	void __init tegra_cpu_reset_handler_init(void)
	93	{
2af6597a DO	94	__tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] =
2af6597a DO	95	trusted_foundations_registered();
b36ab975 PDS	96
	97	#ifdef CONFIG_SMP
	98	__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
9e32366f	99	((u32 )cpu_possible_mask);
b36ab975	100	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
64fc2a94	101	__pa_symbol((void *)secondary_startup);
b36ab975 PDS	102	#endif
b36ab975 PDS	103
d3f29365	104	#ifdef CONFIG_PM_SLEEP
5b795d05	105	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
fddb770d	106	TEGRA_IRAM_LPx_RESUME_AREA;
d3f29365	107	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
64fc2a94	108	__pa_symbol((void *)tegra_resume);
d3f29365 JL	109	#endif
d3f29365 JL	110
b36ab975 PDS	111	tegra_cpu_reset_handler_enable();
b36ab975 PDS	112	}