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Commit | Line | Data |
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8e267f3d | 1 | /* |
1b14f3a5 | 2 | * NVIDIA Tegra SoC device tree board support |
8e267f3d | 3 | * |
1b14f3a5 | 4 | * Copyright (C) 2011, 2013, NVIDIA Corporation |
8e267f3d GL |
5 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. |
6 | * Copyright (C) 2010 Google, Inc. | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
1711b1e1 | 19 | #include <linux/clocksource.h> |
8e267f3d GL |
20 | #include <linux/kernel.h> |
21 | #include <linux/init.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/serial_8250.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/irqdomain.h> | |
27 | #include <linux/of.h> | |
28 | #include <linux/of_address.h> | |
29 | #include <linux/of_fdt.h> | |
8e267f3d GL |
30 | #include <linux/of_platform.h> |
31 | #include <linux/pda_power.h> | |
32 | #include <linux/io.h> | |
d591fdf8 DH |
33 | #include <linux/slab.h> |
34 | #include <linux/sys_soc.h> | |
bab53ce3 | 35 | #include <linux/usb/tegra_usb_phy.h> |
d2207071 | 36 | #include <linux/clk-provider.h> |
441f199a | 37 | #include <linux/clk/tegra.h> |
51100bdc | 38 | #include <linux/irqchip.h> |
8e267f3d | 39 | |
51100bdc | 40 | #include <asm/hardware/cache-l2x0.h> |
8e267f3d GL |
41 | #include <asm/mach-types.h> |
42 | #include <asm/mach/arch.h> | |
43 | #include <asm/mach/time.h> | |
44 | #include <asm/setup.h> | |
45 | ||
51100bdc | 46 | #include "apbio.h" |
8e267f3d | 47 | #include "board.h" |
a1725732 | 48 | #include "common.h" |
51100bdc | 49 | #include "cpuidle.h" |
d591fdf8 | 50 | #include "fuse.h" |
2be39c07 | 51 | #include "iomap.h" |
51100bdc | 52 | #include "irq.h" |
d2207071 | 53 | #include "pmc.h" |
51100bdc SW |
54 | #include "pm.h" |
55 | #include "reset.h" | |
56 | #include "sleep.h" | |
57 | ||
58 | /* | |
59 | * Storage for debug-macro.S's state. | |
60 | * | |
61 | * This must be in .data not .bss so that it gets initialized each time the | |
62 | * kernel is loaded. The data is declared here rather than debug-macro.S so | |
63 | * that multiple inclusions of debug-macro.S point at the same data. | |
64 | */ | |
65 | u32 tegra_uart_config[4] = { | |
66 | /* Debug UART initialization required */ | |
67 | 1, | |
68 | /* Debug UART physical address */ | |
69 | 0, | |
70 | /* Debug UART virtual address */ | |
71 | 0, | |
72 | /* Scratch space for debug macro */ | |
73 | 0, | |
74 | }; | |
75 | ||
76 | static void __init tegra_init_cache(void) | |
77 | { | |
78 | #ifdef CONFIG_CACHE_L2X0 | |
79 | int ret; | |
80 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; | |
81 | u32 aux_ctrl, cache_type; | |
82 | ||
83 | cache_type = readl(p + L2X0_CACHE_TYPE); | |
84 | aux_ctrl = (cache_type & 0x700) << (17-8); | |
85 | aux_ctrl |= 0x7C400001; | |
86 | ||
87 | ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); | |
88 | if (!ret) | |
89 | l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); | |
90 | #endif | |
91 | } | |
92 | ||
93 | static void __init tegra_init_early(void) | |
94 | { | |
95 | tegra_cpu_reset_handler_init(); | |
96 | tegra_apb_io_init(); | |
97 | tegra_init_fuse(); | |
98 | tegra_init_cache(); | |
99 | tegra_powergate_init(); | |
100 | tegra_hotplug_init(); | |
101 | } | |
102 | ||
103 | static void __init tegra_dt_init_irq(void) | |
104 | { | |
105 | tegra_pmc_init_irq(); | |
106 | tegra_init_irq(); | |
107 | irqchip_init(); | |
108 | tegra_legacy_irq_syscore_init(); | |
109 | } | |
bab53ce3 | 110 | |
8e267f3d GL |
111 | static void __init tegra_dt_init(void) |
112 | { | |
d591fdf8 DH |
113 | struct soc_device_attribute *soc_dev_attr; |
114 | struct soc_device *soc_dev; | |
115 | struct device *parent = NULL; | |
116 | ||
d2207071 SW |
117 | tegra_pmc_init(); |
118 | ||
441f199a SW |
119 | tegra_clocks_apply_init_table(); |
120 | ||
d591fdf8 DH |
121 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); |
122 | if (!soc_dev_attr) | |
123 | goto out; | |
124 | ||
125 | soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra"); | |
126 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision); | |
127 | soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id); | |
128 | ||
129 | soc_dev = soc_device_register(soc_dev_attr); | |
130 | if (IS_ERR(soc_dev)) { | |
131 | kfree(soc_dev_attr->family); | |
132 | kfree(soc_dev_attr->revision); | |
133 | kfree(soc_dev_attr->soc_id); | |
134 | kfree(soc_dev_attr); | |
135 | goto out; | |
136 | } | |
137 | ||
138 | parent = soc_device_to_device(soc_dev); | |
139 | ||
a58116f3 SW |
140 | /* |
141 | * Finished with the static registrations now; fill in the missing | |
142 | * devices | |
143 | */ | |
d591fdf8 | 144 | out: |
5fed6828 | 145 | of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); |
8e267f3d GL |
146 | } |
147 | ||
d2207071 SW |
148 | static void __init tegra_dt_init_time(void) |
149 | { | |
150 | of_clk_init(NULL); | |
151 | clocksource_of_init(); | |
152 | } | |
153 | ||
b64a02c6 SW |
154 | static void __init paz00_init(void) |
155 | { | |
1b14f3a5 HD |
156 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
157 | tegra_paz00_wifikill_init(); | |
b64a02c6 | 158 | } |
b64a02c6 | 159 | |
c554dee3 SW |
160 | static struct { |
161 | char *machine; | |
162 | void (*init)(void); | |
163 | } board_init_funcs[] = { | |
b64a02c6 | 164 | { "compal,paz00", paz00_init }, |
c554dee3 SW |
165 | }; |
166 | ||
167 | static void __init tegra_dt_init_late(void) | |
168 | { | |
169 | int i; | |
170 | ||
51100bdc SW |
171 | tegra_init_suspend(); |
172 | tegra_cpuidle_init(); | |
173 | tegra_powergate_debugfs_init(); | |
c554dee3 SW |
174 | |
175 | for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { | |
176 | if (of_machine_is_compatible(board_init_funcs[i].machine)) { | |
177 | board_init_funcs[i].init(); | |
178 | break; | |
179 | } | |
180 | } | |
181 | } | |
182 | ||
1b14f3a5 HD |
183 | static const char * const tegra_dt_board_compat[] = { |
184 | "nvidia,tegra114", | |
185 | "nvidia,tegra30", | |
c5444f39 | 186 | "nvidia,tegra20", |
8e267f3d GL |
187 | NULL |
188 | }; | |
189 | ||
1b14f3a5 | 190 | DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") |
8e267f3d | 191 | .map_io = tegra_map_common_io, |
a1725732 | 192 | .smp = smp_ops(tegra_smp_ops), |
7469688e | 193 | .init_early = tegra_init_early, |
0d4f7479 | 194 | .init_irq = tegra_dt_init_irq, |
d2207071 | 195 | .init_time = tegra_dt_init_time, |
8e267f3d | 196 | .init_machine = tegra_dt_init, |
c554dee3 | 197 | .init_late = tegra_dt_init_late, |
51100bdc | 198 | .restart = tegra_pmc_restart, |
1b14f3a5 | 199 | .dt_compat = tegra_dt_board_compat, |
8e267f3d | 200 | MACHINE_END |