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Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-tegra / tegra.c
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9c92ab61 1// SPDX-License-Identifier: GPL-2.0-only
8e267f3d 2/*
1b14f3a5 3 * NVIDIA Tegra SoC device tree board support
8e267f3d 4 *
1b14f3a5 5 * Copyright (C) 2011, 2013, NVIDIA Corporation
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6 * Copyright (C) 2010 Secret Lab Technologies, Ltd.
7 * Copyright (C) 2010 Google, Inc.
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8 */
9
8e267f3d 10#include <linux/clk.h>
a0524acc 11#include <linux/clk/tegra.h>
8e267f3d 12#include <linux/dma-mapping.h>
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13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/irqchip.h>
8e267f3d 16#include <linux/irqdomain.h>
a0524acc 17#include <linux/kernel.h>
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18#include <linux/of_address.h>
19#include <linux/of_fdt.h>
a0524acc 20#include <linux/of.h>
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21#include <linux/of_platform.h>
22#include <linux/pda_power.h>
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23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
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25#include <linux/slab.h>
26#include <linux/sys_soc.h>
bab53ce3 27#include <linux/usb/tegra_usb_phy.h>
8e267f3d 28
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29#include <linux/firmware/trusted_foundations.h>
30
304664ea 31#include <soc/tegra/fuse.h>
7232398a 32#include <soc/tegra/pmc.h>
304664ea 33
6ad27b83 34#include <asm/firmware.h>
51100bdc 35#include <asm/hardware/cache-l2x0.h>
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36#include <asm/mach/arch.h>
37#include <asm/mach/time.h>
a0524acc 38#include <asm/mach-types.h>
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39#include <asm/setup.h>
40
8e267f3d 41#include "board.h"
a1725732 42#include "common.h"
51100bdc 43#include "cpuidle.h"
2be39c07 44#include "iomap.h"
51100bdc 45#include "irq.h"
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46#include "pm.h"
47#include "reset.h"
48#include "sleep.h"
49
50/*
51 * Storage for debug-macro.S's state.
52 *
53 * This must be in .data not .bss so that it gets initialized each time the
54 * kernel is loaded. The data is declared here rather than debug-macro.S so
55 * that multiple inclusions of debug-macro.S point at the same data.
56 */
2f1d70af 57u32 tegra_uart_config[3] = {
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58 /* Debug UART initialization required */
59 1,
60 /* Debug UART physical address */
61 0,
62 /* Debug UART virtual address */
63 0,
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64};
65
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66static void __init tegra_init_early(void)
67{
1a5de3ae 68 of_register_trusted_foundations();
cd198d6d 69 tegra_cpu_reset_handler_init();
6ad27b83 70 call_firmware_op(l2x0_init);
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71}
72
73static void __init tegra_dt_init_irq(void)
74{
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75 tegra_init_irq();
76 irqchip_init();
51100bdc 77}
bab53ce3 78
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79static void __init tegra_dt_init(void)
80{
27a0342a 81 struct device *parent = tegra_soc_device_register();
d591fdf8 82
435ebcbc 83 of_platform_default_populate(NULL, NULL, parent);
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84}
85
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86static void __init tegra_dt_init_late(void)
87{
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88 tegra_init_suspend();
89 tegra_cpuidle_init();
c554dee3 90
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91 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
92 of_machine_is_compatible("compal,paz00"))
93 tegra_paz00_wifikill_init();
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94
95 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
96 of_machine_is_compatible("nvidia,tegra20"))
97 platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
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98}
99
1b14f3a5 100static const char * const tegra_dt_board_compat[] = {
73944475 101 "nvidia,tegra124",
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102 "nvidia,tegra114",
103 "nvidia,tegra30",
c5444f39 104 "nvidia,tegra20",
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105 NULL
106};
107
1b14f3a5 108DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
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109 .l2c_aux_val = 0x3c400001,
110 .l2c_aux_mask = 0xc20fc3fe,
a1725732 111 .smp = smp_ops(tegra_smp_ops),
00123d9a 112 .map_io = tegra_map_common_io,
7469688e 113 .init_early = tegra_init_early,
0d4f7479 114 .init_irq = tegra_dt_init_irq,
8e267f3d 115 .init_machine = tegra_dt_init,
c554dee3 116 .init_late = tegra_dt_init_late,
1b14f3a5 117 .dt_compat = tegra_dt_board_compat,
8e267f3d 118MACHINE_END