[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-tegra / timer.c

/*
 * arch/arch/mach-tegra/timer.c
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/err.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/mach/time.h>
#include <asm/localtimer.h>
#include <asm/sched_clock.h>

#include <mach/iomap.h>
#include <mach/irqs.h>
#include <mach/suspend.h>

#include "board.h"
#include "clock.h"

#define RTC_SECONDS            0x08
#define RTC_SHADOW_SECONDS     0x0c
#define RTC_MILLISECONDS       0x10

#define TIMERUS_CNTR_1US 0x10
#define TIMERUS_USEC_CFG 0x14
#define TIMERUS_CNTR_FREEZE 0x4c

#define TIMER1_BASE 0x0
#define TIMER2_BASE 0x8
#define TIMER3_BASE 0x50
#define TIMER4_BASE 0x58

#define TIMER_PTV 0x0
#define TIMER_PCR 0x4

static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);

static struct timespec persistent_ts;
static u64 persistent_ms, last_persistent_ms;

#define timer_writel(value, reg) \
	__raw_writel(value, timer_reg_base + (reg))
#define timer_readl(reg) \
	__raw_readl(timer_reg_base + (reg))

static int tegra_timer_set_next_event(unsigned long cycles,
					 struct clock_event_device *evt)
{
	u32 reg;

	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
	timer_writel(reg, TIMER3_BASE + TIMER_PTV);

	return 0;
}

static void tegra_timer_set_mode(enum clock_event_mode mode,
				    struct clock_event_device *evt)
{
	u32 reg;

	timer_writel(0, TIMER3_BASE + TIMER_PTV);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		reg = 0xC0000000 | ((1000000/HZ)-1);
		timer_writel(reg, TIMER3_BASE + TIMER_PTV);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device tegra_clockevent = {
	.name		= "timer0",
	.rating		= 300,
	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.set_next_event	= tegra_timer_set_next_event,
	.set_mode	= tegra_timer_set_mode,
};

static u32 notrace tegra_read_sched_clock(void)
{
	return timer_readl(TIMERUS_CNTR_1US);
}

/*
 * tegra_rtc_read - Reads the Tegra RTC registers
 * Care must be taken that this funciton is not called while the
 * tegra_rtc driver could be executing to avoid race conditions
 * on the RTC shadow register
 */
static u64 tegra_rtc_read_ms(void)
{
	u32 ms = readl(rtc_base + RTC_MILLISECONDS);
	u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
	return (u64)s * MSEC_PER_SEC + ms;
}

/*
 * read_persistent_clock -  Return time from a persistent clock.
 *
 * Reads the time from a source which isn't disabled during PM, the
 * 32k sync timer.  Convert the cycles elapsed since last read into
 * nsecs and adds to a monotonically increasing timespec.
 * Care must be taken that this funciton is not called while the
 * tegra_rtc driver could be executing to avoid race conditions
 * on the RTC shadow register
 */
void read_persistent_clock(struct timespec *ts)
{
	u64 delta;
	struct timespec *tsp = &persistent_ts;

	last_persistent_ms = persistent_ms;
	persistent_ms = tegra_rtc_read_ms();
	delta = persistent_ms - last_persistent_ms;

	timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
	*ts = *tsp;
}

static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction tegra_timer_irq = {
	.name		= "timer0",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
	.handler	= tegra_timer_interrupt,
	.dev_id		= &tegra_clockevent,
	.irq		= INT_TMR3,
};

static void __init tegra_init_timer(void)
{
	struct clk *clk;
	unsigned long rate;
	int ret;

	clk = clk_get_sys("timer", NULL);
	if (IS_ERR(clk)) {
		pr_warn("Unable to get timer clock."
			" Assuming 12Mhz input clock.\n");
		rate = 12000000;
	} else {
		clk_enable(clk);
		rate = clk_get_rate(clk);
	}

	/*
	 * rtc registers are used by read_persistent_clock, keep the rtc clock
	 * enabled
	 */
	clk = clk_get_sys("rtc-tegra", NULL);
	if (IS_ERR(clk))
		pr_warn("Unable to get rtc-tegra clock\n");
	else
		clk_enable(clk);

#ifdef CONFIG_HAVE_ARM_TWD
	twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
#endif

	switch (rate) {
	case 12000000:
		timer_writel(0x000b, TIMERUS_USEC_CFG);
		break;
	case 13000000:
		timer_writel(0x000c, TIMERUS_USEC_CFG);
		break;
	case 19200000:
		timer_writel(0x045f, TIMERUS_USEC_CFG);
		break;
	case 26000000:
		timer_writel(0x0019, TIMERUS_USEC_CFG);
		break;
	default:
		WARN(1, "Unknown clock rate");
	}

	setup_sched_clock(tegra_read_sched_clock, 32, 1000000);

	if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
		"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
		printk(KERN_ERR "Failed to register clocksource\n");
		BUG();
	}

	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
	if (ret) {
		printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
		BUG();
	}

	clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
	tegra_clockevent.max_delta_ns =
		clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
	tegra_clockevent.min_delta_ns =
		clockevent_delta2ns(0x1, &tegra_clockevent);
	tegra_clockevent.cpumask = cpu_all_mask;
	tegra_clockevent.irq = tegra_timer_irq.irq;
	clockevents_register_device(&tegra_clockevent);
}

struct sys_timer tegra_timer = {
	.init = tegra_init_timer,
};

#ifdef CONFIG_PM
static u32 usec_config;

void tegra_timer_suspend(void)
{
	usec_config = timer_readl(TIMERUS_USEC_CFG);
}

void tegra_timer_resume(void)
{
	timer_writel(usec_config, TIMERUS_USEC_CFG);
}
#endif
Commit	Line	Data
2d5cd9a3 CC	1	/*
	2	* arch/arch/mach-tegra/timer.c
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	*
	6	* Author:
	7	* Colin Cross <ccross@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/init.h>
62248ae8	21	#include <linux/err.h>
2d5cd9a3 CC	22	#include <linux/time.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/irq.h>
	25	#include <linux/clockchips.h>
	26	#include <linux/clocksource.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
2d5cd9a3	29
2d5cd9a3 CC	30	#include <asm/mach/time.h>
2d5cd9a3 CC	31	#include <asm/localtimer.h>
e3f4c0ab	32	#include <asm/sched_clock.h>
2d5cd9a3 CC	33
	34	#include <mach/iomap.h>
	35	#include <mach/irqs.h>
2ea67fd1	36	#include <mach/suspend.h>
2d5cd9a3 CC	37
	38	#include "board.h"
	39	#include "clock.h"
	40
09361785 CC	41	#define RTC_SECONDS 0x08
	42	#define RTC_SHADOW_SECONDS 0x0c
	43	#define RTC_MILLISECONDS 0x10
	44
2d5cd9a3 CC	45	#define TIMERUS_CNTR_1US 0x10
	46	#define TIMERUS_USEC_CFG 0x14
	47	#define TIMERUS_CNTR_FREEZE 0x4c
	48
	49	#define TIMER1_BASE 0x0
	50	#define TIMER2_BASE 0x8
	51	#define TIMER3_BASE 0x50
	52	#define TIMER4_BASE 0x58
	53
	54	#define TIMER_PTV 0x0
	55	#define TIMER_PCR 0x4
	56
2d5cd9a3	57	static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
09361785 CC	58	static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
	59
	60	static struct timespec persistent_ts;
	61	static u64 persistent_ms, last_persistent_ms;
2d5cd9a3 CC	62
2d5cd9a3 CC	63	#define timer_writel(value, reg) \
75d71166	64	__raw_writel(value, timer_reg_base + (reg))
2d5cd9a3	65	#define timer_readl(reg) \
75d71166	66	__raw_readl(timer_reg_base + (reg))
2d5cd9a3 CC	67
	68	static int tegra_timer_set_next_event(unsigned long cycles,
	69	struct clock_event_device *evt)
	70	{
	71	u32 reg;
	72
	73	reg = 0x80000000 \| ((cycles > 1) ? (cycles-1) : 0);
	74	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
	75
	76	return 0;
	77	}
	78
	79	static void tegra_timer_set_mode(enum clock_event_mode mode,
	80	struct clock_event_device *evt)
	81	{
	82	u32 reg;
	83
	84	timer_writel(0, TIMER3_BASE + TIMER_PTV);
	85
	86	switch (mode) {
	87	case CLOCK_EVT_MODE_PERIODIC:
	88	reg = 0xC0000000 \| ((1000000/HZ)-1);
	89	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
	90	break;
	91	case CLOCK_EVT_MODE_ONESHOT:
	92	break;
	93	case CLOCK_EVT_MODE_UNUSED:
	94	case CLOCK_EVT_MODE_SHUTDOWN:
	95	case CLOCK_EVT_MODE_RESUME:
	96	break;
	97	}
	98	}
	99
2d5cd9a3 CC	100	static struct clock_event_device tegra_clockevent = {
	101	.name = "timer0",
	102	.rating = 300,
	103	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
	104	.set_next_event = tegra_timer_set_next_event,
	105	.set_mode = tegra_timer_set_mode,
	106	};
	107
2f0778af	108	static u32 notrace tegra_read_sched_clock(void)
e3f4c0ab	109	{
2f0778af	110	return timer_readl(TIMERUS_CNTR_1US);
2d5cd9a3 CC	111	}
2d5cd9a3 CC	112
09361785 CC	113	/*
	114	* tegra_rtc_read - Reads the Tegra RTC registers
	115	* Care must be taken that this funciton is not called while the
	116	* tegra_rtc driver could be executing to avoid race conditions
	117	* on the RTC shadow register
	118	*/
b28fba2a	119	static u64 tegra_rtc_read_ms(void)
09361785 CC	120	{
	121	u32 ms = readl(rtc_base + RTC_MILLISECONDS);
	122	u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
	123	return (u64)s * MSEC_PER_SEC + ms;
	124	}
	125
	126	/*
	127	* read_persistent_clock - Return time from a persistent clock.
	128	*
	129	* Reads the time from a source which isn't disabled during PM, the
	130	* 32k sync timer. Convert the cycles elapsed since last read into
	131	* nsecs and adds to a monotonically increasing timespec.
	132	* Care must be taken that this funciton is not called while the
	133	* tegra_rtc driver could be executing to avoid race conditions
	134	* on the RTC shadow register
	135	*/
	136	void read_persistent_clock(struct timespec *ts)
	137	{
	138	u64 delta;
	139	struct timespec *tsp = &persistent_ts;
	140
	141	last_persistent_ms = persistent_ms;
	142	persistent_ms = tegra_rtc_read_ms();
	143	delta = persistent_ms - last_persistent_ms;
	144
	145	timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
	146	ts = tsp;
	147	}
	148
2d5cd9a3 CC	149	static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
	150	{
	151	struct clock_event_device evt = (struct clock_event_device )dev_id;
	152	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
	153	evt->event_handler(evt);
	154	return IRQ_HANDLED;
	155	}
	156
	157	static struct irqaction tegra_timer_irq = {
	158	.name = "timer0",
	159	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_TRIGGER_HIGH,
	160	.handler = tegra_timer_interrupt,
	161	.dev_id = &tegra_clockevent,
	162	.irq = INT_TMR3,
	163	};
	164
	165	static void __init tegra_init_timer(void)
	166	{
62248ae8	167	struct clk *clk;
8e4fab2c	168	unsigned long rate;
2d5cd9a3 CC	169	int ret;
2d5cd9a3 CC	170
62248ae8	171	clk = clk_get_sys("timer", NULL);
8e4fab2c PDS	172	if (IS_ERR(clk)) {
	173	pr_warn("Unable to get timer clock."
	174	" Assuming 12Mhz input clock.\n");
	175	rate = 12000000;
	176	} else {
2d85b5d8	177	clk_enable(clk);
8e4fab2c PDS	178	rate = clk_get_rate(clk);
8e4fab2c PDS	179	}
62248ae8 CC	180
	181	/*
	182	* rtc registers are used by read_persistent_clock, keep the rtc clock
	183	* enabled
	184	*/
	185	clk = clk_get_sys("rtc-tegra", NULL);
2d85b5d8 PDS	186	if (IS_ERR(clk))
	187	pr_warn("Unable to get rtc-tegra clock\n");
	188	else
	189	clk_enable(clk);
62248ae8	190
2d5cd9a3 CC	191	#ifdef CONFIG_HAVE_ARM_TWD
	192	twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
	193	#endif
	194
	195	switch (rate) {
	196	case 12000000:
	197	timer_writel(0x000b, TIMERUS_USEC_CFG);
	198	break;
	199	case 13000000:
	200	timer_writel(0x000c, TIMERUS_USEC_CFG);
	201	break;
	202	case 19200000:
	203	timer_writel(0x045f, TIMERUS_USEC_CFG);
	204	break;
	205	case 26000000:
	206	timer_writel(0x0019, TIMERUS_USEC_CFG);
	207	break;
	208	default:
	209	WARN(1, "Unknown clock rate");
	210	}
	211
2f0778af	212	setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
e3f4c0ab	213
234b6ced RK	214	if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
234b6ced RK	215	"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
2d5cd9a3 CC	216	printk(KERN_ERR "Failed to register clocksource\n");
	217	BUG();
	218	}
	219
	220	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
	221	if (ret) {
	222	printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
	223	BUG();
	224	}
	225
	226	clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
	227	tegra_clockevent.max_delta_ns =
	228	clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
	229	tegra_clockevent.min_delta_ns =
	230	clockevent_delta2ns(0x1, &tegra_clockevent);
	231	tegra_clockevent.cpumask = cpu_all_mask;
	232	tegra_clockevent.irq = tegra_timer_irq.irq;
	233	clockevents_register_device(&tegra_clockevent);
2d5cd9a3 CC	234	}
	235
	236	struct sys_timer tegra_timer = {
	237	.init = tegra_init_timer,
	238	};
09361785 CC	239
	240	#ifdef CONFIG_PM
	241	static u32 usec_config;
	242
	243	void tegra_timer_suspend(void)
	244	{
	245	usec_config = timer_readl(TIMERUS_USEC_CFG);
	246	}
	247
	248	void tegra_timer_resume(void)
	249	{
	250	timer_writel(usec_config, TIMERUS_USEC_CFG);
	251	}
	252	#endif