[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-u300 / timer.c

/*
 *
 * arch/arm/mach-u300/timer.c
 *
 *
 * Copyright (C) 2007-2009 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * Timer COH 901 328, runs the OS timer interrupt.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
 */
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

/* Generic stuff */
#include <asm/mach/map.h>
#include <asm/mach/time.h>

/*
 * APP side special timer registers
 * This timer contains four timers which can fire an interrupt each.
 * OS (operating system) timer @ 32768 Hz
 * DD (device driver) timer @ 1 kHz
 * GP1 (general purpose 1) timer @ 1MHz
 * GP2 (general purpose 2) timer @ 1MHz
 */

/* Reset OS Timer 32bit (-/W) */
#define U300_TIMER_APP_ROST					(0x0000)
#define U300_TIMER_APP_ROST_TIMER_RESET				(0x00000000)
/* Enable OS Timer 32bit (-/W) */
#define U300_TIMER_APP_EOST					(0x0004)
#define U300_TIMER_APP_EOST_TIMER_ENABLE			(0x00000000)
/* Disable OS Timer 32bit (-/W) */
#define U300_TIMER_APP_DOST					(0x0008)
#define U300_TIMER_APP_DOST_TIMER_DISABLE			(0x00000000)
/* OS Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SOSTM					(0x000c)
#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT			(0x00000001)
/* OS Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_OSTS					(0x0010)
#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK			(0x0000000F)
#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE			(0x00000001)
#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE			(0x00000002)
#define U300_TIMER_APP_OSTS_ENABLE_IND				(0x00000010)
#define U300_TIMER_APP_OSTS_MODE_MASK				(0x00000020)
#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT			(0x00000020)
#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND			(0x00000040)
#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND			(0x00000080)
/* OS Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_OSTCC					(0x0014)
/* OS Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_OSTTC					(0x0018)
/* OS Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_OSTIE					(0x001c)
#define U300_TIMER_APP_OSTIE_IRQ_DISABLE			(0x00000000)
#define U300_TIMER_APP_OSTIE_IRQ_ENABLE				(0x00000001)
/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_OSTIA					(0x0020)
#define U300_TIMER_APP_OSTIA_IRQ_ACK				(0x00000080)

/* Reset DD Timer 32bit (-/W) */
#define U300_TIMER_APP_RDDT					(0x0040)
#define U300_TIMER_APP_RDDT_TIMER_RESET				(0x00000000)
/* Enable DD Timer 32bit (-/W) */
#define U300_TIMER_APP_EDDT					(0x0044)
#define U300_TIMER_APP_EDDT_TIMER_ENABLE			(0x00000000)
/* Disable DD Timer 32bit (-/W) */
#define U300_TIMER_APP_DDDT					(0x0048)
#define U300_TIMER_APP_DDDT_TIMER_DISABLE			(0x00000000)
/* DD Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SDDTM					(0x004c)
#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT			(0x00000001)
/* DD Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_DDTS					(0x0050)
#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK			(0x0000000F)
#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE			(0x00000001)
#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE			(0x00000002)
#define U300_TIMER_APP_DDTS_ENABLE_IND				(0x00000010)
#define U300_TIMER_APP_DDTS_MODE_MASK				(0x00000020)
#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT			(0x00000020)
#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND			(0x00000040)
#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND			(0x00000080)
/* DD Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_DDTCC					(0x0054)
/* DD Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_DDTTC					(0x0058)
/* DD Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_DDTIE					(0x005c)
#define U300_TIMER_APP_DDTIE_IRQ_DISABLE			(0x00000000)
#define U300_TIMER_APP_DDTIE_IRQ_ENABLE				(0x00000001)
/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_DDTIA					(0x0060)
#define U300_TIMER_APP_DDTIA_IRQ_ACK				(0x00000080)

/* Reset GP1 Timer 32bit (-/W) */
#define U300_TIMER_APP_RGPT1					(0x0080)
#define U300_TIMER_APP_RGPT1_TIMER_RESET			(0x00000000)
/* Enable GP1 Timer 32bit (-/W) */
#define U300_TIMER_APP_EGPT1					(0x0084)
#define U300_TIMER_APP_EGPT1_TIMER_ENABLE			(0x00000000)
/* Disable GP1 Timer 32bit (-/W) */
#define U300_TIMER_APP_DGPT1					(0x0088)
#define U300_TIMER_APP_DGPT1_TIMER_DISABLE			(0x00000000)
/* GP1 Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SGPT1M					(0x008c)
#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT			(0x00000001)
/* GP1 Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_GPT1S					(0x0090)
#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK			(0x0000000F)
#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE			(0x00000001)
#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE			(0x00000002)
#define U300_TIMER_APP_GPT1S_ENABLE_IND				(0x00000010)
#define U300_TIMER_APP_GPT1S_MODE_MASK				(0x00000020)
#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT			(0x00000020)
#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND			(0x00000040)
#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND			(0x00000080)
/* GP1 Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_GPT1CC					(0x0094)
/* GP1 Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_GPT1TC					(0x0098)
/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_GPT1IE					(0x009c)
#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE			(0x00000000)
#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE			(0x00000001)
/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_GPT1IA					(0x00a0)
#define U300_TIMER_APP_GPT1IA_IRQ_ACK				(0x00000080)

/* Reset GP2 Timer 32bit (-/W) */
#define U300_TIMER_APP_RGPT2					(0x00c0)
#define U300_TIMER_APP_RGPT2_TIMER_RESET			(0x00000000)
/* Enable GP2 Timer 32bit (-/W) */
#define U300_TIMER_APP_EGPT2					(0x00c4)
#define U300_TIMER_APP_EGPT2_TIMER_ENABLE			(0x00000000)
/* Disable GP2 Timer 32bit (-/W) */
#define U300_TIMER_APP_DGPT2					(0x00c8)
#define U300_TIMER_APP_DGPT2_TIMER_DISABLE			(0x00000000)
/* GP2 Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SGPT2M					(0x00cc)
#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT			(0x00000001)
/* GP2 Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_GPT2S					(0x00d0)
#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK			(0x0000000F)
#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE			(0x00000001)
#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE			(0x00000002)
#define U300_TIMER_APP_GPT2S_ENABLE_IND				(0x00000010)
#define U300_TIMER_APP_GPT2S_MODE_MASK				(0x00000020)
#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT			(0x00000020)
#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND			(0x00000040)
#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND			(0x00000080)
/* GP2 Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_GPT2CC					(0x00d4)
/* GP2 Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_GPT2TC					(0x00d8)
/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_GPT2IE					(0x00dc)
#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE			(0x00000000)
#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE			(0x00000001)
/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_GPT2IA					(0x00e0)
#define U300_TIMER_APP_GPT2IA_IRQ_ACK				(0x00000080)

/* Clock request control register - all four timers */
#define U300_TIMER_APP_CRC					(0x100)
#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE			(0x00000001)

#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)

static void __iomem *u300_timer_base;

/*
 * The u300_set_mode() function is always called first, if we
 * have oneshot timer active, the oneshot scheduling function
 * u300_set_next_event() is called immediately after.
 */
static void u300_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* Disable interrupts on GPT1 */
		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Disable GP1 while we're reprogramming it. */
		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
		       u300_timer_base + U300_TIMER_APP_DGPT1);
		/*
		 * Set the periodic mode to a certain number of ticks per
		 * jiffy.
		 */
		writel(TICKS_PER_JIFFY,
		       u300_timer_base + U300_TIMER_APP_GPT1TC);
		/*
		 * Set continuous mode, so the timer keeps triggering
		 * interrupts.
		 */
		writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
		       u300_timer_base + U300_TIMER_APP_SGPT1M);
		/* Enable timer interrupts */
		writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Then enable the OS timer again */
		writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
		       u300_timer_base + U300_TIMER_APP_EGPT1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Just break; here? */
		/*
		 * The actual event will be programmed by the next event hook,
		 * so we just set a dummy value somewhere at the end of the
		 * universe here.
		 */
		/* Disable interrupts on GPT1 */
		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Disable GP1 while we're reprogramming it. */
		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
		       u300_timer_base + U300_TIMER_APP_DGPT1);
		/*
		 * Expire far in the future, u300_set_next_event() will be
		 * called soon...
		 */
		writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
		/* We run one shot per tick here! */
		writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
		       u300_timer_base + U300_TIMER_APP_SGPT1M);
		/* Enable interrupts for this timer */
		writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Enable timer */
		writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
		       u300_timer_base + U300_TIMER_APP_EGPT1);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		/* Disable interrupts on GP1 */
		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Disable GP1 */
		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
		       u300_timer_base + U300_TIMER_APP_DGPT1);
		break;
	case CLOCK_EVT_MODE_RESUME:
		/* Ignore this call */
		break;
	}
}

/*
 * The app timer in one shot mode obviously has to be reprogrammed
 * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
 * the interrupt disable + timer disable commands with a reset command,
 * it will fail miserably. Apparently (and I found this the hard way)
 * the timer is very sensitive to the instruction order, though you don't
 * get that impression from the data sheet.
 */
static int u300_set_next_event(unsigned long cycles,
			       struct clock_event_device *evt)

{
	/* Disable interrupts on GPT1 */
	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
	       u300_timer_base + U300_TIMER_APP_GPT1IE);
	/* Disable GP1 while we're reprogramming it. */
	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
	       u300_timer_base + U300_TIMER_APP_DGPT1);
	/* Reset the General Purpose timer 1. */
	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
	       u300_timer_base + U300_TIMER_APP_RGPT1);
	/* IRQ in n * cycles */
	writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
	/*
	 * We run one shot per tick here! (This is necessary to reconfigure,
	 * the timer will tilt if you don't!)
	 */
	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
	       u300_timer_base + U300_TIMER_APP_SGPT1M);
	/* Enable timer interrupts */
	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
	       u300_timer_base + U300_TIMER_APP_GPT1IE);
	/* Then enable the OS timer again */
	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
	       u300_timer_base + U300_TIMER_APP_EGPT1);
	return 0;
}


/* Use general purpose timer 1 as clock event */
static struct clock_event_device clockevent_u300_1mhz = {
	.name		= "GPT1",
	.rating		= 300, /* Reasonably fast and accurate clock event */
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_next_event	= u300_set_next_event,
	.set_mode	= u300_set_mode,
};

/* Clock event timer interrupt handler */
static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_u300_1mhz;
	/* ACK/Clear timer IRQ for the APP GPT1 Timer */

	writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
		u300_timer_base + U300_TIMER_APP_GPT1IA);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction u300_timer_irq = {
	.name		= "U300 Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= u300_timer_interrupt,
};

/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel. We accept that
 * this wraps around for now, since it is just a relative time
 * stamp. (Inspired by OMAP implementation.)
 */

static u32 notrace u300_read_sched_clock(void)
{
	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
}

static unsigned long u300_read_current_timer(void)
{
	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
}

static struct delay_timer u300_delay_timer;

/*
 * This sets up the system timers, clock source and clock event.
 */
static void __init u300_timer_init_of(struct device_node *np)
{
	struct resource irq_res;
	int irq;
	struct clk *clk;
	unsigned long rate;

	u300_timer_base = of_iomap(np, 0);
	if (!u300_timer_base)
		panic("could not ioremap system timer\n");

	/* Get the IRQ for the GP1 timer */
	irq = of_irq_to_resource(np, 2, &irq_res);
	if (irq <= 0)
		panic("no IRQ for system timer\n");

	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);

	/* Clock the interrupt controller */
	clk = of_clk_get(np, 0);
	BUG_ON(IS_ERR(clk));
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);

	setup_sched_clock(u300_read_sched_clock, 32, rate);

	u300_delay_timer.read_current_timer = &u300_read_current_timer;
	u300_delay_timer.freq = rate;
	register_current_timer_delay(&u300_delay_timer);

	/*
	 * Disable the "OS" and "DD" timers - these are designed for Symbian!
	 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
	 */
	writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
		u300_timer_base + U300_TIMER_APP_CRC);
	writel(U300_TIMER_APP_ROST_TIMER_RESET,
		u300_timer_base + U300_TIMER_APP_ROST);
	writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
		u300_timer_base + U300_TIMER_APP_DOST);
	writel(U300_TIMER_APP_RDDT_TIMER_RESET,
		u300_timer_base + U300_TIMER_APP_RDDT);
	writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
		u300_timer_base + U300_TIMER_APP_DDDT);

	/* Reset the General Purpose timer 1. */
	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
		u300_timer_base + U300_TIMER_APP_RGPT1);

	/* Set up the IRQ handler */
	setup_irq(irq, &u300_timer_irq);

	/* Reset the General Purpose timer 2 */
	writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
		u300_timer_base + U300_TIMER_APP_RGPT2);
	/* Set this timer to run around forever */
	writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
	/* Set continuous mode so it wraps around */
	writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
	       u300_timer_base + U300_TIMER_APP_SGPT2M);
	/* Disable timer interrupts */
	writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
		u300_timer_base + U300_TIMER_APP_GPT2IE);
	/* Then enable the GP2 timer to use as a free running us counter */
	writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
		u300_timer_base + U300_TIMER_APP_EGPT2);

	/* Use general purpose timer 2 as clock source */
	if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
			"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
		pr_err("timer: failed to initialize U300 clock source\n");

	/* Configure and register the clockevent */
	clockevents_config_and_register(&clockevent_u300_1mhz, rate,
					1, 0xffffffff);

	/*
	 * TODO: init and register the rest of the timers too, they can be
	 * used by hrtimers!
	 */
}

CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
		       u300_timer_init_of);
Commit	Line	Data
bb3cee2b LW	1	/*
	2	*
	3	* arch/arm/mach-u300/timer.c
	4	*
	5	*
	6	* Copyright (C) 2007-2009 ST-Ericsson AB
	7	* License terms: GNU General Public License (GPL) version 2
	8	* Timer COH 901 328, runs the OS timer interrupt.
	9	* Author: Linus Walleij <linus.walleij@stericsson.com>
	10	*/
	11	#include <linux/interrupt.h>
	12	#include <linux/time.h>
	13	#include <linux/timex.h>
	14	#include <linux/clockchips.h>
	15	#include <linux/clocksource.h>
	16	#include <linux/types.h>
	17	#include <linux/io.h>
b7276b23 LW	18	#include <linux/clk.h>
b7276b23 LW	19	#include <linux/err.h>
a4fe292f	20	#include <linux/irq.h>
3c96d8ea	21	#include <linux/delay.h>
5a5056cc LW	22	#include <linux/of_address.h>
5a5056cc LW	23	#include <linux/of_irq.h>
38ff87f7	24	#include <linux/sched_clock.h>
bb3cee2b	25
bb3cee2b LW	26	/* Generic stuff */
	27	#include <asm/mach/map.h>
	28	#include <asm/mach/time.h>
bb3cee2b	29
bb3cee2b LW	30	/*
	31	* APP side special timer registers
	32	* This timer contains four timers which can fire an interrupt each.
	33	* OS (operating system) timer @ 32768 Hz
	34	* DD (device driver) timer @ 1 kHz
	35	* GP1 (general purpose 1) timer @ 1MHz
	36	* GP2 (general purpose 2) timer @ 1MHz
	37	*/
	38
	39	/* Reset OS Timer 32bit (-/W) */
	40	#define U300_TIMER_APP_ROST (0x0000)
	41	#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
	42	/* Enable OS Timer 32bit (-/W) */
	43	#define U300_TIMER_APP_EOST (0x0004)
	44	#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
	45	/* Disable OS Timer 32bit (-/W) */
	46	#define U300_TIMER_APP_DOST (0x0008)
	47	#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
	48	/* OS Timer Mode Register 32bit (-/W) */
	49	#define U300_TIMER_APP_SOSTM (0x000c)
	50	#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
	51	#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
	52	/* OS Timer Status Register 32bit (R/-) */
	53	#define U300_TIMER_APP_OSTS (0x0010)
	54	#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
	55	#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
	56	#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
	57	#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
	58	#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
	59	#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
	60	#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
	61	#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
	62	#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
	63	/* OS Timer Current Count Register 32bit (R/-) */
	64	#define U300_TIMER_APP_OSTCC (0x0014)
	65	/* OS Timer Terminal Count Register 32bit (R/W) */
	66	#define U300_TIMER_APP_OSTTC (0x0018)
	67	/* OS Timer Interrupt Enable Register 32bit (-/W) */
	68	#define U300_TIMER_APP_OSTIE (0x001c)
	69	#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
	70	#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
	71	/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
	72	#define U300_TIMER_APP_OSTIA (0x0020)
	73	#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
	74
	75	/* Reset DD Timer 32bit (-/W) */
	76	#define U300_TIMER_APP_RDDT (0x0040)
	77	#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
	78	/* Enable DD Timer 32bit (-/W) */
	79	#define U300_TIMER_APP_EDDT (0x0044)
	80	#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
	81	/* Disable DD Timer 32bit (-/W) */
	82	#define U300_TIMER_APP_DDDT (0x0048)
	83	#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
	84	/* DD Timer Mode Register 32bit (-/W) */
	85	#define U300_TIMER_APP_SDDTM (0x004c)
	86	#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000)
	87	#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001)
	88	/* DD Timer Status Register 32bit (R/-) */
	89	#define U300_TIMER_APP_DDTS (0x0050)
	90	#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F)
	91	#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001)
	92	#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002)
	93	#define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010)
94	#define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020)
95	#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000)
96	#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020)
97	#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040)
98	#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080)
99	/* DD Timer Current Count Register 32bit (R/-) */
100	#define U300_TIMER_APP_DDTCC (0x0054)
101	/* DD Timer Terminal Count Register 32bit (R/W) */
102	#define U300_TIMER_APP_DDTTC (0x0058)
103	/* DD Timer Interrupt Enable Register 32bit (-/W) */
104	#define U300_TIMER_APP_DDTIE (0x005c)
105	#define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000)
106	#define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001)
107	/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
108	#define U300_TIMER_APP_DDTIA (0x0060)
109	#define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080)
110
111	/* Reset GP1 Timer 32bit (-/W) */
112	#define U300_TIMER_APP_RGPT1 (0x0080)
113	#define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000)
114	/* Enable GP1 Timer 32bit (-/W) */
115	#define U300_TIMER_APP_EGPT1 (0x0084)
116	#define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000)
117	/* Disable GP1 Timer 32bit (-/W) */
118	#define U300_TIMER_APP_DGPT1 (0x0088)
119	#define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000)
120	/* GP1 Timer Mode Register 32bit (-/W) */
121	#define U300_TIMER_APP_SGPT1M (0x008c)
122	#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000)
123	#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001)
124	/* GP1 Timer Status Register 32bit (R/-) */
125	#define U300_TIMER_APP_GPT1S (0x0090)
126	#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F)
127	#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001)
128	#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002)
129	#define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010)
130	#define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020)
131	#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000)
132	#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020)
133	#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040)
134	#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080)
135	/* GP1 Timer Current Count Register 32bit (R/-) */
136	#define U300_TIMER_APP_GPT1CC (0x0094)
137	/* GP1 Timer Terminal Count Register 32bit (R/W) */
138	#define U300_TIMER_APP_GPT1TC (0x0098)
139	/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
140	#define U300_TIMER_APP_GPT1IE (0x009c)
141	#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000)
142	#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001)
143	/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
144	#define U300_TIMER_APP_GPT1IA (0x00a0)
145	#define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080)
146
147	/* Reset GP2 Timer 32bit (-/W) */
148	#define U300_TIMER_APP_RGPT2 (0x00c0)
149	#define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000)
150	/* Enable GP2 Timer 32bit (-/W) */
151	#define U300_TIMER_APP_EGPT2 (0x00c4)
152	#define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000)
153	/* Disable GP2 Timer 32bit (-/W) */
154	#define U300_TIMER_APP_DGPT2 (0x00c8)
155	#define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000)
156	/* GP2 Timer Mode Register 32bit (-/W) */
157	#define U300_TIMER_APP_SGPT2M (0x00cc)
158	#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000)
159	#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001)
160	/* GP2 Timer Status Register 32bit (R/-) */
161	#define U300_TIMER_APP_GPT2S (0x00d0)
162	#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F)
163	#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001)
164	#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002)
165	#define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010)
166	#define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020)
167	#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000)
168	#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020)
169	#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040)
170	#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080)
171	/* GP2 Timer Current Count Register 32bit (R/-) */
172	#define U300_TIMER_APP_GPT2CC (0x00d4)
173	/* GP2 Timer Terminal Count Register 32bit (R/W) */
174	#define U300_TIMER_APP_GPT2TC (0x00d8)
175	/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
176	#define U300_TIMER_APP_GPT2IE (0x00dc)
177	#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000)
178	#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001)
179	/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
180	#define U300_TIMER_APP_GPT2IA (0x00e0)
181	#define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080)
182
183	/* Clock request control register - all four timers */
184	#define U300_TIMER_APP_CRC (0x100)
185	#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
186
187	#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
188	#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
189
5a5056cc LW	190	static void __iomem *u300_timer_base;
5a5056cc LW	191
bb3cee2b LW	192	/*
	193	* The u300_set_mode() function is always called first, if we
	194	* have oneshot timer active, the oneshot scheduling function
	195	* u300_set_next_event() is called immediately after.
	196	*/
	197	static void u300_set_mode(enum clock_event_mode mode,
	198	struct clock_event_device *evt)
	199	{
	200	switch (mode) {
	201	case CLOCK_EVT_MODE_PERIODIC:
	202	/* Disable interrupts on GPT1 */
	203	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
5a5056cc	204	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	205	/* Disable GP1 while we're reprogramming it. */
bb3cee2b LW	206	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
5a5056cc	207	u300_timer_base + U300_TIMER_APP_DGPT1);
bb3cee2b LW	208	/*
	209	* Set the periodic mode to a certain number of ticks per
	210	* jiffy.
	211	*/
	212	writel(TICKS_PER_JIFFY,
5a5056cc	213	u300_timer_base + U300_TIMER_APP_GPT1TC);
bb3cee2b LW	214	/*
	215	* Set continuous mode, so the timer keeps triggering
	216	* interrupts.
	217	*/
	218	writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
5a5056cc	219	u300_timer_base + U300_TIMER_APP_SGPT1M);
bb3cee2b LW	220	/* Enable timer interrupts */
bb3cee2b LW	221	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
5a5056cc	222	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	223	/* Then enable the OS timer again */
bb3cee2b LW	224	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
5a5056cc	225	u300_timer_base + U300_TIMER_APP_EGPT1);
bb3cee2b LW	226	break;
	227	case CLOCK_EVT_MODE_ONESHOT:
	228	/* Just break; here? */
	229	/*
	230	* The actual event will be programmed by the next event hook,
	231	* so we just set a dummy value somewhere at the end of the
	232	* universe here.
	233	*/
	234	/* Disable interrupts on GPT1 */
	235	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
5a5056cc	236	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	237	/* Disable GP1 while we're reprogramming it. */
bb3cee2b LW	238	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
5a5056cc	239	u300_timer_base + U300_TIMER_APP_DGPT1);
bb3cee2b LW	240	/*
	241	* Expire far in the future, u300_set_next_event() will be
	242	* called soon...
	243	*/
5a5056cc	244	writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
bb3cee2b LW	245	/* We run one shot per tick here! */
bb3cee2b LW	246	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
5a5056cc	247	u300_timer_base + U300_TIMER_APP_SGPT1M);
bb3cee2b LW	248	/* Enable interrupts for this timer */
bb3cee2b LW	249	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
5a5056cc	250	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	251	/* Enable timer */
bb3cee2b LW	252	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
5a5056cc	253	u300_timer_base + U300_TIMER_APP_EGPT1);
bb3cee2b LW	254	break;
	255	case CLOCK_EVT_MODE_UNUSED:
	256	case CLOCK_EVT_MODE_SHUTDOWN:
	257	/* Disable interrupts on GP1 */
	258	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
5a5056cc	259	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	260	/* Disable GP1 */
bb3cee2b LW	261	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
5a5056cc	262	u300_timer_base + U300_TIMER_APP_DGPT1);
bb3cee2b LW	263	break;
	264	case CLOCK_EVT_MODE_RESUME:
	265	/* Ignore this call */
	266	break;
	267	}
	268	}
	269
	270	/*
	271	* The app timer in one shot mode obviously has to be reprogrammed
	272	* in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
	273	* the interrupt disable + timer disable commands with a reset command,
	274	* it will fail miserably. Apparently (and I found this the hard way)
	275	* the timer is very sensitive to the instruction order, though you don't
	276	* get that impression from the data sheet.
	277	*/
	278	static int u300_set_next_event(unsigned long cycles,
	279	struct clock_event_device *evt)
	280
	281	{
	282	/* Disable interrupts on GPT1 */
	283	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
5a5056cc	284	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	285	/* Disable GP1 while we're reprogramming it. */
bb3cee2b LW	286	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
5a5056cc	287	u300_timer_base + U300_TIMER_APP_DGPT1);
bb3cee2b LW	288	/* Reset the General Purpose timer 1. */
bb3cee2b LW	289	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
5a5056cc	290	u300_timer_base + U300_TIMER_APP_RGPT1);
bb3cee2b	291	/* IRQ in n * cycles */
5a5056cc	292	writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
bb3cee2b LW	293	/*
	294	* We run one shot per tick here! (This is necessary to reconfigure,
	295	* the timer will tilt if you don't!)
	296	*/
	297	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
5a5056cc	298	u300_timer_base + U300_TIMER_APP_SGPT1M);
bb3cee2b LW	299	/* Enable timer interrupts */
bb3cee2b LW	300	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
5a5056cc	301	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	302	/* Then enable the OS timer again */
bb3cee2b LW	303	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
5a5056cc	304	u300_timer_base + U300_TIMER_APP_EGPT1);
bb3cee2b LW	305	return 0;
	306	}
	307
	308
	309	/* Use general purpose timer 1 as clock event */
	310	static struct clock_event_device clockevent_u300_1mhz = {
cde21de1 LW	311	.name = "GPT1",
	312	.rating = 300, /* Reasonably fast and accurate clock event */
	313	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	314	.set_next_event = u300_set_next_event,
	315	.set_mode = u300_set_mode,
bb3cee2b LW	316	};
	317
	318	/* Clock event timer interrupt handler */
	319	static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
	320	{
	321	struct clock_event_device *evt = &clockevent_u300_1mhz;
	322	/* ACK/Clear timer IRQ for the APP GPT1 Timer */
5a5056cc	323
bb3cee2b	324	writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
5a5056cc	325	u300_timer_base + U300_TIMER_APP_GPT1IA);
bb3cee2b LW	326	evt->event_handler(evt);
	327	return IRQ_HANDLED;
	328	}
	329
	330	static struct irqaction u300_timer_irq = {
cde21de1 LW	331	.name = "U300 Timer Tick",
	332	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	333	.handler = u300_timer_interrupt,
bb3cee2b LW	334	};
bb3cee2b LW	335
a2ca00ea LW	336	/*
	337	* Override the global weak sched_clock symbol with this
	338	* local implementation which uses the clocksource to get some
	339	* better resolution when scheduling the kernel. We accept that
	340	* this wraps around for now, since it is just a relative time
	341	* stamp. (Inspired by OMAP implementation.)
	342	*/
5c21b7ca	343
2f0778af	344	static u32 notrace u300_read_sched_clock(void)
a2ca00ea	345	{
5a5056cc	346	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
a2ca00ea LW	347	}
a2ca00ea LW	348
3c96d8ea LW	349	static unsigned long u300_read_current_timer(void)
3c96d8ea LW	350	{
5a5056cc	351	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
3c96d8ea LW	352	}
	353
	354	static struct delay_timer u300_delay_timer;
bb3cee2b LW	355
	356	/*
	357	* This sets up the system timers, clock source and clock event.
	358	*/
75a7f3f1	359	static void __init u300_timer_init_of(struct device_node *np)
bb3cee2b	360	{
75a7f3f1 LW	361	struct resource irq_res;
75a7f3f1 LW	362	int irq;
b7276b23	363	struct clk *clk;
3af8a8da	364	unsigned long rate;
b7276b23	365
75a7f3f1 LW	366	u300_timer_base = of_iomap(np, 0);
	367	if (!u300_timer_base)
	368	panic("could not ioremap system timer\n");
	369
	370	/* Get the IRQ for the GP1 timer */
	371	irq = of_irq_to_resource(np, 2, &irq_res);
	372	if (irq <= 0)
	373	panic("no IRQ for system timer\n");
	374
5a5056cc LW	375	pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
5a5056cc LW	376
b7276b23	377	/* Clock the interrupt controller */
bba5f2cc	378	clk = of_clk_get(np, 0);
b7276b23	379	BUG_ON(IS_ERR(clk));
50667d63	380	clk_prepare_enable(clk);
3af8a8da	381	rate = clk_get_rate(clk);
b7276b23	382
2f0778af	383	setup_sched_clock(u300_read_sched_clock, 32, rate);
5c21b7ca	384
3c96d8ea LW	385	u300_delay_timer.read_current_timer = &u300_read_current_timer;
	386	u300_delay_timer.freq = rate;
	387	register_current_timer_delay(&u300_delay_timer);
	388
bb3cee2b LW	389	/*
	390	* Disable the "OS" and "DD" timers - these are designed for Symbian!
	391	* Example usage in cnh1601578 cpu subsystem pd_timer_app.c
	392	*/
	393	writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
5a5056cc	394	u300_timer_base + U300_TIMER_APP_CRC);
bb3cee2b	395	writel(U300_TIMER_APP_ROST_TIMER_RESET,
5a5056cc	396	u300_timer_base + U300_TIMER_APP_ROST);
bb3cee2b	397	writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
5a5056cc	398	u300_timer_base + U300_TIMER_APP_DOST);
bb3cee2b	399	writel(U300_TIMER_APP_RDDT_TIMER_RESET,
5a5056cc	400	u300_timer_base + U300_TIMER_APP_RDDT);
bb3cee2b	401	writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
5a5056cc	402	u300_timer_base + U300_TIMER_APP_DDDT);
bb3cee2b LW	403
	404	/* Reset the General Purpose timer 1. */
	405	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
5a5056cc	406	u300_timer_base + U300_TIMER_APP_RGPT1);
bb3cee2b LW	407
bb3cee2b LW	408	/* Set up the IRQ handler */
5a5056cc	409	setup_irq(irq, &u300_timer_irq);
bb3cee2b LW	410
	411	/* Reset the General Purpose timer 2 */
	412	writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
5a5056cc	413	u300_timer_base + U300_TIMER_APP_RGPT2);
bb3cee2b	414	/* Set this timer to run around forever */
5a5056cc	415	writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
bb3cee2b LW	416	/* Set continuous mode so it wraps around */
bb3cee2b LW	417	writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
5a5056cc	418	u300_timer_base + U300_TIMER_APP_SGPT2M);
bb3cee2b LW	419	/* Disable timer interrupts */
bb3cee2b LW	420	writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
5a5056cc	421	u300_timer_base + U300_TIMER_APP_GPT2IE);
bb3cee2b LW	422	/* Then enable the GP2 timer to use as a free running us counter */
bb3cee2b LW	423	writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
5a5056cc	424	u300_timer_base + U300_TIMER_APP_EGPT2);
bb3cee2b	425
234b6ced	426	/* Use general purpose timer 2 as clock source */
5a5056cc	427	if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
234b6ced	428	"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
9425032b	429	pr_err("timer: failed to initialize U300 clock source\n");
bb3cee2b	430
cde21de1 LW	431	/* Configure and register the clockevent */
	432	clockevents_config_and_register(&clockevent_u300_1mhz, rate,
	433	1, 0xffffffff);
	434
bb3cee2b LW	435	/*
	436	* TODO: init and register the rest of the timers too, they can be
	437	* used by hrtimers!
	438	*/
	439	}
5a5056cc	440
5a5056cc LW	441	CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
5a5056cc LW	442	u300_timer_init_of);