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aa44ef4d | 1 | /* |
c15def1c | 2 | * Copyright (C) 2008-2009 ST-Ericsson SA |
aa44ef4d SK |
3 | * |
4 | * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2, as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | #include <linux/types.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/amba/bus.h> | |
aa90eb9d | 15 | #include <linux/interrupt.h> |
aa44ef4d SK |
16 | #include <linux/irq.h> |
17 | #include <linux/platform_device.h> | |
cc2c1334 | 18 | #include <linux/io.h> |
aa44ef4d | 19 | |
aa44ef4d | 20 | #include <asm/mach/map.h> |
aa90eb9d | 21 | #include <asm/pmu.h> |
0f332861 | 22 | #include <plat/gpio-nomadik.h> |
aa44ef4d | 23 | #include <mach/hardware.h> |
cc2c1334 | 24 | #include <mach/setup.h> |
5b1f7ddf | 25 | #include <mach/devices.h> |
6f3f3c3f | 26 | #include <mach/usb.h> |
94bdc0e2 | 27 | |
fbf1eadf | 28 | #include "devices-db8500.h" |
6f3f3c3f | 29 | #include "ste-dma40-db8500.h" |
fbf1eadf | 30 | |
aa44ef4d | 31 | /* minimum static i/o mapping required to boot U8500 platforms */ |
abf12d71 | 32 | static struct map_desc u8500_uart_io_desc[] __initdata = { |
92389ca8 RV |
33 | __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), |
34 | __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), | |
abf12d71 RV |
35 | }; |
36 | ||
37 | static struct map_desc u8500_io_desc[] __initdata = { | |
215e83d9 LW |
38 | /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ |
39 | __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), | |
92389ca8 RV |
40 | __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), |
41 | __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), | |
92389ca8 | 42 | __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), |
92389ca8 RV |
43 | __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), |
44 | ||
45 | __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), | |
46 | __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), | |
47 | __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), | |
48 | __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), | |
49 | __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), | |
50 | ||
1df20afc | 51 | __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), |
c9c09572 | 52 | __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), |
94bdc0e2 RV |
53 | __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), |
54 | __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), | |
55 | __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), | |
fcbd458e | 56 | __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), |
75a36ee0 RV |
57 | }; |
58 | ||
abf12d71 | 59 | void __init u8500_map_io(void) |
f946738c | 60 | { |
abf12d71 RV |
61 | /* |
62 | * Map the UARTs early so that the DEBUG_LL stuff continues to work. | |
63 | */ | |
64 | iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); | |
f946738c | 65 | |
abf12d71 | 66 | ux500_map_io(); |
f946738c | 67 | |
aa44ef4d | 68 | iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); |
75a36ee0 | 69 | |
11871890 | 70 | _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); |
aa44ef4d SK |
71 | } |
72 | ||
aa90eb9d RV |
73 | static struct resource db8500_pmu_resources[] = { |
74 | [0] = { | |
75 | .start = IRQ_DB8500_PMU, | |
76 | .end = IRQ_DB8500_PMU, | |
77 | .flags = IORESOURCE_IRQ, | |
78 | }, | |
79 | }; | |
80 | ||
81 | /* | |
82 | * The PMU IRQ lines of two cores are wired together into a single interrupt. | |
83 | * Bounce the interrupt to the other core if it's not ours. | |
84 | */ | |
85 | static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) | |
86 | { | |
87 | irqreturn_t ret = handler(irq, dev); | |
88 | int other = !smp_processor_id(); | |
89 | ||
90 | if (ret == IRQ_NONE && cpu_online(other)) | |
91 | irq_set_affinity(irq, cpumask_of(other)); | |
92 | ||
93 | /* | |
94 | * We should be able to get away with the amount of IRQ_NONEs we give, | |
95 | * while still having the spurious IRQ detection code kick in if the | |
96 | * interrupt really starts hitting spuriously. | |
97 | */ | |
98 | return ret; | |
99 | } | |
100 | ||
101 | static struct arm_pmu_platdata db8500_pmu_platdata = { | |
102 | .handle_irq = db8500_pmu_handler, | |
103 | }; | |
104 | ||
105 | static struct platform_device db8500_pmu_device = { | |
106 | .name = "arm-pmu", | |
107 | .id = ARM_PMU_DEVICE_CPU, | |
108 | .num_resources = ARRAY_SIZE(db8500_pmu_resources), | |
109 | .resource = db8500_pmu_resources, | |
110 | .dev.platform_data = &db8500_pmu_platdata, | |
111 | }; | |
112 | ||
3df57bcf MN |
113 | static struct platform_device db8500_prcmu_device = { |
114 | .name = "db8500-prcmu", | |
115 | }; | |
116 | ||
aa90eb9d RV |
117 | static struct platform_device *platform_devs[] __initdata = { |
118 | &u8500_dma40_device, | |
119 | &db8500_pmu_device, | |
3df57bcf | 120 | &db8500_prcmu_device, |
aa90eb9d RV |
121 | }; |
122 | ||
01afdd13 RV |
123 | static resource_size_t __initdata db8500_gpio_base[] = { |
124 | U8500_GPIOBANK0_BASE, | |
125 | U8500_GPIOBANK1_BASE, | |
126 | U8500_GPIOBANK2_BASE, | |
127 | U8500_GPIOBANK3_BASE, | |
128 | U8500_GPIOBANK4_BASE, | |
129 | U8500_GPIOBANK5_BASE, | |
130 | U8500_GPIOBANK6_BASE, | |
131 | U8500_GPIOBANK7_BASE, | |
132 | U8500_GPIOBANK8_BASE, | |
133 | }; | |
134 | ||
18403424 | 135 | static void __init db8500_add_gpios(struct device *parent) |
01afdd13 RV |
136 | { |
137 | struct nmk_gpio_platform_data pdata = { | |
c15def1c | 138 | .supports_sleepmode = true, |
01afdd13 RV |
139 | }; |
140 | ||
18403424 | 141 | dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), |
01afdd13 RV |
142 | IRQ_DB8500_GPIO0, &pdata); |
143 | } | |
144 | ||
6f3f3c3f MYK |
145 | static int usb_db8500_rx_dma_cfg[] = { |
146 | DB8500_DMA_DEV38_USB_OTG_IEP_1_9, | |
147 | DB8500_DMA_DEV37_USB_OTG_IEP_2_10, | |
148 | DB8500_DMA_DEV36_USB_OTG_IEP_3_11, | |
149 | DB8500_DMA_DEV19_USB_OTG_IEP_4_12, | |
150 | DB8500_DMA_DEV18_USB_OTG_IEP_5_13, | |
151 | DB8500_DMA_DEV17_USB_OTG_IEP_6_14, | |
152 | DB8500_DMA_DEV16_USB_OTG_IEP_7_15, | |
153 | DB8500_DMA_DEV39_USB_OTG_IEP_8 | |
154 | }; | |
155 | ||
156 | static int usb_db8500_tx_dma_cfg[] = { | |
157 | DB8500_DMA_DEV38_USB_OTG_OEP_1_9, | |
158 | DB8500_DMA_DEV37_USB_OTG_OEP_2_10, | |
159 | DB8500_DMA_DEV36_USB_OTG_OEP_3_11, | |
160 | DB8500_DMA_DEV19_USB_OTG_OEP_4_12, | |
161 | DB8500_DMA_DEV18_USB_OTG_OEP_5_13, | |
162 | DB8500_DMA_DEV17_USB_OTG_OEP_6_14, | |
163 | DB8500_DMA_DEV16_USB_OTG_OEP_7_15, | |
164 | DB8500_DMA_DEV39_USB_OTG_OEP_8 | |
165 | }; | |
166 | ||
aa44ef4d SK |
167 | /* |
168 | * This function is called from the board init | |
169 | */ | |
18403424 | 170 | struct device* __init u8500_init_devices(void) |
aa44ef4d | 171 | { |
18403424 LJ |
172 | db8500_add_rtc(NULL); |
173 | db8500_add_gpios(NULL); | |
174 | db8500_add_usb(NULL, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); | |
fbf1eadf | 175 | |
7c1a70e9 | 176 | platform_device_register_simple("cpufreq-u8500", -1, NULL, 0); |
aa44ef4d SK |
177 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); |
178 | ||
18403424 LJ |
179 | /* FIXME: Return value to be a real parent. */ |
180 | return NULL; | |
aa44ef4d | 181 | } |