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[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-versatile / core.c
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1da177e4
LT		 1/*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
1da177e4
LT		 21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/dma-mapping.h>
d052d1be 24#include <linux/platform_device.h>
1da177e4
LT		 25#include <linux/sysdev.h>
26#include <linux/interrupt.h>
a62c80e5
RK		 27#include <linux/amba/bus.h>
28#include <linux/amba/clcd.h>
bbeddc43 29#include <linux/amba/pl061.h>
6ef297f8 30#include <linux/amba/mmci.h>
b49c87c2 31#include <linux/clocksource.h>
89df1272 32#include <linux/clockchips.h>
b4f151ff 33#include <linux/cnt32_to_63.h>
fced80c7 34#include <linux/io.h>
5a0e3ad6 35#include <linux/gfp.h>
1da177e4 36
71a06da0 37#include <asm/clkdev.h>
1da177e4 38#include <asm/system.h>
a09e64fb 39#include <mach/hardware.h>
1da177e4
LT		 40#include <asm/irq.h>
41#include <asm/leds.h>
b720f732 42#include <asm/hardware/arm_timer.h>
1da177e4 43#include <asm/hardware/icst307.h>
fa0fe48f 44#include <asm/hardware/vic.h>
dc5bc8f1 45#include <asm/mach-types.h>
1da177e4
LT		 46
47#include <asm/mach/arch.h>
48#include <asm/mach/flash.h>
49#include <asm/mach/irq.h>
50#include <asm/mach/time.h>
51#include <asm/mach/map.h>
1da177e4
LT		 52
53#include "core.h"
54#include "clock.h"
55
56/*
57 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
58 * is the (PA >> 12).
59 *
60 * Setup a VA for the Versatile Vectored Interrupt Controller.
61 */
2ad4f86b
AV		 62#define __io_address(n) __io(IO_ADDRESS(n))
63#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
64#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
1da177e4 65
1da177e4
LT		 66static void sic_mask_irq(unsigned int irq)
67{
68 irq -= IRQ_SIC_START;
69 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
70}
71
72static void sic_unmask_irq(unsigned int irq)
73{
74 irq -= IRQ_SIC_START;
75 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
76}
77
38c677cb
DB		 78static struct irq_chip sic_chip = {
79 .name = "SIC",
1da177e4
LT		 80 .ack = sic_mask_irq,
81 .mask = sic_mask_irq,
82 .unmask = sic_unmask_irq,
83};
84
85static void
10dd5ce2 86sic_handle_irq(unsigned int irq, struct irq_desc *desc)
1da177e4
LT		 87{
88 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
89
90 if (status == 0) {
0cd61b68 91 do_bad_IRQ(irq, desc);
1da177e4
LT		 92 return;
93 }
94
95 do {
96 irq = ffs(status) - 1;
97 status &= ~(1 << irq);
98
99 irq += IRQ_SIC_START;
100
d8aa0251 101 generic_handle_irq(irq);
1da177e4
LT		 102 } while (status);
103}
104
105#if 1
106#define IRQ_MMCI0A IRQ_VICSOURCE22
107#define IRQ_AACI IRQ_VICSOURCE24
108#define IRQ_ETH IRQ_VICSOURCE25
109#define PIC_MASK 0xFFD00000
110#else
111#define IRQ_MMCI0A IRQ_SIC_MMCI0A
112#define IRQ_AACI IRQ_SIC_AACI
113#define IRQ_ETH IRQ_SIC_ETH
114#define PIC_MASK 0
115#endif
116
117void __init versatile_init_irq(void)
118{
fa0fe48f 119 unsigned int i;
1da177e4 120
c07f87f2 121 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
1da177e4 122
56f1319e 123 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
1da177e4
LT		 124
125 /* Do second interrupt controller */
126 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
127
128 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
129 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
130 set_irq_chip(i, &sic_chip);
10dd5ce2 131 set_irq_handler(i, handle_level_irq);
1da177e4
LT		 132 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
133 }
134 }
135
136 /*
137 * Interrupts on secondary controller from 0 to 8 are routed to
138 * source 31 on PIC.
139 * Interrupts from 21 to 31 are routed directly to the VIC on
140 * the corresponding number on primary controller. This is controlled
141 * by setting PIC_ENABLEx.
142 */
143 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
144}
145
146static struct map_desc versatile_io_desc[] __initdata = {
1311521f
DS		 147 {
148 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
149 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
150 .length = SZ_4K,
151 .type = MT_DEVICE
152 }, {
153 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
154 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
155 .length = SZ_4K,
156 .type = MT_DEVICE
157 }, {
158 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
159 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
160 .length = SZ_4K,
161 .type = MT_DEVICE
162 }, {
163 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
164 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
165 .length = SZ_4K * 9,
166 .type = MT_DEVICE
167 },
1da177e4 168#ifdef CONFIG_MACH_VERSATILE_AB
1311521f
DS		 169 {
170 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
171 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
172 .length = SZ_4K,
173 .type = MT_DEVICE
174 }, {
175 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
176 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
177 .length = SZ_64M,
178 .type = MT_DEVICE
179 },
1da177e4
LT		 180#endif
181#ifdef CONFIG_DEBUG_LL
1311521f
DS		 182 {
183 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
184 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
185 .length = SZ_4K,
186 .type = MT_DEVICE
187 },
1da177e4 188#endif
c0da085a 189#ifdef CONFIG_PCI
1311521f
DS		 190 {
191 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
192 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
193 .length = SZ_4K,
194 .type = MT_DEVICE
195 }, {
399ad77b 196 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
1311521f
DS		 197 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
198 .length = VERSATILE_PCI_BASE_SIZE,
199 .type = MT_DEVICE
200 }, {
399ad77b 201 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
1311521f
DS		 202 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
203 .length = VERSATILE_PCI_CFG_BASE_SIZE,
204 .type = MT_DEVICE
205 },
c0da085a 206#if 0
1311521f
DS		 207 {
208 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
209 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
210 .length = SZ_16M,
211 .type = MT_DEVICE
212 }, {
213 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
214 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
215 .length = SZ_16M,
216 .type = MT_DEVICE
217 }, {
218 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
219 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
220 .length = SZ_16M,
221 .type = MT_DEVICE
222 },
c0da085a 223#endif
1da177e4
LT		 224#endif
225};
226
227void __init versatile_map_io(void)
228{
229 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
230}
231
2ad4f86b 232#define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
1da177e4
LT		 233
234/*
235 * This is the Versatile sched_clock implementation. This has
752bee17
NP		 236 * a resolution of 41.7ns, and a maximum value of about 35583 days.
237 *
238 * The return value is guaranteed to be monotonic in that range as
239 * long as there is always less than 89 seconds between successive
240 * calls to this function.
1da177e4
LT		 241 */
242unsigned long long sched_clock(void)
243{
752bee17 244 unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
1da177e4 245
752bee17
NP		 246 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
247 v *= 125<<1;
248 do_div(v, 3<<1);
1da177e4
LT		 249
250 return v;
251}
252
253
2ad4f86b 254#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
1da177e4
LT		 255
256static int versatile_flash_init(void)
257{
258 u32 val;
259
260 val = __raw_readl(VERSATILE_FLASHCTRL);
261 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
262 __raw_writel(val, VERSATILE_FLASHCTRL);
263
264 return 0;
265}
266
267static void versatile_flash_exit(void)
268{
269 u32 val;
270
271 val = __raw_readl(VERSATILE_FLASHCTRL);
272 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
273 __raw_writel(val, VERSATILE_FLASHCTRL);
274}
275
276static void versatile_flash_set_vpp(int on)
277{
278 u32 val;
279
280 val = __raw_readl(VERSATILE_FLASHCTRL);
281 if (on)
282 val |= VERSATILE_FLASHPROG_FLVPPEN;
283 else
284 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
285 __raw_writel(val, VERSATILE_FLASHCTRL);
286}
287
288static struct flash_platform_data versatile_flash_data = {
289 .map_name = "cfi_probe",
290 .width = 4,
291 .init = versatile_flash_init,
292 .exit = versatile_flash_exit,
293 .set_vpp = versatile_flash_set_vpp,
294};
295
296static struct resource versatile_flash_resource = {
297 .start = VERSATILE_FLASH_BASE,
a0c5a645 298 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
1da177e4
LT		 299 .flags = IORESOURCE_MEM,
300};
301
302static struct platform_device versatile_flash_device = {
303 .name = "armflash",
304 .id = 0,
305 .dev = {
306 .platform_data = &versatile_flash_data,
307 },
308 .num_resources = 1,
309 .resource = &versatile_flash_resource,
310};
311
312static struct resource smc91x_resources[] = {
313 [0] = {
314 .start = VERSATILE_ETH_BASE,
315 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
316 .flags = IORESOURCE_MEM,
317 },
318 [1] = {
319 .start = IRQ_ETH,
320 .end = IRQ_ETH,
321 .flags = IORESOURCE_IRQ,
322 },
323};
324
325static struct platform_device smc91x_device = {
326 .name = "smc91x",
327 .id = 0,
328 .num_resources = ARRAY_SIZE(smc91x_resources),
329 .resource = smc91x_resources,
330};
331
6b65cd74
RK		 332static struct resource versatile_i2c_resource = {
333 .start = VERSATILE_I2C_BASE,
334 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
335 .flags = IORESOURCE_MEM,
336};
337
338static struct platform_device versatile_i2c_device = {
339 .name = "versatile-i2c",
533ad5e6 340 .id = 0,
6b65cd74
RK		 341 .num_resources = 1,
342 .resource = &versatile_i2c_resource,
343};
344
533ad5e6
CM		 345static struct i2c_board_info versatile_i2c_board_info[] = {
346 {
64e8be6e 347 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6
CM		 348 },
349};
350
351static int __init versatile_i2c_init(void)
352{
353 return i2c_register_board_info(0, versatile_i2c_board_info,
354 ARRAY_SIZE(versatile_i2c_board_info));
355}
356arch_initcall(versatile_i2c_init);
357
2ad4f86b 358#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
1da177e4
LT		 359
360unsigned int mmc_status(struct device *dev)
361{
362 struct amba_device *adev = container_of(dev, struct amba_device, dev);
363 u32 mask;
364
365 if (adev->res.start == VERSATILE_MMCI0_BASE)
366 mask = 1;
367 else
368 mask = 2;
369
370 return readl(VERSATILE_SYSMCI) & mask;
371}
372
6ef297f8 373static struct mmci_platform_data mmc0_plat_data = {
1da177e4
LT		 374 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
375 .status = mmc_status,
7fb2bbf4
RK		 376 .gpio_wp = -1,
377 .gpio_cd = -1,
1da177e4
LT		 378};
379
380/*
381 * Clock handling
382 */
383static const struct icst307_params versatile_oscvco_params = {
384 .ref = 24000,
385 .vco_max = 200000,
386 .vd_min = 4 + 8,
387 .vd_max = 511 + 8,
388 .rd_min = 1 + 2,
389 .rd_max = 127 + 2,
390};
391
392static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
393{
71a06da0
RK		 394 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
395 void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
1da177e4
LT		 396 u32 val;
397
71a06da0 398 val = readl(sys + clk->oscoff) & ~0x7ffff;
1da177e4
LT		 399 val |= vco.v | (vco.r << 9) | (vco.s << 16);
400
401 writel(0xa05f, sys_lock);
71a06da0 402 writel(val, sys + clk->oscoff);
1da177e4
LT		 403 writel(0, sys_lock);
404}
405
71a06da0 406static struct clk osc4_clk = {
1da177e4 407 .params = &versatile_oscvco_params,
71a06da0
RK		 408 .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
409 .setvco = versatile_oscvco_set,
410};
411
412/*
413 * These are fixed clocks.
414 */
415static struct clk ref24_clk = {
416 .rate = 24000000,
417};
418
982db663 419static struct clk_lookup lookups[] = {
71a06da0
RK		 420 { /* UART0 */
421 .dev_id = "dev:f1",
422 .clk = &ref24_clk,
423 }, { /* UART1 */
424 .dev_id = "dev:f2",
425 .clk = &ref24_clk,
426 }, { /* UART2 */
427 .dev_id = "dev:f3",
428 .clk = &ref24_clk,
429 }, { /* UART3 */
430 .dev_id = "fpga:09",
431 .clk = &ref24_clk,
432 }, { /* KMI0 */
433 .dev_id = "fpga:06",
434 .clk = &ref24_clk,
435 }, { /* KMI1 */
436 .dev_id = "fpga:07",
437 .clk = &ref24_clk,
438 }, { /* MMC0 */
439 .dev_id = "fpga:05",
440 .clk = &ref24_clk,
441 }, { /* MMC1 */
442 .dev_id = "fpga:0b",
443 .clk = &ref24_clk,
444 }, { /* CLCD */
445 .dev_id = "dev:20",
446 .clk = &osc4_clk,
447 }
1da177e4
LT		 448};
449
450/*
451 * CLCD support.
452 */
453#define SYS_CLCD_MODE_MASK (3 << 0)
454#define SYS_CLCD_MODE_888 (0 << 0)
455#define SYS_CLCD_MODE_5551 (1 << 0)
456#define SYS_CLCD_MODE_565_RLSB (2 << 0)
457#define SYS_CLCD_MODE_565_BLSB (3 << 0)
458#define SYS_CLCD_NLCDIOON (1 << 2)
459#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
460#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
461#define SYS_CLCD_ID_MASK (0x1f << 8)
462#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
463#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
464#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
465#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
466#define SYS_CLCD_ID_VGA (0x1f << 8)
467
468static struct clcd_panel vga = {
469 .mode = {
470 .name = "VGA",
471 .refresh = 60,
472 .xres = 640,
473 .yres = 480,
474 .pixclock = 39721,
475 .left_margin = 40,
476 .right_margin = 24,
477 .upper_margin = 32,
478 .lower_margin = 11,
479 .hsync_len = 96,
480 .vsync_len = 2,
481 .sync = 0,
482 .vmode = FB_VMODE_NONINTERLACED,
483 },
484 .width = -1,
485 .height = -1,
486 .tim2 = TIM2_BCD | TIM2_IPC,
487 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
488 .bpp = 16,
489};
490
491static struct clcd_panel sanyo_3_8_in = {
492 .mode = {
493 .name = "Sanyo QVGA",
494 .refresh = 116,
495 .xres = 320,
496 .yres = 240,
497 .pixclock = 100000,
498 .left_margin = 6,
499 .right_margin = 6,
500 .upper_margin = 5,
501 .lower_margin = 5,
502 .hsync_len = 6,
503 .vsync_len = 6,
504 .sync = 0,
505 .vmode = FB_VMODE_NONINTERLACED,
506 },
507 .width = -1,
508 .height = -1,
509 .tim2 = TIM2_BCD,
510 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
511 .bpp = 16,
512};
513
514static struct clcd_panel sanyo_2_5_in = {
515 .mode = {
516 .name = "Sanyo QVGA Portrait",
517 .refresh = 116,
518 .xres = 240,
519 .yres = 320,
520 .pixclock = 100000,
521 .left_margin = 20,
522 .right_margin = 10,
523 .upper_margin = 2,
524 .lower_margin = 2,
525 .hsync_len = 10,
526 .vsync_len = 2,
527 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
528 .vmode = FB_VMODE_NONINTERLACED,
529 },
530 .width = -1,
531 .height = -1,
532 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
533 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
534 .bpp = 16,
535};
536
537static struct clcd_panel epson_2_2_in = {
538 .mode = {
539 .name = "Epson QCIF",
540 .refresh = 390,
541 .xres = 176,
542 .yres = 220,
543 .pixclock = 62500,
544 .left_margin = 3,
545 .right_margin = 2,
546 .upper_margin = 1,
547 .lower_margin = 0,
548 .hsync_len = 3,
549 .vsync_len = 2,
550 .sync = 0,
551 .vmode = FB_VMODE_NONINTERLACED,
552 },
553 .width = -1,
554 .height = -1,
555 .tim2 = TIM2_BCD | TIM2_IPC,
556 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
557 .bpp = 16,
558};
559
560/*
561 * Detect which LCD panel is connected, and return the appropriate
562 * clcd_panel structure. Note: we do not have any information on
563 * the required timings for the 8.4in panel, so we presently assume
564 * VGA timings.
565 */
566static struct clcd_panel *versatile_clcd_panel(void)
567{
2ad4f86b 568 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 569 struct clcd_panel *panel = &vga;
570 u32 val;
571
572 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
573 if (val == SYS_CLCD_ID_SANYO_3_8)
574 panel = &sanyo_3_8_in;
575 else if (val == SYS_CLCD_ID_SANYO_2_5)
576 panel = &sanyo_2_5_in;
577 else if (val == SYS_CLCD_ID_EPSON_2_2)
578 panel = &epson_2_2_in;
579 else if (val == SYS_CLCD_ID_VGA)
580 panel = &vga;
581 else {
582 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
583 val);
584 panel = &vga;
585 }
586
587 return panel;
588}
589
590/*
591 * Disable all display connectors on the interface module.
592 */
593static void versatile_clcd_disable(struct clcd_fb *fb)
594{
2ad4f86b 595 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 596 u32 val;
597
598 val = readl(sys_clcd);
599 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
600 writel(val, sys_clcd);
601
602#ifdef CONFIG_MACH_VERSATILE_AB
603 /*
604 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
605 */
dc5bc8f1 606 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 607 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 608 unsigned long ctrl;
609
610 ctrl = readl(versatile_ib2_ctrl);
611 ctrl &= ~0x01;
612 writel(ctrl, versatile_ib2_ctrl);
613 }
614#endif
615}
616
617/*
618 * Enable the relevant connector on the interface module.
619 */
620static void versatile_clcd_enable(struct clcd_fb *fb)
621{
2ad4f86b 622 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 623 u32 val;
624
625 val = readl(sys_clcd);
626 val &= ~SYS_CLCD_MODE_MASK;
627
628 switch (fb->fb.var.green.length) {
629 case 5:
630 val |= SYS_CLCD_MODE_5551;
631 break;
632 case 6:
90ef713b 633 val |= SYS_CLCD_MODE_565_RLSB;
1da177e4
LT		 634 break;
635 case 8:
636 val |= SYS_CLCD_MODE_888;
637 break;
638 }
639
640 /*
641 * Set the MUX
642 */
643 writel(val, sys_clcd);
644
645 /*
646 * And now enable the PSUs
647 */
648 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
649 writel(val, sys_clcd);
650
651#ifdef CONFIG_MACH_VERSATILE_AB
652 /*
653 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
654 */
dc5bc8f1 655 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 656 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 657 unsigned long ctrl;
658
659 ctrl = readl(versatile_ib2_ctrl);
660 ctrl |= 0x01;
661 writel(ctrl, versatile_ib2_ctrl);
662 }
663#endif
664}
665
666static unsigned long framesize = SZ_1M;
667
668static int versatile_clcd_setup(struct clcd_fb *fb)
669{
670 dma_addr_t dma;
671
672 fb->panel = versatile_clcd_panel();
673
674 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
675 &dma, GFP_KERNEL);
676 if (!fb->fb.screen_base) {
677 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
678 return -ENOMEM;
679 }
680
681 fb->fb.fix.smem_start = dma;
682 fb->fb.fix.smem_len = framesize;
683
684 return 0;
685}
686
687static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
688{
689 return dma_mmap_writecombine(&fb->dev->dev, vma,
690 fb->fb.screen_base,
691 fb->fb.fix.smem_start,
692 fb->fb.fix.smem_len);
693}
694
695static void versatile_clcd_remove(struct clcd_fb *fb)
696{
697 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
698 fb->fb.screen_base, fb->fb.fix.smem_start);
699}
700
701static struct clcd_board clcd_plat_data = {
702 .name = "Versatile",
703 .check = clcdfb_check,
704 .decode = clcdfb_decode,
705 .disable = versatile_clcd_disable,
706 .enable = versatile_clcd_enable,
707 .setup = versatile_clcd_setup,
708 .mmap = versatile_clcd_mmap,
709 .remove = versatile_clcd_remove,
710};
711
bbeddc43
RK		 712static struct pl061_platform_data gpio0_plat_data = {
713 .gpio_base = 0,
714 .irq_base = IRQ_GPIO0_START,
715};
716
717static struct pl061_platform_data gpio1_plat_data = {
718 .gpio_base = 8,
719 .irq_base = IRQ_GPIO1_START,
720};
721
1da177e4
LT		 722#define AACI_IRQ { IRQ_AACI, NO_IRQ }
723#define AACI_DMA { 0x80, 0x81 }
724#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
725#define MMCI0_DMA { 0x84, 0 }
726#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
727#define KMI0_DMA { 0, 0 }
728#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
729#define KMI1_DMA { 0, 0 }
730
731/*
732 * These devices are connected directly to the multi-layer AHB switch
733 */
734#define SMC_IRQ { NO_IRQ, NO_IRQ }
735#define SMC_DMA { 0, 0 }
736#define MPMC_IRQ { NO_IRQ, NO_IRQ }
737#define MPMC_DMA { 0, 0 }
738#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
739#define CLCD_DMA { 0, 0 }
740#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
741#define DMAC_DMA { 0, 0 }
742
743/*
744 * These devices are connected via the core APB bridge
745 */
746#define SCTL_IRQ { NO_IRQ, NO_IRQ }
747#define SCTL_DMA { 0, 0 }
748#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
749#define WATCHDOG_DMA { 0, 0 }
750#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
751#define GPIO0_DMA { 0, 0 }
752#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
753#define GPIO1_DMA { 0, 0 }
754#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
755#define RTC_DMA { 0, 0 }
756
757/*
758 * These devices are connected via the DMA APB bridge
759 */
760#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
761#define SCI_DMA { 7, 6 }
762#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
763#define UART0_DMA { 15, 14 }
764#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
765#define UART1_DMA { 13, 12 }
766#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
767#define UART2_DMA { 11, 10 }
768#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
769#define SSP_DMA { 9, 8 }
770
771/* FPGA Primecells */
772AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
773AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
774AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
775AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
776
777/* DevChip Primecells */
778AMBA_DEVICE(smc, "dev:00", SMC, NULL);
779AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
780AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
781AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
782AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
783AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
bbeddc43
RK		 784AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
785AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
1da177e4
LT		 786AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
787AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
788AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
789AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
790AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
791AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
792
793static struct amba_device *amba_devs[] __initdata = {
794 &dmac_device,
795 &uart0_device,
796 &uart1_device,
797 &uart2_device,
798 &smc_device,
799 &mpmc_device,
800 &clcd_device,
801 &sctl_device,
802 &wdog_device,
803 &gpio0_device,
804 &gpio1_device,
805 &rtc_device,
806 &sci0_device,
807 &ssp0_device,
808 &aaci_device,
809 &mmc0_device,
810 &kmi0_device,
811 &kmi1_device,
812};
813
814#ifdef CONFIG_LEDS
2ad4f86b 815#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
1da177e4
LT		 816
817static void versatile_leds_event(led_event_t ledevt)
818{
819 unsigned long flags;
820 u32 val;
821
822 local_irq_save(flags);
823 val = readl(VA_LEDS_BASE);
824
825 switch (ledevt) {
826 case led_idle_start:
827 val = val & ~VERSATILE_SYS_LED0;
828 break;
829
830 case led_idle_end:
831 val = val | VERSATILE_SYS_LED0;
832 break;
833
834 case led_timer:
835 val = val ^ VERSATILE_SYS_LED1;
836 break;
837
838 case led_halted:
839 val = 0;
840 break;
841
842 default:
843 break;
844 }
845
846 writel(val, VA_LEDS_BASE);
847 local_irq_restore(flags);
848}
849#endif /* CONFIG_LEDS */
850
851void __init versatile_init(void)
852{
853 int i;
854
0a0300dc 855 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1da177e4
LT		 856
857 platform_device_register(&versatile_flash_device);
6b65cd74 858 platform_device_register(&versatile_i2c_device);
1da177e4
LT		 859 platform_device_register(&smc91x_device);
860
861 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
862 struct amba_device *d = amba_devs[i];
863 amba_device_register(d, &iomem_resource);
864 }
865
866#ifdef CONFIG_LEDS
867 leds_event = versatile_leds_event;
868#endif
869}
870
871/*
872 * Where is the timer (VA)?
873 */
2ad4f86b
AV		 874#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
875#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
876#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
877#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
878#define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
1da177e4
LT		 879
880/*
881 * How long is the timer interval?
882 */
883#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
884#if TIMER_INTERVAL >= 0x100000
b720f732
RK		 885#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
886#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
1da177e4
LT		 887#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
888#elif TIMER_INTERVAL >= 0x10000
889#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
b720f732 890#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
1da177e4
LT		 891#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
892#else
893#define TIMER_RELOAD (TIMER_INTERVAL)
b720f732 894#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
1da177e4
LT		 895#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
896#endif
897
89df1272
KH		 898static void timer_set_mode(enum clock_event_mode mode,
899 struct clock_event_device *clk)
900{
901 unsigned long ctrl;
902
903 switch(mode) {
904 case CLOCK_EVT_MODE_PERIODIC:
905 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
906
907 ctrl = TIMER_CTRL_PERIODIC;
908 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
909 break;
910 case CLOCK_EVT_MODE_ONESHOT:
911 /* period set, and timer enabled in 'next_event' hook */
912 ctrl = TIMER_CTRL_ONESHOT;
913 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
914 break;
915 case CLOCK_EVT_MODE_UNUSED:
916 case CLOCK_EVT_MODE_SHUTDOWN:
917 default:
918 ctrl = 0;
919 }
920
921 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
922}
923
924static int timer_set_next_event(unsigned long evt,
925 struct clock_event_device *unused)
926{
927 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
928
929 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
930 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
931
932 return 0;
933}
934
935static struct clock_event_device timer0_clockevent = {
936 .name = "timer0",
937 .shift = 32,
938 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
939 .set_mode = timer_set_mode,
940 .set_next_event = timer_set_next_event,
941};
942
1da177e4
LT		 943/*
944 * IRQ handler for the timer
945 */
0cd61b68 946static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
1da177e4 947{
89df1272 948 struct clock_event_device *evt = &timer0_clockevent;
1da177e4 949
b720f732 950 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
1da177e4 951
89df1272 952 evt->event_handler(evt);
1da177e4
LT		 953
954 return IRQ_HANDLED;
955}
956
957static struct irqaction versatile_timer_irq = {
958 .name = "Versatile Timer Tick",
b30fabad 959 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
09b8b5f8 960 .handler = versatile_timer_interrupt,
1da177e4
LT		 961};
962
8e19608e 963static cycle_t versatile_get_cycles(struct clocksource *cs)
b49c87c2
KH		 964{
965 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
966}
967
968static struct clocksource clocksource_versatile = {
969 .name = "timer3",
970 .rating = 200,
971 .read = versatile_get_cycles,
972 .mask = CLOCKSOURCE_MASK(32),
973 .shift = 20,
974 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
975};
976
977static int __init versatile_clocksource_init(void)
978{
979 /* setup timer3 as free-running clocksource */
980 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
981 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
982 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
983 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
984 TIMER3_VA_BASE + TIMER_CTRL);
985
986 clocksource_versatile.mult =
987 clocksource_khz2mult(1000, clocksource_versatile.shift);
988 clocksource_register(&clocksource_versatile);
989
990 return 0;
991}
992
1da177e4
LT		 993/*
994 * Set up timer interrupt, and return the current time in seconds.
995 */
996static void __init versatile_timer_init(void)
997{
b720f732 998 u32 val;
1da177e4
LT		 999
1000 /*
1001 * set clock frequency:
1002 * VERSATILE_REFCLK is 32KHz
1003 * VERSATILE_TIMCLK is 1MHz
1004 */
2ad4f86b 1005 val = readl(__io_address(VERSATILE_SCTL_BASE));
b720f732
RK		 1006 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
1007 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
1008 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
1009 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
2ad4f86b 1010 __io_address(VERSATILE_SCTL_BASE));
1da177e4
LT		 1011
1012 /*
1013 * Initialise to a known state (all timers off)
1014 */
b720f732
RK		 1015 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
1016 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
1017 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
1018 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
1019
1da177e4
LT		 1020 /*
1021 * Make irqs happen for the system timer
1022 */
1023 setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
b49c87c2
KH		 1024
1025 versatile_clocksource_init();
89df1272
KH		 1026
1027 timer0_clockevent.mult =
1028 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
1029 timer0_clockevent.max_delta_ns =
1030 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1031 timer0_clockevent.min_delta_ns =
1032 clockevent_delta2ns(0xf, &timer0_clockevent);
1033
320ab2b0 1034 timer0_clockevent.cpumask = cpumask_of(0);
89df1272 1035 clockevents_register_device(&timer0_clockevent);
1da177e4
LT		 1036}
1037
1038struct sys_timer versatile_timer = {
1039 .init = versatile_timer_init,
1da177e4 1040};
b49c87c2 1041
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