[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-vexpress / ct-ca9x4.c

/*
 * Versatile Express Core Tile Cortex A9x4 Support
 */
#include <linux/init.h>
#include <linux/gfp.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/clkdev.h>

#include <asm/pgtable.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/pmu.h>
#include <asm/smp_twd.h>

#include <mach/ct-ca9x4.h>

#include <plat/timer-sp.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "core.h"

#include <mach/motherboard.h>

#define V2M_PA_CS7	0x10000000

static struct map_desc ct_ca9x4_io_desc[] __initdata = {
	{
		.virtual	= __MMIO_P2V(CT_CA9X4_MPIC),
		.pfn		= __phys_to_pfn(CT_CA9X4_MPIC),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
		.pfn		= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= __MMIO_P2V(CT_CA9X4_L2CC),
		.pfn		= __phys_to_pfn(CT_CA9X4_L2CC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static void __init ct_ca9x4_map_io(void)
{
	twd_base = MMIO_P2V(A9_MPCORE_TWD);
	v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}

void __iomem *gic_cpu_base_addr;

static void __init ct_ca9x4_init_irq(void)
{
	gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
	gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
	gic_cpu_init(0, gic_cpu_base_addr);
}

#if 0
static void __init ct_ca9x4_timer_init(void)
{
	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);

	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
}

static struct sys_timer ct_ca9x4_timer = {
	.init	= ct_ca9x4_timer_init,
};
#endif

static struct clcd_panel xvga_panel = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15384,
		.left_margin	= 168,
		.right_margin	= 8,
		.upper_margin	= 29,
		.lower_margin	= 3,
		.hsync_len	= 144,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
	v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
}

static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize = 1024 * 768 * 2;
	dma_addr_t dma;

	fb->panel = &xvga_panel;

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
				&dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map frame buffer\n");
		return -ENOMEM;
	}
	fb->fb.fix.smem_start = dma;
	fb->fb.fix.smem_len = framesize;

	return 0;
}

static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
		fb->fb.fix.smem_start, fb->fb.fix.smem_len);
}

static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
		fb->fb.screen_base, fb->fb.fix.smem_start);
}

static struct clcd_board ct_ca9x4_clcd_data = {
	.name		= "CT-CA9X4",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= ct_ca9x4_clcd_enable,
	.setup		= ct_ca9x4_clcd_setup,
	.mmap		= ct_ca9x4_clcd_mmap,
	.remove		= ct_ca9x4_clcd_remove,
};

static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);

static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
	&clcd_device,
	&dmc_device,
	&smc_device,
	&gpio_device,
};


static long ct_round(struct clk *clk, unsigned long rate)
{
	return rate;
}

static int ct_set(struct clk *clk, unsigned long rate)
{
	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
}

static const struct clk_ops osc1_clk_ops = {
	.round	= ct_round,
	.set	= ct_set,
};

static struct clk osc1_clk = {
	.ops	= &osc1_clk_ops,
	.rate	= 24000000,
};

static struct clk_lookup lookups[] = {
	{	/* CLCD */
		.dev_id		= "ct:clcd",
		.clk		= &osc1_clk,
	},
};

static struct resource pmu_resources[] = {
	[0] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU0,
		.end	= IRQ_CT_CA9X4_PMU_CPU0,
		.flags	= IORESOURCE_IRQ,
	},
	[1] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU1,
		.end	= IRQ_CT_CA9X4_PMU_CPU1,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU2,
		.end	= IRQ_CT_CA9X4_PMU_CPU2,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU3,
		.end	= IRQ_CT_CA9X4_PMU_CPU3,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device pmu_device = {
	.name		= "arm-pmu",
	.id		= ARM_PMU_DEVICE_CPU,
	.num_resources	= ARRAY_SIZE(pmu_resources),
	.resource	= pmu_resources,
};

static void __init ct_ca9x4_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);

	/* set RAM latencies to 1 cycle for this core tile. */
	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);

	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
#endif

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
		amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);

	platform_device_register(&pmu_device);
}

MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
	.boot_params	= PHYS_OFFSET + 0x00000100,
	.map_io		= ct_ca9x4_map_io,
	.init_irq	= ct_ca9x4_init_irq,
#if 0
	.timer		= &ct_ca9x4_timer,
#else
	.timer		= &v2m_timer,
#endif
	.init_machine	= ct_ca9x4_init,
MACHINE_END
Commit	Line	Data
fef88f10 RK	1	/*
	2	* Versatile Express Core Tile Cortex A9x4 Support
	3	*/
	4	#include <linux/init.h>
68aaae9e	5	#include <linux/gfp.h>
fef88f10 RK	6	#include <linux/device.h>
fef88f10 RK	7	#include <linux/dma-mapping.h>
f417cbad	8	#include <linux/platform_device.h>
fef88f10 RK	9	#include <linux/amba/bus.h>
fef88f10 RK	10	#include <linux/amba/clcd.h>
6d803ba7	11	#include <linux/clkdev.h>
fef88f10	12
cf0bb91b	13	#include <asm/pgtable.h>
fef88f10 RK	14	#include <asm/hardware/arm_timer.h>
	15	#include <asm/hardware/cache-l2x0.h>
	16	#include <asm/hardware/gic.h>
	17	#include <asm/mach-types.h>
f417cbad	18	#include <asm/pmu.h>
bde28b84	19	#include <asm/smp_twd.h>
fef88f10	20
fef88f10 RK	21	#include <mach/ct-ca9x4.h>
	22
	23	#include <plat/timer-sp.h>
	24
	25	#include <asm/mach/arch.h>
	26	#include <asm/mach/map.h>
	27	#include <asm/mach/time.h>
	28
	29	#include "core.h"
	30
	31	#include <mach/motherboard.h>
	32
	33	#define V2M_PA_CS7 0x10000000
	34
	35	static struct map_desc ct_ca9x4_io_desc[] __initdata = {
	36	{
	37	.virtual = __MMIO_P2V(CT_CA9X4_MPIC),
	38	.pfn = __phys_to_pfn(CT_CA9X4_MPIC),
	39	.length = SZ_16K,
	40	.type = MT_DEVICE,
	41	}, {
	42	.virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
	43	.pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
	44	.length = SZ_4K,
	45	.type = MT_DEVICE,
	46	}, {
	47	.virtual = __MMIO_P2V(CT_CA9X4_L2CC),
	48	.pfn = __phys_to_pfn(CT_CA9X4_L2CC),
	49	.length = SZ_4K,
	50	.type = MT_DEVICE,
	51	},
	52	};
	53
	54	static void __init ct_ca9x4_map_io(void)
	55	{
bde28b84	56	twd_base = MMIO_P2V(A9_MPCORE_TWD);
fef88f10 RK	57	v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
	58	}
	59
	60	void __iomem *gic_cpu_base_addr;
	61
	62	static void __init ct_ca9x4_init_irq(void)
	63	{
	64	gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
	65	gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
	66	gic_cpu_init(0, gic_cpu_base_addr);
	67	}
	68
	69	#if 0
cdaf9a2f	70	static void __init ct_ca9x4_timer_init(void)
fef88f10 RK	71	{
	72	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
	73	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
	74
	75	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
	76	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
	77	}
	78
	79	static struct sys_timer ct_ca9x4_timer = {
	80	.init = ct_ca9x4_timer_init,
	81	};
	82	#endif
	83
	84	static struct clcd_panel xvga_panel = {
	85	.mode = {
	86	.name = "XVGA",
	87	.refresh = 60,
	88	.xres = 1024,
	89	.yres = 768,
	90	.pixclock = 15384,
	91	.left_margin = 168,
	92	.right_margin = 8,
	93	.upper_margin = 29,
	94	.lower_margin = 3,
	95	.hsync_len = 144,
	96	.vsync_len = 6,
	97	.sync = 0,
	98	.vmode = FB_VMODE_NONINTERLACED,
	99	},
	100	.width = -1,
	101	.height = -1,
	102	.tim2 = TIM2_BCD \| TIM2_IPC,
	103	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
	104	.bpp = 16,
	105	};
	106
	107	static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
	108	{
	109	v2m_cfg_write(SYS_CFG_MUXFPGA \| SYS_CFG_SITE_DB1, 0);
	110	v2m_cfg_write(SYS_CFG_DVIMODE \| SYS_CFG_SITE_DB1, 2);
	111	}
	112
	113	static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
	114	{
	115	unsigned long framesize = 1024 * 768 * 2;
	116	dma_addr_t dma;
	117
	118	fb->panel = &xvga_panel;
	119
	120	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
	121	&dma, GFP_KERNEL);
	122	if (!fb->fb.screen_base) {
	123	printk(KERN_ERR "CLCD: unable to map frame buffer\n");
	124	return -ENOMEM;
	125	}
	126	fb->fb.fix.smem_start = dma;
	127	fb->fb.fix.smem_len = framesize;
	128
	129	return 0;
	130	}
	131
	132	static int ct_ca9x4_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	133	{
	134	return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
135	fb->fb.fix.smem_start, fb->fb.fix.smem_len);
136	}
137
138	static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
139	{
140	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
141	fb->fb.screen_base, fb->fb.fix.smem_start);
142	}
143
144	static struct clcd_board ct_ca9x4_clcd_data = {
145	.name = "CT-CA9X4",
146	.check = clcdfb_check,
147	.decode = clcdfb_decode,
148	.enable = ct_ca9x4_clcd_enable,
149	.setup = ct_ca9x4_clcd_setup,
150	.mmap = ct_ca9x4_clcd_mmap,
151	.remove = ct_ca9x4_clcd_remove,
152	};
153
154	static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
155	static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
156	static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
157	static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
158
159	static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
160	&clcd_device,
161	&dmc_device,
162	&smc_device,
163	&gpio_device,
164	};
165
166
167	static long ct_round(struct clk *clk, unsigned long rate)
168	{
169	return rate;
170	}
171
172	static int ct_set(struct clk *clk, unsigned long rate)
173	{
174	return v2m_cfg_write(SYS_CFG_OSC \| SYS_CFG_SITE_DB1 \| 1, rate);
175	}
176
177	static const struct clk_ops osc1_clk_ops = {
178	.round = ct_round,
179	.set = ct_set,
180	};
181
182	static struct clk osc1_clk = {
183	.ops = &osc1_clk_ops,
184	.rate = 24000000,
185	};
186
187	static struct clk_lookup lookups[] = {
188	{ /* CLCD */
189	.dev_id = "ct:clcd",
190	.clk = &osc1_clk,
191	},
192	};
193
f417cbad WD	194	static struct resource pmu_resources[] = {
	195	[0] = {
	196	.start = IRQ_CT_CA9X4_PMU_CPU0,
	197	.end = IRQ_CT_CA9X4_PMU_CPU0,
	198	.flags = IORESOURCE_IRQ,
	199	},
	200	[1] = {
	201	.start = IRQ_CT_CA9X4_PMU_CPU1,
	202	.end = IRQ_CT_CA9X4_PMU_CPU1,
	203	.flags = IORESOURCE_IRQ,
	204	},
	205	[2] = {
	206	.start = IRQ_CT_CA9X4_PMU_CPU2,
	207	.end = IRQ_CT_CA9X4_PMU_CPU2,
	208	.flags = IORESOURCE_IRQ,
	209	},
	210	[3] = {
	211	.start = IRQ_CT_CA9X4_PMU_CPU3,
	212	.end = IRQ_CT_CA9X4_PMU_CPU3,
	213	.flags = IORESOURCE_IRQ,
	214	},
	215	};
	216
	217	static struct platform_device pmu_device = {
	218	.name = "arm-pmu",
	219	.id = ARM_PMU_DEVICE_CPU,
	220	.num_resources = ARRAY_SIZE(pmu_resources),
	221	.resource = pmu_resources,
	222	};
	223
cdaf9a2f	224	static void __init ct_ca9x4_init(void)
fef88f10 RK	225	{
	226	int i;
	227
	228	#ifdef CONFIG_CACHE_L2X0
2de59fea WD	229	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
	230
	231	/* set RAM latencies to 1 cycle for this core tile. */
	232	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
	233	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
	234
	235	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
fef88f10 RK	236	#endif
	237
	238	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
	239
	240	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
	241	amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
f417cbad WD	242
f417cbad WD	243	platform_device_register(&pmu_device);
fef88f10 RK	244	}
	245
	246	MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
fef88f10 RK	247	.boot_params = PHYS_OFFSET + 0x00000100,
	248	.map_io = ct_ca9x4_map_io,
	249	.init_irq = ct_ca9x4_init_irq,
	250	#if 0
	251	.timer = &ct_ca9x4_timer,
	252	#else
	253	.timer = &v2m_timer,
	254	#endif
	255	.init_machine = ct_ca9x4_init,
	256	MACHINE_END