[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-vexpress / ct-ca9x4.c

/*
 * Versatile Express Core Tile Cortex A9x4 Support
 */
#include <linux/init.h>
#include <linux/gfp.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/clkdev.h>

#include <asm/pgtable.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/pmu.h>
#include <asm/smp_twd.h>

#include <mach/ct-ca9x4.h>

#include <asm/hardware/timer-sp.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "core.h"

#include <mach/motherboard.h>

#define V2M_PA_CS7	0x10000000

static struct map_desc ct_ca9x4_io_desc[] __initdata = {
	{
		.virtual	= __MMIO_P2V(CT_CA9X4_MPIC),
		.pfn		= __phys_to_pfn(CT_CA9X4_MPIC),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
		.pfn		= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= __MMIO_P2V(CT_CA9X4_L2CC),
		.pfn		= __phys_to_pfn(CT_CA9X4_L2CC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static void __init ct_ca9x4_map_io(void)
{
#ifdef CONFIG_LOCAL_TIMERS
	twd_base = MMIO_P2V(A9_MPCORE_TWD);
#endif
	v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}

static void __init ct_ca9x4_init_irq(void)
{
	gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
		 MMIO_P2V(A9_MPCORE_GIC_CPU));
}

#if 0
static void __init ct_ca9x4_timer_init(void)
{
	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);

	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
}

static struct sys_timer ct_ca9x4_timer = {
	.init	= ct_ca9x4_timer_init,
};
#endif

static struct clcd_panel xvga_panel = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15384,
		.left_margin	= 168,
		.right_margin	= 8,
		.upper_margin	= 29,
		.lower_margin	= 3,
		.hsync_len	= 144,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
	v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
}

static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize = 1024 * 768 * 2;
	dma_addr_t dma;

	fb->panel = &xvga_panel;

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
				&dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map frame buffer\n");
		return -ENOMEM;
	}
	fb->fb.fix.smem_start = dma;
	fb->fb.fix.smem_len = framesize;

	return 0;
}

static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
		fb->fb.fix.smem_start, fb->fb.fix.smem_len);
}

static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
		fb->fb.screen_base, fb->fb.fix.smem_start);
}

static struct clcd_board ct_ca9x4_clcd_data = {
	.name		= "CT-CA9X4",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= ct_ca9x4_clcd_enable,
	.setup		= ct_ca9x4_clcd_setup,
	.mmap		= ct_ca9x4_clcd_mmap,
	.remove		= ct_ca9x4_clcd_remove,
};

static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);

static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
	&clcd_device,
	&dmc_device,
	&smc_device,
	&gpio_device,
};


static long ct_round(struct clk *clk, unsigned long rate)
{
	return rate;
}

static int ct_set(struct clk *clk, unsigned long rate)
{
	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
}

static const struct clk_ops osc1_clk_ops = {
	.round	= ct_round,
	.set	= ct_set,
};

static struct clk osc1_clk = {
	.ops	= &osc1_clk_ops,
	.rate	= 24000000,
};

static struct clk_lookup lookups[] = {
	{	/* CLCD */
		.dev_id		= "ct:clcd",
		.clk		= &osc1_clk,
	},
};

static struct resource pmu_resources[] = {
	[0] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU0,
		.end	= IRQ_CT_CA9X4_PMU_CPU0,
		.flags	= IORESOURCE_IRQ,
	},
	[1] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU1,
		.end	= IRQ_CT_CA9X4_PMU_CPU1,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU2,
		.end	= IRQ_CT_CA9X4_PMU_CPU2,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU3,
		.end	= IRQ_CT_CA9X4_PMU_CPU3,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device pmu_device = {
	.name		= "arm-pmu",
	.id		= ARM_PMU_DEVICE_CPU,
	.num_resources	= ARRAY_SIZE(pmu_resources),
	.resource	= pmu_resources,
};

static void __init ct_ca9x4_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);

	/* set RAM latencies to 1 cycle for this core tile. */
	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);

	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
#endif

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
		amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);

	platform_device_register(&pmu_device);
}

MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
	.boot_params	= PLAT_PHYS_OFFSET + 0x00000100,
	.map_io		= ct_ca9x4_map_io,
	.init_irq	= ct_ca9x4_init_irq,
#if 0
	.timer		= &ct_ca9x4_timer,
#else
	.timer		= &v2m_timer,
#endif
	.init_machine	= ct_ca9x4_init,
MACHINE_END
Commit	Line	Data
fef88f10 RK	1	/*
	2	* Versatile Express Core Tile Cortex A9x4 Support
	3	*/
	4	#include <linux/init.h>
68aaae9e	5	#include <linux/gfp.h>
fef88f10 RK	6	#include <linux/device.h>
fef88f10 RK	7	#include <linux/dma-mapping.h>
f417cbad	8	#include <linux/platform_device.h>
fef88f10 RK	9	#include <linux/amba/bus.h>
fef88f10 RK	10	#include <linux/amba/clcd.h>
6d803ba7	11	#include <linux/clkdev.h>
fef88f10	12
cf0bb91b	13	#include <asm/pgtable.h>
fef88f10 RK	14	#include <asm/hardware/arm_timer.h>
	15	#include <asm/hardware/cache-l2x0.h>
	16	#include <asm/hardware/gic.h>
	17	#include <asm/mach-types.h>
f417cbad	18	#include <asm/pmu.h>
bde28b84	19	#include <asm/smp_twd.h>
fef88f10	20
fef88f10 RK	21	#include <mach/ct-ca9x4.h>
fef88f10 RK	22
8a9618f5	23	#include <asm/hardware/timer-sp.h>
fef88f10 RK	24
	25	#include <asm/mach/arch.h>
	26	#include <asm/mach/map.h>
	27	#include <asm/mach/time.h>
	28
	29	#include "core.h"
	30
	31	#include <mach/motherboard.h>
	32
	33	#define V2M_PA_CS7 0x10000000
	34
	35	static struct map_desc ct_ca9x4_io_desc[] __initdata = {
	36	{
	37	.virtual = __MMIO_P2V(CT_CA9X4_MPIC),
	38	.pfn = __phys_to_pfn(CT_CA9X4_MPIC),
	39	.length = SZ_16K,
	40	.type = MT_DEVICE,
	41	}, {
	42	.virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
	43	.pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
	44	.length = SZ_4K,
	45	.type = MT_DEVICE,
	46	}, {
	47	.virtual = __MMIO_P2V(CT_CA9X4_L2CC),
	48	.pfn = __phys_to_pfn(CT_CA9X4_L2CC),
	49	.length = SZ_4K,
	50	.type = MT_DEVICE,
	51	},
	52	};
	53
	54	static void __init ct_ca9x4_map_io(void)
	55	{
e56c010f	56	#ifdef CONFIG_LOCAL_TIMERS
bde28b84	57	twd_base = MMIO_P2V(A9_MPCORE_TWD);
e56c010f	58	#endif
fef88f10 RK	59	v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
	60	}
	61
fef88f10 RK	62	static void __init ct_ca9x4_init_irq(void)
fef88f10 RK	63	{
ff2e27ae RK	64	gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
ff2e27ae RK	65	MMIO_P2V(A9_MPCORE_GIC_CPU));
fef88f10 RK	66	}
	67
	68	#if 0
cdaf9a2f	69	static void __init ct_ca9x4_timer_init(void)
fef88f10 RK	70	{
	71	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
	72	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
	73
	74	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
	75	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
	76	}
	77
	78	static struct sys_timer ct_ca9x4_timer = {
	79	.init = ct_ca9x4_timer_init,
	80	};
	81	#endif
	82
	83	static struct clcd_panel xvga_panel = {
	84	.mode = {
	85	.name = "XVGA",
	86	.refresh = 60,
	87	.xres = 1024,
	88	.yres = 768,
	89	.pixclock = 15384,
	90	.left_margin = 168,
	91	.right_margin = 8,
	92	.upper_margin = 29,
	93	.lower_margin = 3,
	94	.hsync_len = 144,
	95	.vsync_len = 6,
	96	.sync = 0,
	97	.vmode = FB_VMODE_NONINTERLACED,
	98	},
	99	.width = -1,
	100	.height = -1,
	101	.tim2 = TIM2_BCD \| TIM2_IPC,
	102	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
	103	.bpp = 16,
	104	};
	105
	106	static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
	107	{
	108	v2m_cfg_write(SYS_CFG_MUXFPGA \| SYS_CFG_SITE_DB1, 0);
	109	v2m_cfg_write(SYS_CFG_DVIMODE \| SYS_CFG_SITE_DB1, 2);
	110	}
	111
	112	static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
	113	{
	114	unsigned long framesize = 1024 * 768 * 2;
	115	dma_addr_t dma;
	116
	117	fb->panel = &xvga_panel;
	118
	119	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
	120	&dma, GFP_KERNEL);
	121	if (!fb->fb.screen_base) {
	122	printk(KERN_ERR "CLCD: unable to map frame buffer\n");
	123	return -ENOMEM;
	124	}
	125	fb->fb.fix.smem_start = dma;
	126	fb->fb.fix.smem_len = framesize;
	127
	128	return 0;
	129	}
	130
	131	static int ct_ca9x4_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	132	{
	133	return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
134	fb->fb.fix.smem_start, fb->fb.fix.smem_len);
135	}
136
137	static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
138	{
139	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
140	fb->fb.screen_base, fb->fb.fix.smem_start);
141	}
142
143	static struct clcd_board ct_ca9x4_clcd_data = {
144	.name = "CT-CA9X4",
145	.check = clcdfb_check,
146	.decode = clcdfb_decode,
147	.enable = ct_ca9x4_clcd_enable,
148	.setup = ct_ca9x4_clcd_setup,
149	.mmap = ct_ca9x4_clcd_mmap,
150	.remove = ct_ca9x4_clcd_remove,
151	};
152
153	static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
154	static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
155	static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
156	static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
157
158	static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
159	&clcd_device,
160	&dmc_device,
161	&smc_device,
162	&gpio_device,
163	};
164
165
166	static long ct_round(struct clk *clk, unsigned long rate)
167	{
168	return rate;
169	}
170
171	static int ct_set(struct clk *clk, unsigned long rate)
172	{
173	return v2m_cfg_write(SYS_CFG_OSC \| SYS_CFG_SITE_DB1 \| 1, rate);
174	}
175
176	static const struct clk_ops osc1_clk_ops = {
177	.round = ct_round,
178	.set = ct_set,
179	};
180
181	static struct clk osc1_clk = {
182	.ops = &osc1_clk_ops,
183	.rate = 24000000,
184	};
185
186	static struct clk_lookup lookups[] = {
187	{ /* CLCD */
188	.dev_id = "ct:clcd",
189	.clk = &osc1_clk,
190	},
191	};
192
f417cbad WD	193	static struct resource pmu_resources[] = {
	194	[0] = {
	195	.start = IRQ_CT_CA9X4_PMU_CPU0,
	196	.end = IRQ_CT_CA9X4_PMU_CPU0,
	197	.flags = IORESOURCE_IRQ,
	198	},
	199	[1] = {
	200	.start = IRQ_CT_CA9X4_PMU_CPU1,
	201	.end = IRQ_CT_CA9X4_PMU_CPU1,
	202	.flags = IORESOURCE_IRQ,
	203	},
	204	[2] = {
	205	.start = IRQ_CT_CA9X4_PMU_CPU2,
	206	.end = IRQ_CT_CA9X4_PMU_CPU2,
	207	.flags = IORESOURCE_IRQ,
	208	},
	209	[3] = {
	210	.start = IRQ_CT_CA9X4_PMU_CPU3,
	211	.end = IRQ_CT_CA9X4_PMU_CPU3,
	212	.flags = IORESOURCE_IRQ,
	213	},
	214	};
	215
	216	static struct platform_device pmu_device = {
	217	.name = "arm-pmu",
	218	.id = ARM_PMU_DEVICE_CPU,
	219	.num_resources = ARRAY_SIZE(pmu_resources),
	220	.resource = pmu_resources,
	221	};
	222
cdaf9a2f	223	static void __init ct_ca9x4_init(void)
fef88f10 RK	224	{
	225	int i;
	226
	227	#ifdef CONFIG_CACHE_L2X0
2de59fea WD	228	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
	229
	230	/* set RAM latencies to 1 cycle for this core tile. */
	231	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
	232	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
	233
	234	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
fef88f10 RK	235	#endif
	236
	237	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
	238
	239	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
	240	amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
f417cbad WD	241
f417cbad WD	242	platform_device_register(&pmu_device);
fef88f10 RK	243	}
	244
	245	MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
b75c178a	246	.boot_params = PLAT_PHYS_OFFSET + 0x00000100,
fef88f10 RK	247	.map_io = ct_ca9x4_map_io,
	248	.init_irq = ct_ca9x4_init_irq,
	249	#if 0
	250	.timer = &ct_ca9x4_timer,
	251	#else
	252	.timer = &v2m_timer,
	253	#endif
	254	.init_machine = ct_ca9x4_init,
	255	MACHINE_END