[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-vexpress / spc.c

/*
 * Versatile Express Serial Power Controller (SPC) support
 *
 * Copyright (C) 2013 ARM Ltd.
 *
 * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
 *          Achin Gupta           <achin.gupta@arm.com>
 *          Lorenzo Pieralisi     <lorenzo.pieralisi@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/semaphore.h>

#include <asm/cacheflush.h>

#define SPCLOG "vexpress-spc: "

#define PERF_LVL_A15		0x00
#define PERF_REQ_A15		0x04
#define PERF_LVL_A7		0x08
#define PERF_REQ_A7		0x0c
#define COMMS			0x10
#define COMMS_REQ		0x14
#define PWC_STATUS		0x18
#define PWC_FLAG		0x1c

/* SPC wake-up IRQs status and mask */
#define WAKE_INT_MASK		0x24
#define WAKE_INT_RAW		0x28
#define WAKE_INT_STAT		0x2c
/* SPC power down registers */
#define A15_PWRDN_EN		0x30
#define A7_PWRDN_EN		0x34
/* SPC per-CPU mailboxes */
#define A15_BX_ADDR0		0x68
#define A7_BX_ADDR0		0x78

/* SPC CPU/cluster reset statue */
#define STANDBYWFI_STAT		0x3c
#define STANDBYWFI_STAT_A15_CPU_MASK(cpu)	(1 << (cpu))
#define STANDBYWFI_STAT_A7_CPU_MASK(cpu)	(1 << (3 + (cpu)))

/* SPC system config interface registers */
#define SYSCFG_WDATA		0x70
#define SYSCFG_RDATA		0x74

/* A15/A7 OPP virtual register base */
#define A15_PERFVAL_BASE	0xC10
#define A7_PERFVAL_BASE		0xC30

/* Config interface control bits */
#define SYSCFG_START		(1 << 31)
#define SYSCFG_SCC		(6 << 20)
#define SYSCFG_STAT		(14 << 20)

/* wake-up interrupt masks */
#define GBL_WAKEUP_INT_MSK	(0x3 << 10)

/* TC2 static dual-cluster configuration */
#define MAX_CLUSTERS		2

/*
 * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
 * operation, the operation could start just before jiffie is about
 * to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz
 */
#define TIMEOUT_US	20000

#define MAX_OPPS	8
#define CA15_DVFS	0
#define CA7_DVFS	1
#define SPC_SYS_CFG	2
#define STAT_COMPLETE(type)	((1 << 0) << (type << 2))
#define STAT_ERR(type)		((1 << 1) << (type << 2))
#define RESPONSE_MASK(type)	(STAT_COMPLETE(type) | STAT_ERR(type))

struct ve_spc_opp {
	unsigned long freq;
	unsigned long u_volt;
};

struct ve_spc_drvdata {
	void __iomem *baseaddr;
	/*
	 * A15s cluster identifier
	 * It corresponds to A15 processors MPIDR[15:8] bitfield
	 */
	u32 a15_clusid;
	uint32_t cur_rsp_mask;
	uint32_t cur_rsp_stat;
	struct semaphore sem;
	struct completion done;
	struct ve_spc_opp *opps[MAX_CLUSTERS];
	int num_opps[MAX_CLUSTERS];
};

static struct ve_spc_drvdata *info;

static inline bool cluster_is_a15(u32 cluster)
{
	return cluster == info->a15_clusid;
}

/**
 * ve_spc_global_wakeup_irq()
 *
 * Function to set/clear global wakeup IRQs. Not protected by locking since
 * it might be used in code paths where normal cacheable locks are not
 * working. Locking must be provided by the caller to ensure atomicity.
 *
 * @set: if true, global wake-up IRQs are set, if false they are cleared
 */
void ve_spc_global_wakeup_irq(bool set)
{
	u32 reg;

	reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);

	if (set)
		reg |= GBL_WAKEUP_INT_MSK;
	else
		reg &= ~GBL_WAKEUP_INT_MSK;

	writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
}

/**
 * ve_spc_cpu_wakeup_irq()
 *
 * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
 * it might be used in code paths where normal cacheable locks are not
 * working. Locking must be provided by the caller to ensure atomicity.
 *
 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
 * @set: if true, wake-up IRQs are set, if false they are cleared
 */
void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
{
	u32 mask, reg;

	if (cluster >= MAX_CLUSTERS)
		return;

	mask = 1 << cpu;

	if (!cluster_is_a15(cluster))
		mask <<= 4;

	reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);

	if (set)
		reg |= mask;
	else
		reg &= ~mask;

	writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
}

/**
 * ve_spc_set_resume_addr() - set the jump address used for warm boot
 *
 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
 * @addr: physical resume address
 */
void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
{
	void __iomem *baseaddr;

	if (cluster >= MAX_CLUSTERS)
		return;

	if (cluster_is_a15(cluster))
		baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
	else
		baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);

	writel_relaxed(addr, baseaddr);
}

/**
 * ve_spc_powerdown()
 *
 * Function to enable/disable cluster powerdown. Not protected by locking
 * since it might be used in code paths where normal cacheable locks are not
 * working. Locking must be provided by the caller to ensure atomicity.
 *
 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
 * @enable: if true enables powerdown, if false disables it
 */
void ve_spc_powerdown(u32 cluster, bool enable)
{
	u32 pwdrn_reg;

	if (cluster >= MAX_CLUSTERS)
		return;

	pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
	writel_relaxed(enable, info->baseaddr + pwdrn_reg);
}

static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster)
{
	return cluster_is_a15(cluster) ?
		  STANDBYWFI_STAT_A15_CPU_MASK(cpu)
		: STANDBYWFI_STAT_A7_CPU_MASK(cpu);
}

/**
 * ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
 *
 * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
 *
 * @return: non-zero if and only if the specified CPU is in WFI
 *
 * Take care when interpreting the result of this function: a CPU might
 * be in WFI temporarily due to idle, and is not necessarily safely
 * parked.
 */
int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
{
	int ret;
	u32 mask = standbywfi_cpu_mask(cpu, cluster);

	if (cluster >= MAX_CLUSTERS)
		return 1;

	ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT);

	pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n",
		 __func__, STANDBYWFI_STAT, ret, mask);

	return ret & mask;
}

static int ve_spc_get_performance(int cluster, u32 *freq)
{
	struct ve_spc_opp *opps = info->opps[cluster];
	u32 perf_cfg_reg = 0;
	u32 perf;

	perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7;

	perf = readl_relaxed(info->baseaddr + perf_cfg_reg);
	if (perf >= info->num_opps[cluster])
		return -EINVAL;

	opps += perf;
	*freq = opps->freq;

	return 0;
}

/* find closest match to given frequency in OPP table */
static int ve_spc_round_performance(int cluster, u32 freq)
{
	int idx, max_opp = info->num_opps[cluster];
	struct ve_spc_opp *opps = info->opps[cluster];
	u32 fmin = 0, fmax = ~0, ftmp;

	freq /= 1000; /* OPP entries in kHz */
	for (idx = 0; idx < max_opp; idx++, opps++) {
		ftmp = opps->freq;
		if (ftmp >= freq) {
			if (ftmp <= fmax)
				fmax = ftmp;
		} else {
			if (ftmp >= fmin)
				fmin = ftmp;
		}
	}
	if (fmax != ~0)
		return fmax * 1000;
	else
		return fmin * 1000;
}

static int ve_spc_find_performance_index(int cluster, u32 freq)
{
	int idx, max_opp = info->num_opps[cluster];
	struct ve_spc_opp *opps = info->opps[cluster];

	for (idx = 0; idx < max_opp; idx++, opps++)
		if (opps->freq == freq)
			break;
	return (idx == max_opp) ? -EINVAL : idx;
}

static int ve_spc_waitforcompletion(int req_type)
{
	int ret = wait_for_completion_interruptible_timeout(
			&info->done, usecs_to_jiffies(TIMEOUT_US));
	if (ret == 0)
		ret = -ETIMEDOUT;
	else if (ret > 0)
		ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO;
	return ret;
}

static int ve_spc_set_performance(int cluster, u32 freq)
{
	u32 perf_cfg_reg;
	int ret, perf, req_type;

	if (cluster_is_a15(cluster)) {
		req_type = CA15_DVFS;
		perf_cfg_reg = PERF_LVL_A15;
	} else {
		req_type = CA7_DVFS;
		perf_cfg_reg = PERF_LVL_A7;
	}

	perf = ve_spc_find_performance_index(cluster, freq);

	if (perf < 0)
		return perf;

	if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
		return -ETIME;

	init_completion(&info->done);
	info->cur_rsp_mask = RESPONSE_MASK(req_type);

	writel(perf, info->baseaddr + perf_cfg_reg);
	ret = ve_spc_waitforcompletion(req_type);

	info->cur_rsp_mask = 0;
	up(&info->sem);

	return ret;
}

static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data)
{
	int ret;

	if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
		return -ETIME;

	init_completion(&info->done);
	info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG);

	/* Set the control value */
	writel(SYSCFG_START | func | offset >> 2, info->baseaddr + COMMS);
	ret = ve_spc_waitforcompletion(SPC_SYS_CFG);

	if (ret == 0)
		*data = readl(info->baseaddr + SYSCFG_RDATA);

	info->cur_rsp_mask = 0;
	up(&info->sem);

	return ret;
}

static irqreturn_t ve_spc_irq_handler(int irq, void *data)
{
	struct ve_spc_drvdata *drv_data = data;
	uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS);

	if (info->cur_rsp_mask & status) {
		info->cur_rsp_stat = status;
		complete(&drv_data->done);
	}

	return IRQ_HANDLED;
}

/*
 *  +--------------------------+
 *  | 31      20 | 19        0 |
 *  +--------------------------+
 *  |   m_volt   |  freq(kHz)  |
 *  +--------------------------+
 */
#define MULT_FACTOR	20
#define VOLT_SHIFT	20
#define FREQ_MASK	(0xFFFFF)
static int ve_spc_populate_opps(uint32_t cluster)
{
	uint32_t data = 0, off, ret, idx;
	struct ve_spc_opp *opps;

	opps = kzalloc(sizeof(*opps) * MAX_OPPS, GFP_KERNEL);
	if (!opps)
		return -ENOMEM;

	info->opps[cluster] = opps;

	off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE;
	for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) {
		ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
		if (!ret) {
			opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
			opps->u_volt = (data >> VOLT_SHIFT) * 1000;
		} else {
			break;
		}
	}
	info->num_opps[cluster] = idx;

	return ret;
}

static int ve_init_opp_table(struct device *cpu_dev)
{
	int cluster;
	int idx, ret = 0, max_opp;
	struct ve_spc_opp *opps;

	cluster = topology_physical_package_id(cpu_dev->id);
	cluster = cluster < 0 ? 0 : cluster;

	max_opp = info->num_opps[cluster];
	opps = info->opps[cluster];

	for (idx = 0; idx < max_opp; idx++, opps++) {
		ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
		if (ret) {
			dev_warn(cpu_dev, "failed to add opp %lu %lu\n",
				 opps->freq, opps->u_volt);
			return ret;
		}
	}
	return ret;
}

int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq)
{
	int ret;
	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (!info) {
		pr_err(SPCLOG "unable to allocate mem\n");
		return -ENOMEM;
	}

	info->baseaddr = baseaddr;
	info->a15_clusid = a15_clusid;

	if (irq <= 0) {
		pr_err(SPCLOG "Invalid IRQ %d\n", irq);
		kfree(info);
		return -EINVAL;
	}

	init_completion(&info->done);

	readl_relaxed(info->baseaddr + PWC_STATUS);

	ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH
				| IRQF_ONESHOT, "vexpress-spc", info);
	if (ret) {
		pr_err(SPCLOG "IRQ %d request failed\n", irq);
		kfree(info);
		return -ENODEV;
	}

	sema_init(&info->sem, 1);
	/*
	 * Multi-cluster systems may need this data when non-coherent, during
	 * cluster power-up/power-down. Make sure driver info reaches main
	 * memory.
	 */
	sync_cache_w(info);
	sync_cache_w(&info);

	return 0;
}

struct clk_spc {
	struct clk_hw hw;
	int cluster;
};

#define to_clk_spc(spc) container_of(spc, struct clk_spc, hw)
static unsigned long spc_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct clk_spc *spc = to_clk_spc(hw);
	u32 freq;

	if (ve_spc_get_performance(spc->cluster, &freq))
		return -EIO;

	return freq * 1000;
}

static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
		unsigned long *parent_rate)
{
	struct clk_spc *spc = to_clk_spc(hw);

	return ve_spc_round_performance(spc->cluster, drate);
}

static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_spc *spc = to_clk_spc(hw);

	return ve_spc_set_performance(spc->cluster, rate / 1000);
}

static struct clk_ops clk_spc_ops = {
	.recalc_rate = spc_recalc_rate,
	.round_rate = spc_round_rate,
	.set_rate = spc_set_rate,
};

static struct clk *ve_spc_clk_register(struct device *cpu_dev)
{
	struct clk_init_data init;
	struct clk_spc *spc;

	spc = kzalloc(sizeof(*spc), GFP_KERNEL);
	if (!spc) {
		pr_err("could not allocate spc clk\n");
		return ERR_PTR(-ENOMEM);
	}

	spc->hw.init = &init;
	spc->cluster = topology_physical_package_id(cpu_dev->id);

	spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;

	init.name = dev_name(cpu_dev);
	init.ops = &clk_spc_ops;
	init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
	init.num_parents = 0;

	return devm_clk_register(cpu_dev, &spc->hw);
}

static int __init ve_spc_clk_init(void)
{
	int cpu;
	struct clk *clk;

	if (!info)
		return 0; /* Continue only if SPC is initialised */

	if (ve_spc_populate_opps(0) || ve_spc_populate_opps(1)) {
		pr_err("failed to build OPP table\n");
		return -ENODEV;
	}

	for_each_possible_cpu(cpu) {
		struct device *cpu_dev = get_cpu_device(cpu);
		if (!cpu_dev) {
			pr_warn("failed to get cpu%d device\n", cpu);
			continue;
		}
		clk = ve_spc_clk_register(cpu_dev);
		if (IS_ERR(clk)) {
			pr_warn("failed to register cpu%d clock\n", cpu);
			continue;
		}
		if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
			pr_warn("failed to register cpu%d clock lookup\n", cpu);
			continue;
		}

		if (ve_init_opp_table(cpu_dev))
			pr_warn("failed to initialise cpu%d opp table\n", cpu);
	}

	platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0);
	return 0;
}
device_initcall(ve_spc_clk_init);
Commit	Line	Data
63819cb1 LP	1	/*
	2	* Versatile Express Serial Power Controller (SPC) support
	3	*
	4	* Copyright (C) 2013 ARM Ltd.
	5	*
	6	* Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
	7	* Achin Gupta <achin.gupta@arm.com>
	8	* Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	15	* kind, whether express or implied; without even the implied warranty
	16	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*/
	19
4d910d5b SH	20	#include <linux/clk-provider.h>
	21	#include <linux/clkdev.h>
	22	#include <linux/cpu.h>
f7cd2d83	23	#include <linux/delay.h>
63819cb1	24	#include <linux/err.h>
f7cd2d83	25	#include <linux/interrupt.h>
63819cb1	26	#include <linux/io.h>
9e941b6f	27	#include <linux/platform_device.h>
f7cd2d83	28	#include <linux/pm_opp.h>
63819cb1	29	#include <linux/slab.h>
f7cd2d83	30	#include <linux/semaphore.h>
63819cb1 LP	31
	32	#include <asm/cacheflush.h>
	33
	34	#define SPCLOG "vexpress-spc: "
	35
f7cd2d83 SH	36	#define PERF_LVL_A15 0x00
	37	#define PERF_REQ_A15 0x04
	38	#define PERF_LVL_A7 0x08
	39	#define PERF_REQ_A7 0x0c
	40	#define COMMS 0x10
	41	#define COMMS_REQ 0x14
	42	#define PWC_STATUS 0x18
	43	#define PWC_FLAG 0x1c
	44
63819cb1 LP	45	/* SPC wake-up IRQs status and mask */
	46	#define WAKE_INT_MASK 0x24
	47	#define WAKE_INT_RAW 0x28
	48	#define WAKE_INT_STAT 0x2c
	49	/* SPC power down registers */
	50	#define A15_PWRDN_EN 0x30
	51	#define A7_PWRDN_EN 0x34
	52	/* SPC per-CPU mailboxes */
	53	#define A15_BX_ADDR0 0x68
	54	#define A7_BX_ADDR0 0x78
	55
33cb667a DM	56	/* SPC CPU/cluster reset statue */
	57	#define STANDBYWFI_STAT 0x3c
	58	#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
	59	#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
	60
f7cd2d83 SH	61	/* SPC system config interface registers */
	62	#define SYSCFG_WDATA 0x70
	63	#define SYSCFG_RDATA 0x74
	64
	65	/* A15/A7 OPP virtual register base */
	66	#define A15_PERFVAL_BASE 0xC10
	67	#define A7_PERFVAL_BASE 0xC30
	68
	69	/* Config interface control bits */
	70	#define SYSCFG_START (1 << 31)
	71	#define SYSCFG_SCC (6 << 20)
	72	#define SYSCFG_STAT (14 << 20)
	73
63819cb1 LP	74	/* wake-up interrupt masks */
	75	#define GBL_WAKEUP_INT_MSK (0x3 << 10)
	76
	77	/* TC2 static dual-cluster configuration */
	78	#define MAX_CLUSTERS 2
	79
f7cd2d83 SH	80	/*
	81	* Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
	82	* operation, the operation could start just before jiffie is about
	83	* to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz
	84	*/
	85	#define TIMEOUT_US 20000
	86
	87	#define MAX_OPPS 8
	88	#define CA15_DVFS 0
	89	#define CA7_DVFS 1
	90	#define SPC_SYS_CFG 2
	91	#define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
	92	#define STAT_ERR(type) ((1 << 1) << (type << 2))
	93	#define RESPONSE_MASK(type) (STAT_COMPLETE(type) \| STAT_ERR(type))
	94
	95	struct ve_spc_opp {
	96	unsigned long freq;
	97	unsigned long u_volt;
	98	};
	99
63819cb1 LP	100	struct ve_spc_drvdata {
	101	void __iomem *baseaddr;
	102	/*
	103	* A15s cluster identifier
	104	* It corresponds to A15 processors MPIDR[15:8] bitfield
	105	*/
	106	u32 a15_clusid;
f7cd2d83 SH	107	uint32_t cur_rsp_mask;
	108	uint32_t cur_rsp_stat;
	109	struct semaphore sem;
	110	struct completion done;
	111	struct ve_spc_opp *opps[MAX_CLUSTERS];
	112	int num_opps[MAX_CLUSTERS];
63819cb1 LP	113	};
	114
	115	static struct ve_spc_drvdata *info;
	116
	117	static inline bool cluster_is_a15(u32 cluster)
	118	{
	119	return cluster == info->a15_clusid;
	120	}
	121
	122	/**
	123	* ve_spc_global_wakeup_irq()
	124	*
	125	* Function to set/clear global wakeup IRQs. Not protected by locking since
	126	* it might be used in code paths where normal cacheable locks are not
	127	* working. Locking must be provided by the caller to ensure atomicity.
	128	*
	129	* @set: if true, global wake-up IRQs are set, if false they are cleared
	130	*/
	131	void ve_spc_global_wakeup_irq(bool set)
	132	{
	133	u32 reg;
	134
	135	reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
	136
	137	if (set)
	138	reg \|= GBL_WAKEUP_INT_MSK;
	139	else
	140	reg &= ~GBL_WAKEUP_INT_MSK;
	141
	142	writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
	143	}
	144
	145	/**
	146	* ve_spc_cpu_wakeup_irq()
	147	*
	148	* Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
	149	* it might be used in code paths where normal cacheable locks are not
	150	* working. Locking must be provided by the caller to ensure atomicity.
	151	*
	152	* @cluster: mpidr[15:8] bitfield describing cluster affinity level
	153	* @cpu: mpidr[7:0] bitfield describing cpu affinity level
	154	* @set: if true, wake-up IRQs are set, if false they are cleared
	155	*/
	156	void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
	157	{
	158	u32 mask, reg;
	159
	160	if (cluster >= MAX_CLUSTERS)
	161	return;
	162
	163	mask = 1 << cpu;
	164
	165	if (!cluster_is_a15(cluster))
	166	mask <<= 4;
	167
	168	reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
	169
	170	if (set)
	171	reg \|= mask;
	172	else
	173	reg &= ~mask;
	174
	175	writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
	176	}
177
178	/**
179	* ve_spc_set_resume_addr() - set the jump address used for warm boot
180	*
181	* @cluster: mpidr[15:8] bitfield describing cluster affinity level
182	* @cpu: mpidr[7:0] bitfield describing cpu affinity level
183	* @addr: physical resume address
184	*/
185	void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
186	{
187	void __iomem *baseaddr;
188
189	if (cluster >= MAX_CLUSTERS)
190	return;
191
192	if (cluster_is_a15(cluster))
193	baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
194	else
195	baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
196
197	writel_relaxed(addr, baseaddr);
198	}
199
200	/**
201	* ve_spc_powerdown()
202	*
203	* Function to enable/disable cluster powerdown. Not protected by locking
204	* since it might be used in code paths where normal cacheable locks are not
205	* working. Locking must be provided by the caller to ensure atomicity.
206	*
207	* @cluster: mpidr[15:8] bitfield describing cluster affinity level
208	* @enable: if true enables powerdown, if false disables it
209	*/
210	void ve_spc_powerdown(u32 cluster, bool enable)
211	{
212	u32 pwdrn_reg;
213
214	if (cluster >= MAX_CLUSTERS)
215	return;
216
217	pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
218	writel_relaxed(enable, info->baseaddr + pwdrn_reg);
219	}
220
33cb667a DM	221	static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster)
	222	{
	223	return cluster_is_a15(cluster) ?
	224	STANDBYWFI_STAT_A15_CPU_MASK(cpu)
	225	: STANDBYWFI_STAT_A7_CPU_MASK(cpu);
	226	}
	227
	228	/**
	229	* ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
	230	*
	231	* @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
	232	* @cluster: mpidr[15:8] bitfield describing cluster affinity level
	233	*
	234	* @return: non-zero if and only if the specified CPU is in WFI
	235	*
	236	* Take care when interpreting the result of this function: a CPU might
	237	* be in WFI temporarily due to idle, and is not necessarily safely
	238	* parked.
	239	*/
	240	int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
	241	{
	242	int ret;
	243	u32 mask = standbywfi_cpu_mask(cpu, cluster);
	244
	245	if (cluster >= MAX_CLUSTERS)
	246	return 1;
	247
	248	ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT);
	249
	250	pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n",
	251	__func__, STANDBYWFI_STAT, ret, mask);
	252
	253	return ret & mask;
	254	}
	255
f7cd2d83 SH	256	static int ve_spc_get_performance(int cluster, u32 *freq)
	257	{
	258	struct ve_spc_opp *opps = info->opps[cluster];
	259	u32 perf_cfg_reg = 0;
	260	u32 perf;
	261
	262	perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7;
	263
	264	perf = readl_relaxed(info->baseaddr + perf_cfg_reg);
	265	if (perf >= info->num_opps[cluster])
	266	return -EINVAL;
	267
	268	opps += perf;
	269	*freq = opps->freq;
	270
	271	return 0;
	272	}
	273
	274	/* find closest match to given frequency in OPP table */
	275	static int ve_spc_round_performance(int cluster, u32 freq)
	276	{
	277	int idx, max_opp = info->num_opps[cluster];
	278	struct ve_spc_opp *opps = info->opps[cluster];
	279	u32 fmin = 0, fmax = ~0, ftmp;
	280
	281	freq /= 1000; /* OPP entries in kHz */
	282	for (idx = 0; idx < max_opp; idx++, opps++) {
	283	ftmp = opps->freq;
	284	if (ftmp >= freq) {
	285	if (ftmp <= fmax)
	286	fmax = ftmp;
	287	} else {
	288	if (ftmp >= fmin)
	289	fmin = ftmp;
	290	}
	291	}
	292	if (fmax != ~0)
	293	return fmax * 1000;
	294	else
	295	return fmin * 1000;
	296	}
	297
	298	static int ve_spc_find_performance_index(int cluster, u32 freq)
	299	{
	300	int idx, max_opp = info->num_opps[cluster];
	301	struct ve_spc_opp *opps = info->opps[cluster];
	302
	303	for (idx = 0; idx < max_opp; idx++, opps++)
	304	if (opps->freq == freq)
	305	break;
	306	return (idx == max_opp) ? -EINVAL : idx;
	307	}
	308
	309	static int ve_spc_waitforcompletion(int req_type)
	310	{
	311	int ret = wait_for_completion_interruptible_timeout(
	312	&info->done, usecs_to_jiffies(TIMEOUT_US));
	313	if (ret == 0)
	314	ret = -ETIMEDOUT;
	315	else if (ret > 0)
	316	ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO;
	317	return ret;
	318	}
	319
320	static int ve_spc_set_performance(int cluster, u32 freq)
321	{
f66ce0da	322	u32 perf_cfg_reg;
f7cd2d83 SH	323	int ret, perf, req_type;
	324
	325	if (cluster_is_a15(cluster)) {
	326	req_type = CA15_DVFS;
	327	perf_cfg_reg = PERF_LVL_A15;
f7cd2d83 SH	328	} else {
	329	req_type = CA7_DVFS;
	330	perf_cfg_reg = PERF_LVL_A7;
f7cd2d83 SH	331	}
	332
	333	perf = ve_spc_find_performance_index(cluster, freq);
	334
	335	if (perf < 0)
	336	return perf;
	337
	338	if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
	339	return -ETIME;
	340
	341	init_completion(&info->done);
	342	info->cur_rsp_mask = RESPONSE_MASK(req_type);
	343
	344	writel(perf, info->baseaddr + perf_cfg_reg);
	345	ret = ve_spc_waitforcompletion(req_type);
	346
	347	info->cur_rsp_mask = 0;
	348	up(&info->sem);
	349
	350	return ret;
	351	}
	352
	353	static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data)
	354	{
	355	int ret;
	356
	357	if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
	358	return -ETIME;
	359
	360	init_completion(&info->done);
	361	info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG);
	362
	363	/* Set the control value */
	364	writel(SYSCFG_START \| func \| offset >> 2, info->baseaddr + COMMS);
	365	ret = ve_spc_waitforcompletion(SPC_SYS_CFG);
	366
	367	if (ret == 0)
	368	*data = readl(info->baseaddr + SYSCFG_RDATA);
	369
	370	info->cur_rsp_mask = 0;
	371	up(&info->sem);
	372
	373	return ret;
	374	}
	375
	376	static irqreturn_t ve_spc_irq_handler(int irq, void *data)
	377	{
	378	struct ve_spc_drvdata *drv_data = data;
	379	uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS);
	380
	381	if (info->cur_rsp_mask & status) {
	382	info->cur_rsp_stat = status;
	383	complete(&drv_data->done);
	384	}
	385
	386	return IRQ_HANDLED;
	387	}
	388
	389	/*
	390	* +--------------------------+
	391	* \| 31 20 \| 19 0 \|
	392	* +--------------------------+
cf2e0a73	393	* \| m_volt \| freq(kHz) \|
f7cd2d83 SH	394	* +--------------------------+
	395	*/
	396	#define MULT_FACTOR 20
	397	#define VOLT_SHIFT 20
	398	#define FREQ_MASK (0xFFFFF)
	399	static int ve_spc_populate_opps(uint32_t cluster)
	400	{
	401	uint32_t data = 0, off, ret, idx;
	402	struct ve_spc_opp *opps;
	403
	404	opps = kzalloc(sizeof(opps) MAX_OPPS, GFP_KERNEL);
	405	if (!opps)
	406	return -ENOMEM;
	407
	408	info->opps[cluster] = opps;
	409
	410	off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE;
	411	for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) {
	412	ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
	413	if (!ret) {
	414	opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
cf2e0a73	415	opps->u_volt = (data >> VOLT_SHIFT) * 1000;
f7cd2d83 SH	416	} else {
	417	break;
	418	}
	419	}
	420	info->num_opps[cluster] = idx;
	421
	422	return ret;
	423	}
	424
	425	static int ve_init_opp_table(struct device *cpu_dev)
	426	{
e160cc17 AS	427	int cluster;
	428	int idx, ret = 0, max_opp;
	429	struct ve_spc_opp *opps;
	430
	431	cluster = topology_physical_package_id(cpu_dev->id);
	432	cluster = cluster < 0 ? 0 : cluster;
	433
	434	max_opp = info->num_opps[cluster];
	435	opps = info->opps[cluster];
f7cd2d83 SH	436
	437	for (idx = 0; idx < max_opp; idx++, opps++) {
	438	ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
	439	if (ret) {
	440	dev_warn(cpu_dev, "failed to add opp %lu %lu\n",
	441	opps->freq, opps->u_volt);
	442	return ret;
	443	}
	444	}
	445	return ret;
	446	}
	447
	448	int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq)
63819cb1	449	{
f7cd2d83	450	int ret;
63819cb1 LP	451	info = kzalloc(sizeof(*info), GFP_KERNEL);
	452	if (!info) {
	453	pr_err(SPCLOG "unable to allocate mem\n");
	454	return -ENOMEM;
	455	}
	456
	457	info->baseaddr = baseaddr;
	458	info->a15_clusid = a15_clusid;
	459
f7cd2d83 SH	460	if (irq <= 0) {
	461	pr_err(SPCLOG "Invalid IRQ %d\n", irq);
	462	kfree(info);
	463	return -EINVAL;
	464	}
	465
	466	init_completion(&info->done);
	467
	468	readl_relaxed(info->baseaddr + PWC_STATUS);
	469
	470	ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH
	471	\| IRQF_ONESHOT, "vexpress-spc", info);
	472	if (ret) {
	473	pr_err(SPCLOG "IRQ %d request failed\n", irq);
	474	kfree(info);
	475	return -ENODEV;
	476	}
	477
	478	sema_init(&info->sem, 1);
63819cb1 LP	479	/*
	480	* Multi-cluster systems may need this data when non-coherent, during
	481	* cluster power-up/power-down. Make sure driver info reaches main
	482	* memory.
	483	*/
	484	sync_cache_w(info);
	485	sync_cache_w(&info);
	486
	487	return 0;
	488	}
4d910d5b SH	489
	490	struct clk_spc {
	491	struct clk_hw hw;
	492	int cluster;
	493	};
	494
	495	#define to_clk_spc(spc) container_of(spc, struct clk_spc, hw)
	496	static unsigned long spc_recalc_rate(struct clk_hw *hw,
	497	unsigned long parent_rate)
	498	{
	499	struct clk_spc *spc = to_clk_spc(hw);
	500	u32 freq;
	501
	502	if (ve_spc_get_performance(spc->cluster, &freq))
	503	return -EIO;
	504
	505	return freq * 1000;
	506	}
	507
	508	static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
	509	unsigned long *parent_rate)
	510	{
	511	struct clk_spc *spc = to_clk_spc(hw);
	512
	513	return ve_spc_round_performance(spc->cluster, drate);
	514	}
	515
	516	static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
	517	unsigned long parent_rate)
	518	{
	519	struct clk_spc *spc = to_clk_spc(hw);
	520
	521	return ve_spc_set_performance(spc->cluster, rate / 1000);
	522	}
	523
	524	static struct clk_ops clk_spc_ops = {
	525	.recalc_rate = spc_recalc_rate,
	526	.round_rate = spc_round_rate,
	527	.set_rate = spc_set_rate,
	528	};
	529
	530	static struct clk ve_spc_clk_register(struct device cpu_dev)
	531	{
	532	struct clk_init_data init;
	533	struct clk_spc *spc;
	534
	535	spc = kzalloc(sizeof(*spc), GFP_KERNEL);
	536	if (!spc) {
	537	pr_err("could not allocate spc clk\n");
	538	return ERR_PTR(-ENOMEM);
	539	}
	540
	541	spc->hw.init = &init;
	542	spc->cluster = topology_physical_package_id(cpu_dev->id);
	543
e160cc17 AS	544	spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
e160cc17 AS	545
4d910d5b SH	546	init.name = dev_name(cpu_dev);
	547	init.ops = &clk_spc_ops;
	548	init.flags = CLK_IS_ROOT \| CLK_GET_RATE_NOCACHE;
	549	init.num_parents = 0;
	550
	551	return devm_clk_register(cpu_dev, &spc->hw);
	552	}
	553
	554	static int __init ve_spc_clk_init(void)
	555	{
	556	int cpu;
	557	struct clk *clk;
	558
	559	if (!info)
	560	return 0; /* Continue only if SPC is initialised */
	561
	562	if (ve_spc_populate_opps(0) \|\| ve_spc_populate_opps(1)) {
	563	pr_err("failed to build OPP table\n");
	564	return -ENODEV;
	565	}
	566
	567	for_each_possible_cpu(cpu) {
	568	struct device *cpu_dev = get_cpu_device(cpu);
	569	if (!cpu_dev) {
	570	pr_warn("failed to get cpu%d device\n", cpu);
	571	continue;
	572	}
	573	clk = ve_spc_clk_register(cpu_dev);
	574	if (IS_ERR(clk)) {
	575	pr_warn("failed to register cpu%d clock\n", cpu);
	576	continue;
	577	}
	578	if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
	579	pr_warn("failed to register cpu%d clock lookup\n", cpu);
	580	continue;
	581	}
	582
	583	if (ve_init_opp_table(cpu_dev))
	584	pr_warn("failed to initialise cpu%d opp table\n", cpu);
	585	}
	586
9e941b6f	587	platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0);
4d910d5b SH	588	return 0;
4d910d5b SH	589	}
4a0ece7c	590	device_initcall(ve_spc_clk_init);