[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-vexpress / spc.c

/*
 * Versatile Express Serial Power Controller (SPC) support
 *
 * Copyright (C) 2013 ARM Ltd.
 *
 * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
 *          Achin Gupta           <achin.gupta@arm.com>
 *          Lorenzo Pieralisi     <lorenzo.pieralisi@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/semaphore.h>

#include <asm/cacheflush.h>

#include "spc.h"

#define SPCLOG "vexpress-spc: "

#define PERF_LVL_A15		0x00
#define PERF_REQ_A15		0x04
#define PERF_LVL_A7		0x08
#define PERF_REQ_A7		0x0c
#define COMMS			0x10
#define COMMS_REQ		0x14
#define PWC_STATUS		0x18
#define PWC_FLAG		0x1c

/* SPC wake-up IRQs status and mask */
#define WAKE_INT_MASK		0x24
#define WAKE_INT_RAW		0x28
#define WAKE_INT_STAT		0x2c
/* SPC power down registers */
#define A15_PWRDN_EN		0x30
#define A7_PWRDN_EN		0x34
/* SPC per-CPU mailboxes */
#define A15_BX_ADDR0		0x68
#define A7_BX_ADDR0		0x78

/* SPC CPU/cluster reset statue */
#define STANDBYWFI_STAT		0x3c
#define STANDBYWFI_STAT_A15_CPU_MASK(cpu)	(1 << (cpu))
#define STANDBYWFI_STAT_A7_CPU_MASK(cpu)	(1 << (3 + (cpu)))

/* SPC system config interface registers */
#define SYSCFG_WDATA		0x70
#define SYSCFG_RDATA		0x74

/* A15/A7 OPP virtual register base */
#define A15_PERFVAL_BASE	0xC10
#define A7_PERFVAL_BASE		0xC30

/* Config interface control bits */
#define SYSCFG_START		(1 << 31)
#define SYSCFG_SCC		(6 << 20)
#define SYSCFG_STAT		(14 << 20)

/* wake-up interrupt masks */
#define GBL_WAKEUP_INT_MSK	(0x3 << 10)

/* TC2 static dual-cluster configuration */
#define MAX_CLUSTERS		2

/*
 * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
 * operation, the operation could start just before jiffie is about
 * to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz
 */
#define TIMEOUT_US	20000

#define MAX_OPPS	8
#define CA15_DVFS	0
#define CA7_DVFS	1
#define SPC_SYS_CFG	2
#define STAT_COMPLETE(type)	((1 << 0) << (type << 2))
#define STAT_ERR(type)		((1 << 1) << (type << 2))
#define RESPONSE_MASK(type)	(STAT_COMPLETE(type) | STAT_ERR(type))

struct ve_spc_opp {
	unsigned long freq;
	unsigned long u_volt;
};

struct ve_spc_drvdata {
	void __iomem *baseaddr;
	/*
	 * A15s cluster identifier
	 * It corresponds to A15 processors MPIDR[15:8] bitfield
	 */
	u32 a15_clusid;
	uint32_t cur_rsp_mask;
	uint32_t cur_rsp_stat;
	struct semaphore sem;
	struct completion done;
	struct ve_spc_opp *opps[MAX_CLUSTERS];
	int num_opps[MAX_CLUSTERS];
};

static struct ve_spc_drvdata *info;

static inline bool cluster_is_a15(u32 cluster)
{
	return cluster == info->a15_clusid;
}

/**
 * ve_spc_global_wakeup_irq()
 *
 * Function to set/clear global wakeup IRQs. Not protected by locking since
 * it might be used in code paths where normal cacheable locks are not
 * working. Locking must be provided by the caller to ensure atomicity.
 *
 * @set: if true, global wake-up IRQs are set, if false they are cleared
 */
void ve_spc_global_wakeup_irq(bool set)
{
	u32 reg;

	reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);

	if (set)
		reg |= GBL_WAKEUP_INT_MSK;
	else
		reg &= ~GBL_WAKEUP_INT_MSK;

	writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
}

/**
 * ve_spc_cpu_wakeup_irq()
 *
 * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
 * it might be used in code paths where normal cacheable locks are not
 * working. Locking must be provided by the caller to ensure atomicity.
 *
 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
 * @set: if true, wake-up IRQs are set, if false they are cleared
 */
void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
{
	u32 mask, reg;

	if (cluster >= MAX_CLUSTERS)
		return;

	mask = 1 << cpu;

	if (!cluster_is_a15(cluster))
		mask <<= 4;

	reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);

	if (set)
		reg |= mask;
	else
		reg &= ~mask;

	writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
}

/**
 * ve_spc_set_resume_addr() - set the jump address used for warm boot
 *
 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
 * @addr: physical resume address
 */
void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
{
	void __iomem *baseaddr;

	if (cluster >= MAX_CLUSTERS)
		return;

	if (cluster_is_a15(cluster))
		baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
	else
		baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);

	writel_relaxed(addr, baseaddr);
}

/**
 * ve_spc_powerdown()
 *
 * Function to enable/disable cluster powerdown. Not protected by locking
 * since it might be used in code paths where normal cacheable locks are not
 * working. Locking must be provided by the caller to ensure atomicity.
 *
 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
 * @enable: if true enables powerdown, if false disables it
 */
void ve_spc_powerdown(u32 cluster, bool enable)
{
	u32 pwdrn_reg;

	if (cluster >= MAX_CLUSTERS)
		return;

	pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
	writel_relaxed(enable, info->baseaddr + pwdrn_reg);
}

static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster)
{
	return cluster_is_a15(cluster) ?
		  STANDBYWFI_STAT_A15_CPU_MASK(cpu)
		: STANDBYWFI_STAT_A7_CPU_MASK(cpu);
}

/**
 * ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
 *
 * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
 *
 * @return: non-zero if and only if the specified CPU is in WFI
 *
 * Take care when interpreting the result of this function: a CPU might
 * be in WFI temporarily due to idle, and is not necessarily safely
 * parked.
 */
int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
{
	int ret;
	u32 mask = standbywfi_cpu_mask(cpu, cluster);

	if (cluster >= MAX_CLUSTERS)
		return 1;

	ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT);

	pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n",
		 __func__, STANDBYWFI_STAT, ret, mask);

	return ret & mask;
}

static int ve_spc_get_performance(int cluster, u32 *freq)
{
	struct ve_spc_opp *opps = info->opps[cluster];
	u32 perf_cfg_reg = 0;
	u32 perf;

	perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7;

	perf = readl_relaxed(info->baseaddr + perf_cfg_reg);
	if (perf >= info->num_opps[cluster])
		return -EINVAL;

	opps += perf;
	*freq = opps->freq;

	return 0;
}

/* find closest match to given frequency in OPP table */
static int ve_spc_round_performance(int cluster, u32 freq)
{
	int idx, max_opp = info->num_opps[cluster];
	struct ve_spc_opp *opps = info->opps[cluster];
	u32 fmin = 0, fmax = ~0, ftmp;

	freq /= 1000; /* OPP entries in kHz */
	for (idx = 0; idx < max_opp; idx++, opps++) {
		ftmp = opps->freq;
		if (ftmp >= freq) {
			if (ftmp <= fmax)
				fmax = ftmp;
		} else {
			if (ftmp >= fmin)
				fmin = ftmp;
		}
	}
	if (fmax != ~0)
		return fmax * 1000;
	else
		return fmin * 1000;
}

static int ve_spc_find_performance_index(int cluster, u32 freq)
{
	int idx, max_opp = info->num_opps[cluster];
	struct ve_spc_opp *opps = info->opps[cluster];

	for (idx = 0; idx < max_opp; idx++, opps++)
		if (opps->freq == freq)
			break;
	return (idx == max_opp) ? -EINVAL : idx;
}

static int ve_spc_waitforcompletion(int req_type)
{
	int ret = wait_for_completion_interruptible_timeout(
			&info->done, usecs_to_jiffies(TIMEOUT_US));
	if (ret == 0)
		ret = -ETIMEDOUT;
	else if (ret > 0)
		ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO;
	return ret;
}

static int ve_spc_set_performance(int cluster, u32 freq)
{
	u32 perf_cfg_reg;
	int ret, perf, req_type;

	if (cluster_is_a15(cluster)) {
		req_type = CA15_DVFS;
		perf_cfg_reg = PERF_LVL_A15;
	} else {
		req_type = CA7_DVFS;
		perf_cfg_reg = PERF_LVL_A7;
	}

	perf = ve_spc_find_performance_index(cluster, freq);

	if (perf < 0)
		return perf;

	if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
		return -ETIME;

	init_completion(&info->done);
	info->cur_rsp_mask = RESPONSE_MASK(req_type);

	writel(perf, info->baseaddr + perf_cfg_reg);
	ret = ve_spc_waitforcompletion(req_type);

	info->cur_rsp_mask = 0;
	up(&info->sem);

	return ret;
}

static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data)
{
	int ret;

	if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
		return -ETIME;

	init_completion(&info->done);
	info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG);

	/* Set the control value */
	writel(SYSCFG_START | func | offset >> 2, info->baseaddr + COMMS);
	ret = ve_spc_waitforcompletion(SPC_SYS_CFG);

	if (ret == 0)
		*data = readl(info->baseaddr + SYSCFG_RDATA);

	info->cur_rsp_mask = 0;
	up(&info->sem);

	return ret;
}

static irqreturn_t ve_spc_irq_handler(int irq, void *data)
{
	struct ve_spc_drvdata *drv_data = data;
	uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS);

	if (info->cur_rsp_mask & status) {
		info->cur_rsp_stat = status;
		complete(&drv_data->done);
	}

	return IRQ_HANDLED;
}

/*
 *  +--------------------------+
 *  | 31      20 | 19        0 |
 *  +--------------------------+
 *  |   m_volt   |  freq(kHz)  |
 *  +--------------------------+
 */
#define MULT_FACTOR	20
#define VOLT_SHIFT	20
#define FREQ_MASK	(0xFFFFF)
static int ve_spc_populate_opps(uint32_t cluster)
{
	uint32_t data = 0, off, ret, idx;
	struct ve_spc_opp *opps;

	opps = kzalloc(sizeof(*opps) * MAX_OPPS, GFP_KERNEL);
	if (!opps)
		return -ENOMEM;

	info->opps[cluster] = opps;

	off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE;
	for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) {
		ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
		if (!ret) {
			opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
			opps->u_volt = (data >> VOLT_SHIFT) * 1000;
		} else {
			break;
		}
	}
	info->num_opps[cluster] = idx;

	return ret;
}

static int ve_init_opp_table(struct device *cpu_dev)
{
	int cluster;
	int idx, ret = 0, max_opp;
	struct ve_spc_opp *opps;

	cluster = topology_physical_package_id(cpu_dev->id);
	cluster = cluster < 0 ? 0 : cluster;

	max_opp = info->num_opps[cluster];
	opps = info->opps[cluster];

	for (idx = 0; idx < max_opp; idx++, opps++) {
		ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
		if (ret) {
			dev_warn(cpu_dev, "failed to add opp %lu %lu\n",
				 opps->freq, opps->u_volt);
			return ret;
		}
	}
	return ret;
}

int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq)
{
	int ret;
	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (!info) {
		pr_err(SPCLOG "unable to allocate mem\n");
		return -ENOMEM;
	}

	info->baseaddr = baseaddr;
	info->a15_clusid = a15_clusid;

	if (irq <= 0) {
		pr_err(SPCLOG "Invalid IRQ %d\n", irq);
		kfree(info);
		return -EINVAL;
	}

	init_completion(&info->done);

	readl_relaxed(info->baseaddr + PWC_STATUS);

	ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH
				| IRQF_ONESHOT, "vexpress-spc", info);
	if (ret) {
		pr_err(SPCLOG "IRQ %d request failed\n", irq);
		kfree(info);
		return -ENODEV;
	}

	sema_init(&info->sem, 1);
	/*
	 * Multi-cluster systems may need this data when non-coherent, during
	 * cluster power-up/power-down. Make sure driver info reaches main
	 * memory.
	 */
	sync_cache_w(info);
	sync_cache_w(&info);

	return 0;
}

struct clk_spc {
	struct clk_hw hw;
	int cluster;
};

#define to_clk_spc(spc) container_of(spc, struct clk_spc, hw)
static unsigned long spc_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct clk_spc *spc = to_clk_spc(hw);
	u32 freq;

	if (ve_spc_get_performance(spc->cluster, &freq))
		return -EIO;

	return freq * 1000;
}

static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
		unsigned long *parent_rate)
{
	struct clk_spc *spc = to_clk_spc(hw);

	return ve_spc_round_performance(spc->cluster, drate);
}

static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_spc *spc = to_clk_spc(hw);

	return ve_spc_set_performance(spc->cluster, rate / 1000);
}

static struct clk_ops clk_spc_ops = {
	.recalc_rate = spc_recalc_rate,
	.round_rate = spc_round_rate,
	.set_rate = spc_set_rate,
};

static struct clk *ve_spc_clk_register(struct device *cpu_dev)
{
	struct clk_init_data init;
	struct clk_spc *spc;

	spc = kzalloc(sizeof(*spc), GFP_KERNEL);
	if (!spc) {
		pr_err("could not allocate spc clk\n");
		return ERR_PTR(-ENOMEM);
	}

	spc->hw.init = &init;
	spc->cluster = topology_physical_package_id(cpu_dev->id);

	spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;

	init.name = dev_name(cpu_dev);
	init.ops = &clk_spc_ops;
	init.flags = CLK_GET_RATE_NOCACHE;
	init.num_parents = 0;

	return devm_clk_register(cpu_dev, &spc->hw);
}

static int __init ve_spc_clk_init(void)
{
	int cpu;
	struct clk *clk;

	if (!info)
		return 0; /* Continue only if SPC is initialised */

	if (ve_spc_populate_opps(0) || ve_spc_populate_opps(1)) {
		pr_err("failed to build OPP table\n");
		return -ENODEV;
	}

	for_each_possible_cpu(cpu) {
		struct device *cpu_dev = get_cpu_device(cpu);
		if (!cpu_dev) {
			pr_warn("failed to get cpu%d device\n", cpu);
			continue;
		}
		clk = ve_spc_clk_register(cpu_dev);
		if (IS_ERR(clk)) {
			pr_warn("failed to register cpu%d clock\n", cpu);
			continue;
		}
		if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
			pr_warn("failed to register cpu%d clock lookup\n", cpu);
			continue;
		}

		if (ve_init_opp_table(cpu_dev))
			pr_warn("failed to initialise cpu%d opp table\n", cpu);
	}

	platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0);
	return 0;
}
device_initcall(ve_spc_clk_init);
Commit	Line	Data
63819cb1 LP	1	/*
	2	* Versatile Express Serial Power Controller (SPC) support
	3	*
	4	* Copyright (C) 2013 ARM Ltd.
	5	*
	6	* Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
	7	* Achin Gupta <achin.gupta@arm.com>
	8	* Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	15	* kind, whether express or implied; without even the implied warranty
	16	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*/
	19
4d910d5b SH	20	#include <linux/clk-provider.h>
	21	#include <linux/clkdev.h>
	22	#include <linux/cpu.h>
f7cd2d83	23	#include <linux/delay.h>
63819cb1	24	#include <linux/err.h>
f7cd2d83	25	#include <linux/interrupt.h>
63819cb1	26	#include <linux/io.h>
9e941b6f	27	#include <linux/platform_device.h>
f7cd2d83	28	#include <linux/pm_opp.h>
63819cb1	29	#include <linux/slab.h>
f7cd2d83	30	#include <linux/semaphore.h>
63819cb1 LP	31
	32	#include <asm/cacheflush.h>
	33
e13de0a8 BD	34	#include "spc.h"
e13de0a8 BD	35
63819cb1 LP	36	#define SPCLOG "vexpress-spc: "
63819cb1 LP	37
f7cd2d83 SH	38	#define PERF_LVL_A15 0x00
	39	#define PERF_REQ_A15 0x04
	40	#define PERF_LVL_A7 0x08
	41	#define PERF_REQ_A7 0x0c
	42	#define COMMS 0x10
	43	#define COMMS_REQ 0x14
	44	#define PWC_STATUS 0x18
	45	#define PWC_FLAG 0x1c
	46
63819cb1 LP	47	/* SPC wake-up IRQs status and mask */
	48	#define WAKE_INT_MASK 0x24
	49	#define WAKE_INT_RAW 0x28
	50	#define WAKE_INT_STAT 0x2c
	51	/* SPC power down registers */
	52	#define A15_PWRDN_EN 0x30
	53	#define A7_PWRDN_EN 0x34
	54	/* SPC per-CPU mailboxes */
	55	#define A15_BX_ADDR0 0x68
	56	#define A7_BX_ADDR0 0x78
	57
33cb667a DM	58	/* SPC CPU/cluster reset statue */
	59	#define STANDBYWFI_STAT 0x3c
	60	#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
	61	#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
	62
f7cd2d83 SH	63	/* SPC system config interface registers */
	64	#define SYSCFG_WDATA 0x70
	65	#define SYSCFG_RDATA 0x74
	66
	67	/* A15/A7 OPP virtual register base */
	68	#define A15_PERFVAL_BASE 0xC10
	69	#define A7_PERFVAL_BASE 0xC30
	70
	71	/* Config interface control bits */
	72	#define SYSCFG_START (1 << 31)
	73	#define SYSCFG_SCC (6 << 20)
	74	#define SYSCFG_STAT (14 << 20)
	75
63819cb1 LP	76	/* wake-up interrupt masks */
	77	#define GBL_WAKEUP_INT_MSK (0x3 << 10)
	78
	79	/* TC2 static dual-cluster configuration */
	80	#define MAX_CLUSTERS 2
	81
f7cd2d83 SH	82	/*
	83	* Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
	84	* operation, the operation could start just before jiffie is about
	85	* to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz
	86	*/
	87	#define TIMEOUT_US 20000
	88
	89	#define MAX_OPPS 8
	90	#define CA15_DVFS 0
	91	#define CA7_DVFS 1
	92	#define SPC_SYS_CFG 2
	93	#define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
	94	#define STAT_ERR(type) ((1 << 1) << (type << 2))
	95	#define RESPONSE_MASK(type) (STAT_COMPLETE(type) \| STAT_ERR(type))
	96
	97	struct ve_spc_opp {
	98	unsigned long freq;
	99	unsigned long u_volt;
	100	};
	101
63819cb1 LP	102	struct ve_spc_drvdata {
	103	void __iomem *baseaddr;
	104	/*
	105	* A15s cluster identifier
	106	* It corresponds to A15 processors MPIDR[15:8] bitfield
	107	*/
	108	u32 a15_clusid;
f7cd2d83 SH	109	uint32_t cur_rsp_mask;
	110	uint32_t cur_rsp_stat;
	111	struct semaphore sem;
	112	struct completion done;
	113	struct ve_spc_opp *opps[MAX_CLUSTERS];
	114	int num_opps[MAX_CLUSTERS];
63819cb1 LP	115	};
	116
	117	static struct ve_spc_drvdata *info;
	118
	119	static inline bool cluster_is_a15(u32 cluster)
	120	{
	121	return cluster == info->a15_clusid;
	122	}
	123
	124	/**
	125	* ve_spc_global_wakeup_irq()
	126	*
	127	* Function to set/clear global wakeup IRQs. Not protected by locking since
	128	* it might be used in code paths where normal cacheable locks are not
	129	* working. Locking must be provided by the caller to ensure atomicity.
	130	*
	131	* @set: if true, global wake-up IRQs are set, if false they are cleared
	132	*/
	133	void ve_spc_global_wakeup_irq(bool set)
	134	{
	135	u32 reg;
	136
	137	reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
	138
	139	if (set)
	140	reg \|= GBL_WAKEUP_INT_MSK;
	141	else
	142	reg &= ~GBL_WAKEUP_INT_MSK;
	143
	144	writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
	145	}
	146
	147	/**
	148	* ve_spc_cpu_wakeup_irq()
	149	*
	150	* Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
	151	* it might be used in code paths where normal cacheable locks are not
	152	* working. Locking must be provided by the caller to ensure atomicity.
	153	*
	154	* @cluster: mpidr[15:8] bitfield describing cluster affinity level
	155	* @cpu: mpidr[7:0] bitfield describing cpu affinity level
	156	* @set: if true, wake-up IRQs are set, if false they are cleared
	157	*/
	158	void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
	159	{
	160	u32 mask, reg;
	161
	162	if (cluster >= MAX_CLUSTERS)
	163	return;
	164
	165	mask = 1 << cpu;
	166
	167	if (!cluster_is_a15(cluster))
	168	mask <<= 4;
	169
	170	reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
	171
	172	if (set)
	173	reg \|= mask;
	174	else
	175	reg &= ~mask;
	176
	177	writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
	178	}
179
180	/**
181	* ve_spc_set_resume_addr() - set the jump address used for warm boot
182	*
183	* @cluster: mpidr[15:8] bitfield describing cluster affinity level
184	* @cpu: mpidr[7:0] bitfield describing cpu affinity level
185	* @addr: physical resume address
186	*/
187	void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
188	{
189	void __iomem *baseaddr;
190
191	if (cluster >= MAX_CLUSTERS)
192	return;
193
194	if (cluster_is_a15(cluster))
195	baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
196	else
197	baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
198
199	writel_relaxed(addr, baseaddr);
200	}
201
202	/**
203	* ve_spc_powerdown()
204	*
205	* Function to enable/disable cluster powerdown. Not protected by locking
206	* since it might be used in code paths where normal cacheable locks are not
207	* working. Locking must be provided by the caller to ensure atomicity.
208	*
209	* @cluster: mpidr[15:8] bitfield describing cluster affinity level
210	* @enable: if true enables powerdown, if false disables it
211	*/
212	void ve_spc_powerdown(u32 cluster, bool enable)
213	{
214	u32 pwdrn_reg;
215
216	if (cluster >= MAX_CLUSTERS)
217	return;
218
219	pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
220	writel_relaxed(enable, info->baseaddr + pwdrn_reg);
221	}
222
33cb667a DM	223	static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster)
	224	{
	225	return cluster_is_a15(cluster) ?
	226	STANDBYWFI_STAT_A15_CPU_MASK(cpu)
	227	: STANDBYWFI_STAT_A7_CPU_MASK(cpu);
	228	}
	229
	230	/**
	231	* ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
	232	*
	233	* @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
	234	* @cluster: mpidr[15:8] bitfield describing cluster affinity level
	235	*
	236	* @return: non-zero if and only if the specified CPU is in WFI
	237	*
	238	* Take care when interpreting the result of this function: a CPU might
	239	* be in WFI temporarily due to idle, and is not necessarily safely
	240	* parked.
	241	*/
	242	int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
	243	{
	244	int ret;
	245	u32 mask = standbywfi_cpu_mask(cpu, cluster);
	246
	247	if (cluster >= MAX_CLUSTERS)
	248	return 1;
	249
	250	ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT);
	251
	252	pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n",
	253	__func__, STANDBYWFI_STAT, ret, mask);
	254
	255	return ret & mask;
	256	}
	257
f7cd2d83 SH	258	static int ve_spc_get_performance(int cluster, u32 *freq)
	259	{
	260	struct ve_spc_opp *opps = info->opps[cluster];
	261	u32 perf_cfg_reg = 0;
	262	u32 perf;
	263
	264	perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7;
	265
	266	perf = readl_relaxed(info->baseaddr + perf_cfg_reg);
	267	if (perf >= info->num_opps[cluster])
	268	return -EINVAL;
	269
	270	opps += perf;
	271	*freq = opps->freq;
	272
	273	return 0;
	274	}
	275
	276	/* find closest match to given frequency in OPP table */
	277	static int ve_spc_round_performance(int cluster, u32 freq)
	278	{
	279	int idx, max_opp = info->num_opps[cluster];
	280	struct ve_spc_opp *opps = info->opps[cluster];
	281	u32 fmin = 0, fmax = ~0, ftmp;
	282
	283	freq /= 1000; /* OPP entries in kHz */
	284	for (idx = 0; idx < max_opp; idx++, opps++) {
	285	ftmp = opps->freq;
	286	if (ftmp >= freq) {
	287	if (ftmp <= fmax)
	288	fmax = ftmp;
	289	} else {
	290	if (ftmp >= fmin)
	291	fmin = ftmp;
	292	}
	293	}
	294	if (fmax != ~0)
	295	return fmax * 1000;
	296	else
	297	return fmin * 1000;
	298	}
	299
	300	static int ve_spc_find_performance_index(int cluster, u32 freq)
	301	{
	302	int idx, max_opp = info->num_opps[cluster];
	303	struct ve_spc_opp *opps = info->opps[cluster];
	304
	305	for (idx = 0; idx < max_opp; idx++, opps++)
	306	if (opps->freq == freq)
	307	break;
	308	return (idx == max_opp) ? -EINVAL : idx;
	309	}
	310
	311	static int ve_spc_waitforcompletion(int req_type)
	312	{
	313	int ret = wait_for_completion_interruptible_timeout(
	314	&info->done, usecs_to_jiffies(TIMEOUT_US));
	315	if (ret == 0)
	316	ret = -ETIMEDOUT;
	317	else if (ret > 0)
	318	ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO;
	319	return ret;
	320	}
	321
322	static int ve_spc_set_performance(int cluster, u32 freq)
323	{
f66ce0da	324	u32 perf_cfg_reg;
f7cd2d83 SH	325	int ret, perf, req_type;
	326
	327	if (cluster_is_a15(cluster)) {
	328	req_type = CA15_DVFS;
	329	perf_cfg_reg = PERF_LVL_A15;
f7cd2d83 SH	330	} else {
	331	req_type = CA7_DVFS;
	332	perf_cfg_reg = PERF_LVL_A7;
f7cd2d83 SH	333	}
	334
	335	perf = ve_spc_find_performance_index(cluster, freq);
	336
	337	if (perf < 0)
	338	return perf;
	339
	340	if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
	341	return -ETIME;
	342
	343	init_completion(&info->done);
	344	info->cur_rsp_mask = RESPONSE_MASK(req_type);
	345
	346	writel(perf, info->baseaddr + perf_cfg_reg);
	347	ret = ve_spc_waitforcompletion(req_type);
	348
	349	info->cur_rsp_mask = 0;
	350	up(&info->sem);
	351
	352	return ret;
	353	}
	354
	355	static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data)
	356	{
	357	int ret;
	358
	359	if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
	360	return -ETIME;
	361
	362	init_completion(&info->done);
	363	info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG);
	364
	365	/* Set the control value */
	366	writel(SYSCFG_START \| func \| offset >> 2, info->baseaddr + COMMS);
	367	ret = ve_spc_waitforcompletion(SPC_SYS_CFG);
	368
	369	if (ret == 0)
	370	*data = readl(info->baseaddr + SYSCFG_RDATA);
	371
	372	info->cur_rsp_mask = 0;
	373	up(&info->sem);
	374
	375	return ret;
	376	}
	377
	378	static irqreturn_t ve_spc_irq_handler(int irq, void *data)
	379	{
	380	struct ve_spc_drvdata *drv_data = data;
	381	uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS);
	382
	383	if (info->cur_rsp_mask & status) {
	384	info->cur_rsp_stat = status;
	385	complete(&drv_data->done);
	386	}
	387
	388	return IRQ_HANDLED;
	389	}
	390
	391	/*
	392	* +--------------------------+
	393	* \| 31 20 \| 19 0 \|
	394	* +--------------------------+
cf2e0a73	395	* \| m_volt \| freq(kHz) \|
f7cd2d83 SH	396	* +--------------------------+
	397	*/
	398	#define MULT_FACTOR 20
	399	#define VOLT_SHIFT 20
	400	#define FREQ_MASK (0xFFFFF)
	401	static int ve_spc_populate_opps(uint32_t cluster)
	402	{
	403	uint32_t data = 0, off, ret, idx;
	404	struct ve_spc_opp *opps;
	405
	406	opps = kzalloc(sizeof(opps) MAX_OPPS, GFP_KERNEL);
	407	if (!opps)
	408	return -ENOMEM;
	409
	410	info->opps[cluster] = opps;
	411
	412	off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE;
	413	for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) {
	414	ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
	415	if (!ret) {
	416	opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
cf2e0a73	417	opps->u_volt = (data >> VOLT_SHIFT) * 1000;
f7cd2d83 SH	418	} else {
	419	break;
	420	}
	421	}
	422	info->num_opps[cluster] = idx;
	423
	424	return ret;
	425	}
	426
	427	static int ve_init_opp_table(struct device *cpu_dev)
	428	{
e160cc17 AS	429	int cluster;
	430	int idx, ret = 0, max_opp;
	431	struct ve_spc_opp *opps;
	432
	433	cluster = topology_physical_package_id(cpu_dev->id);
	434	cluster = cluster < 0 ? 0 : cluster;
	435
	436	max_opp = info->num_opps[cluster];
	437	opps = info->opps[cluster];
f7cd2d83 SH	438
	439	for (idx = 0; idx < max_opp; idx++, opps++) {
	440	ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
	441	if (ret) {
	442	dev_warn(cpu_dev, "failed to add opp %lu %lu\n",
	443	opps->freq, opps->u_volt);
	444	return ret;
	445	}
	446	}
	447	return ret;
	448	}
	449
	450	int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq)
63819cb1	451	{
f7cd2d83	452	int ret;
63819cb1 LP	453	info = kzalloc(sizeof(*info), GFP_KERNEL);
	454	if (!info) {
	455	pr_err(SPCLOG "unable to allocate mem\n");
	456	return -ENOMEM;
	457	}
	458
	459	info->baseaddr = baseaddr;
	460	info->a15_clusid = a15_clusid;
	461
f7cd2d83 SH	462	if (irq <= 0) {
	463	pr_err(SPCLOG "Invalid IRQ %d\n", irq);
	464	kfree(info);
	465	return -EINVAL;
	466	}
	467
	468	init_completion(&info->done);
	469
	470	readl_relaxed(info->baseaddr + PWC_STATUS);
	471
	472	ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH
	473	\| IRQF_ONESHOT, "vexpress-spc", info);
	474	if (ret) {
	475	pr_err(SPCLOG "IRQ %d request failed\n", irq);
	476	kfree(info);
	477	return -ENODEV;
	478	}
	479
	480	sema_init(&info->sem, 1);
63819cb1 LP	481	/*
	482	* Multi-cluster systems may need this data when non-coherent, during
	483	* cluster power-up/power-down. Make sure driver info reaches main
	484	* memory.
	485	*/
	486	sync_cache_w(info);
	487	sync_cache_w(&info);
	488
	489	return 0;
	490	}
4d910d5b SH	491
	492	struct clk_spc {
	493	struct clk_hw hw;
	494	int cluster;
	495	};
	496
	497	#define to_clk_spc(spc) container_of(spc, struct clk_spc, hw)
	498	static unsigned long spc_recalc_rate(struct clk_hw *hw,
	499	unsigned long parent_rate)
	500	{
	501	struct clk_spc *spc = to_clk_spc(hw);
	502	u32 freq;
	503
	504	if (ve_spc_get_performance(spc->cluster, &freq))
	505	return -EIO;
	506
	507	return freq * 1000;
	508	}
	509
	510	static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
	511	unsigned long *parent_rate)
	512	{
	513	struct clk_spc *spc = to_clk_spc(hw);
	514
	515	return ve_spc_round_performance(spc->cluster, drate);
	516	}
	517
	518	static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
	519	unsigned long parent_rate)
	520	{
	521	struct clk_spc *spc = to_clk_spc(hw);
	522
	523	return ve_spc_set_performance(spc->cluster, rate / 1000);
	524	}
	525
	526	static struct clk_ops clk_spc_ops = {
	527	.recalc_rate = spc_recalc_rate,
	528	.round_rate = spc_round_rate,
	529	.set_rate = spc_set_rate,
	530	};
	531
	532	static struct clk ve_spc_clk_register(struct device cpu_dev)
	533	{
	534	struct clk_init_data init;
	535	struct clk_spc *spc;
	536
	537	spc = kzalloc(sizeof(*spc), GFP_KERNEL);
	538	if (!spc) {
	539	pr_err("could not allocate spc clk\n");
	540	return ERR_PTR(-ENOMEM);
	541	}
	542
	543	spc->hw.init = &init;
	544	spc->cluster = topology_physical_package_id(cpu_dev->id);
	545
e160cc17 AS	546	spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
e160cc17 AS	547
4d910d5b SH	548	init.name = dev_name(cpu_dev);
4d910d5b SH	549	init.ops = &clk_spc_ops;
b52fc218	550	init.flags = CLK_GET_RATE_NOCACHE;
4d910d5b SH	551	init.num_parents = 0;
	552
	553	return devm_clk_register(cpu_dev, &spc->hw);
	554	}
	555
	556	static int __init ve_spc_clk_init(void)
	557	{
	558	int cpu;
	559	struct clk *clk;
	560
	561	if (!info)
	562	return 0; /* Continue only if SPC is initialised */
	563
	564	if (ve_spc_populate_opps(0) \|\| ve_spc_populate_opps(1)) {
	565	pr_err("failed to build OPP table\n");
	566	return -ENODEV;
	567	}
	568
	569	for_each_possible_cpu(cpu) {
	570	struct device *cpu_dev = get_cpu_device(cpu);
	571	if (!cpu_dev) {
	572	pr_warn("failed to get cpu%d device\n", cpu);
	573	continue;
	574	}
	575	clk = ve_spc_clk_register(cpu_dev);
	576	if (IS_ERR(clk)) {
	577	pr_warn("failed to register cpu%d clock\n", cpu);
	578	continue;
	579	}
	580	if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
	581	pr_warn("failed to register cpu%d clock lookup\n", cpu);
	582	continue;
	583	}
	584
	585	if (ve_init_opp_table(cpu_dev))
	586	pr_warn("failed to initialise cpu%d opp table\n", cpu);
	587	}
	588
9e941b6f	589	platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0);
4d910d5b SH	590	return 0;
4d910d5b SH	591	}
4a0ece7c	592	device_initcall(ve_spc_clk_init);