[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-w90x900 / gpio.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * linux/arch/arm/mach-w90x900/gpio.c
 *
 * Generic nuc900 GPIO handling
 *
 *  Wan ZongShun <mcuos.com@gmail.com>
 */

#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>

#include <mach/hardware.h>

#define GPIO_BASE 		(W90X900_VA_GPIO)
#define GPIO_DIR		(0x04)
#define GPIO_OUT		(0x08)
#define GPIO_IN			(0x0C)
#define GROUPINERV		(0x10)
#define GPIO_GPIO(Nb)		(0x00000001 << (Nb))

#define NUC900_GPIO_CHIP(name, base_gpio, nr_gpio)			\
	{								\
		.chip = {						\
			.label		  = name,			\
			.direction_input  = nuc900_dir_input,		\
			.direction_output = nuc900_dir_output,		\
			.get		  = nuc900_gpio_get,		\
			.set		  = nuc900_gpio_set,		\
			.base		  = base_gpio,			\
			.ngpio		  = nr_gpio,			\
		}							\
	}

struct nuc900_gpio_chip {
	struct gpio_chip	chip;
	void __iomem		*regbase;	/* Base of group register*/
	spinlock_t 		gpio_lock;
};

static int nuc900_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip);
	void __iomem *pio = nuc900_gpio->regbase + GPIO_IN;
	unsigned int regval;

	regval = __raw_readl(pio);
	regval &= GPIO_GPIO(offset);

	return (regval != 0);
}

static void nuc900_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip);
	void __iomem *pio = nuc900_gpio->regbase + GPIO_OUT;
	unsigned int regval;
	unsigned long flags;

	spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);

	regval = __raw_readl(pio);

	if (val)
		regval |= GPIO_GPIO(offset);
	else
		regval &= ~GPIO_GPIO(offset);

	__raw_writel(regval, pio);

	spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
}

static int nuc900_dir_input(struct gpio_chip *chip, unsigned offset)
{
	struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip);
	void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR;
	unsigned int regval;
	unsigned long flags;

	spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);

	regval = __raw_readl(pio);
	regval &= ~GPIO_GPIO(offset);
	__raw_writel(regval, pio);

	spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);

	return 0;
}

static int nuc900_dir_output(struct gpio_chip *chip, unsigned offset, int val)
{
	struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip);
	void __iomem *outreg = nuc900_gpio->regbase + GPIO_OUT;
	void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR;
	unsigned int regval;
	unsigned long flags;

	spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);

	regval = __raw_readl(pio);
	regval |= GPIO_GPIO(offset);
	__raw_writel(regval, pio);

	regval = __raw_readl(outreg);

	if (val)
		regval |= GPIO_GPIO(offset);
	else
		regval &= ~GPIO_GPIO(offset);

	__raw_writel(regval, outreg);

	spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);

	return 0;
}

static struct nuc900_gpio_chip nuc900_gpio[] = {
	NUC900_GPIO_CHIP("GROUPC", 0, 16),
	NUC900_GPIO_CHIP("GROUPD", 16, 10),
	NUC900_GPIO_CHIP("GROUPE", 26, 14),
	NUC900_GPIO_CHIP("GROUPF", 40, 10),
	NUC900_GPIO_CHIP("GROUPG", 50, 17),
	NUC900_GPIO_CHIP("GROUPH", 67, 8),
	NUC900_GPIO_CHIP("GROUPI", 75, 17),
};

void __init nuc900_init_gpio(int nr_group)
{
	unsigned	i;
	struct nuc900_gpio_chip *gpio_chip;

	for (i = 0; i < nr_group; i++) {
		gpio_chip = &nuc900_gpio[i];
		spin_lock_init(&gpio_chip->gpio_lock);
		gpio_chip->regbase = GPIO_BASE + i * GROUPINERV;
		gpiochip_add_data(&gpio_chip->chip, gpio_chip);
	}
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
c52d3d68	2	/*
35c9221a	3	* linux/arch/arm/mach-w90x900/gpio.c
c52d3d68	4	*
35c9221a	5	* Generic nuc900 GPIO handling
c52d3d68	6	*
c52d3d68	7	* Wan ZongShun <mcuos.com@gmail.com>
c52d3d68	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/errno.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14	#include <linux/debugfs.h>
	15	#include <linux/seq_file.h>
	16	#include <linux/kernel.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19	#include <linux/io.h>
c788aab7	20	#include <linux/gpio/driver.h>
c52d3d68	21
	22	#include <mach/hardware.h>
	23
	24	#define GPIO_BASE (W90X900_VA_GPIO)
	25	#define GPIO_DIR (0x04)
	26	#define GPIO_OUT (0x08)
	27	#define GPIO_IN (0x0C)
	28	#define GROUPINERV (0x10)
	29	#define GPIO_GPIO(Nb) (0x00000001 << (Nb))
c52d3d68	30
35c9221a	31	#define NUC900_GPIO_CHIP(name, base_gpio, nr_gpio) \
c52d3d68	32	{ \
	33	.chip = { \
	34	.label = name, \
35c9221a	35	.direction_input = nuc900_dir_input, \
	36	.direction_output = nuc900_dir_output, \
	37	.get = nuc900_gpio_get, \
	38	.set = nuc900_gpio_set, \
c52d3d68	39	.base = base_gpio, \
	40	.ngpio = nr_gpio, \
	41	} \
	42	}
	43
35c9221a	44	struct nuc900_gpio_chip {
c52d3d68	45	struct gpio_chip chip;
	46	void __iomem regbase; / Base of group register*/
	47	spinlock_t gpio_lock;
	48	};
	49
35c9221a	50	static int nuc900_gpio_get(struct gpio_chip *chip, unsigned offset)
c52d3d68	51	{
c788aab7	52	struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip);
35c9221a	53	void __iomem *pio = nuc900_gpio->regbase + GPIO_IN;
c52d3d68	54	unsigned int regval;
	55
	56	regval = __raw_readl(pio);
	57	regval &= GPIO_GPIO(offset);
	58
	59	return (regval != 0);
	60	}
	61
35c9221a	62	static void nuc900_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
c52d3d68	63	{
c788aab7	64	struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip);
35c9221a	65	void __iomem *pio = nuc900_gpio->regbase + GPIO_OUT;
c52d3d68	66	unsigned int regval;
	67	unsigned long flags;
	68
35c9221a	69	spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);
c52d3d68	70
	71	regval = __raw_readl(pio);
	72
	73	if (val)
	74	regval \|= GPIO_GPIO(offset);
	75	else
	76	regval &= ~GPIO_GPIO(offset);
	77
	78	__raw_writel(regval, pio);
	79
35c9221a	80	spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
c52d3d68	81	}
c52d3d68	82
35c9221a	83	static int nuc900_dir_input(struct gpio_chip *chip, unsigned offset)
c52d3d68	84	{
c788aab7	85	struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip);
35c9221a	86	void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR;
c52d3d68	87	unsigned int regval;
	88	unsigned long flags;
	89
35c9221a	90	spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);
c52d3d68	91
	92	regval = __raw_readl(pio);
	93	regval &= ~GPIO_GPIO(offset);
	94	__raw_writel(regval, pio);
	95
35c9221a	96	spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
c52d3d68	97
	98	return 0;
	99	}
	100
35c9221a	101	static int nuc900_dir_output(struct gpio_chip *chip, unsigned offset, int val)
c52d3d68	102	{
c788aab7	103	struct nuc900_gpio_chip *nuc900_gpio = gpiochip_get_data(chip);
35c9221a	104	void __iomem *outreg = nuc900_gpio->regbase + GPIO_OUT;
35c9221a	105	void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR;
c52d3d68	106	unsigned int regval;
	107	unsigned long flags;
	108
35c9221a	109	spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);
c52d3d68	110
	111	regval = __raw_readl(pio);
	112	regval \|= GPIO_GPIO(offset);
	113	__raw_writel(regval, pio);
	114
	115	regval = __raw_readl(outreg);
	116
	117	if (val)
	118	regval \|= GPIO_GPIO(offset);
	119	else
	120	regval &= ~GPIO_GPIO(offset);
	121
	122	__raw_writel(regval, outreg);
	123
35c9221a	124	spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
c52d3d68	125
	126	return 0;
	127	}
	128
35c9221a	129	static struct nuc900_gpio_chip nuc900_gpio[] = {
	130	NUC900_GPIO_CHIP("GROUPC", 0, 16),
	131	NUC900_GPIO_CHIP("GROUPD", 16, 10),
	132	NUC900_GPIO_CHIP("GROUPE", 26, 14),
	133	NUC900_GPIO_CHIP("GROUPF", 40, 10),
	134	NUC900_GPIO_CHIP("GROUPG", 50, 17),
	135	NUC900_GPIO_CHIP("GROUPH", 67, 8),
	136	NUC900_GPIO_CHIP("GROUPI", 75, 17),
c52d3d68	137	};
c52d3d68	138
35c9221a	139	void __init nuc900_init_gpio(int nr_group)
c52d3d68	140	{
c52d3d68	141	unsigned i;
35c9221a	142	struct nuc900_gpio_chip *gpio_chip;
c52d3d68	143
c52d3d68	144	for (i = 0; i < nr_group; i++) {
35c9221a	145	gpio_chip = &nuc900_gpio[i];
c52d3d68	146	spin_lock_init(&gpio_chip->gpio_lock);
c52d3d68	147	gpio_chip->regbase = GPIO_BASE + i * GROUPINERV;
c788aab7	148	gpiochip_add_data(&gpio_chip->chip, gpio_chip);
c52d3d68	149	}
c52d3d68	150	}