]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - arch/arm/mach-w90x900/time.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
[mirror_ubuntu-focal-kernel.git] / arch / arm / mach-w90x900 / time.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
7ec80ddf 2/*
3 * linux/arch/arm/mach-w90x900/time.c
4 *
5 * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
6 *
58b5369e 7 * Copyright (c) 2009 Nuvoton technology corporation
7ec80ddf 8 * All rights reserved.
9 *
10 * Wan ZongShun <mcuos.com@gmail.com>
7ec80ddf 11 */
12
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/leds.h>
58b5369e 21#include <linux/clocksource.h>
22#include <linux/clockchips.h>
7ec80ddf 23
24#include <asm/mach-types.h>
25#include <asm/mach/irq.h>
26#include <asm/mach/time.h>
27
7ec80ddf 28#include <mach/map.h>
1d8f3c49 29#include "regs-timer.h"
7ec80ddf 30
e5bc9e25
RK
31#include "nuc9xx.h"
32
58b5369e 33#define RESETINT 0x1f
34#define PERIOD (0x01 << 27)
35#define ONESHOT (0x00 << 27)
36#define COUNTEN (0x01 << 30)
37#define INTEN (0x01 << 29)
38
39#define TICKS_PER_SEC 100
40#define PRESCALE 0x63 /* Divider = prescale + 1 */
41
1368c51c 42#define TDR_SHIFT 24
1368c51c
LJ
43
44static unsigned int timer0_load;
58b5369e 45
6c724d43 46static int nuc900_clockevent_shutdown(struct clock_event_device *evt)
7ec80ddf 47{
6c724d43 48 unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27);
58b5369e 49
6c724d43
VK
50 __raw_writel(val, REG_TCSR0);
51 return 0;
52}
53
54static int nuc900_clockevent_set_oneshot(struct clock_event_device *evt)
55{
56 unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27);
58b5369e 57
6c724d43 58 val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
58b5369e 59
6c724d43
VK
60 __raw_writel(val, REG_TCSR0);
61 return 0;
62}
58b5369e 63
6c724d43
VK
64static int nuc900_clockevent_set_periodic(struct clock_event_device *evt)
65{
66 unsigned int val = __raw_readl(REG_TCSR0) & ~(0x03 << 27);
58b5369e 67
6c724d43
VK
68 __raw_writel(timer0_load, REG_TICR0);
69 val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
58b5369e 70 __raw_writel(val, REG_TCSR0);
6c724d43 71 return 0;
58b5369e 72}
73
35c9221a 74static int nuc900_clockevent_setnextevent(unsigned long evt,
58b5369e 75 struct clock_event_device *clk)
76{
77 unsigned int val;
78
79 __raw_writel(evt, REG_TICR0);
80
81 val = __raw_readl(REG_TCSR0);
82 val |= (COUNTEN | INTEN | PRESCALE);
83 __raw_writel(val, REG_TCSR0);
84
7ec80ddf 85 return 0;
86}
87
35c9221a 88static struct clock_event_device nuc900_clockevent_device = {
6c724d43
VK
89 .name = "nuc900-timer0",
90 .features = CLOCK_EVT_FEAT_PERIODIC |
91 CLOCK_EVT_FEAT_ONESHOT,
92 .set_state_shutdown = nuc900_clockevent_shutdown,
93 .set_state_periodic = nuc900_clockevent_set_periodic,
94 .set_state_oneshot = nuc900_clockevent_set_oneshot,
95 .tick_resume = nuc900_clockevent_shutdown,
96 .set_next_event = nuc900_clockevent_setnextevent,
97 .rating = 300,
58b5369e 98};
99
7ec80ddf 100/*IRQ handler for the timer*/
101
35c9221a 102static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
7ec80ddf 103{
35c9221a 104 struct clock_event_device *evt = &nuc900_clockevent_device;
58b5369e 105
7ec80ddf 106 __raw_writel(0x01, REG_TISR); /* clear TIF0 */
58b5369e 107
108 evt->event_handler(evt);
7ec80ddf 109 return IRQ_HANDLED;
110}
111
35c9221a 112static struct irqaction nuc900_timer0_irq = {
113 .name = "nuc900-timer0",
2ed71e75 114 .flags = IRQF_TIMER | IRQF_IRQPOLL,
35c9221a 115 .handler = nuc900_timer0_interrupt,
7ec80ddf 116};
117
1368c51c 118static void __init nuc900_clockevents_init(void)
58b5369e 119{
1368c51c
LJ
120 unsigned int rate;
121 struct clk *clk = clk_get(NULL, "timer0");
122
123 BUG_ON(IS_ERR(clk));
124
125 __raw_writel(0x00, REG_TCSR0);
126
127 clk_enable(clk);
128 rate = clk_get_rate(clk) / (PRESCALE + 1);
129
130 timer0_load = (rate / TICKS_PER_SEC);
131
132 __raw_writel(RESETINT, REG_TISR);
133 setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
134
35c9221a 135 nuc900_clockevent_device.cpumask = cpumask_of(0);
136
838a2ae8
SG
137 clockevents_config_and_register(&nuc900_clockevent_device, rate,
138 0xf, 0xffffffff);
58b5369e 139}
140
1368c51c 141static void __init nuc900_clocksource_init(void)
7ec80ddf 142{
58b5369e 143 unsigned int val;
1368c51c
LJ
144 unsigned int rate;
145 struct clk *clk = clk_get(NULL, "timer1");
146
147 BUG_ON(IS_ERR(clk));
148
149 __raw_writel(0x00, REG_TCSR1);
150
151 clk_enable(clk);
152 rate = clk_get_rate(clk) / (PRESCALE + 1);
58b5369e 153
154 __raw_writel(0xffffffff, REG_TICR1);
155
156 val = __raw_readl(REG_TCSR1);
1368c51c 157 val |= (COUNTEN | PERIOD | PRESCALE);
58b5369e 158 __raw_writel(val, REG_TCSR1);
159
6fa5d5f7
RK
160 clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200,
161 TDR_SHIFT, clocksource_mmio_readl_down);
58b5369e 162}
163
6bb27d73 164void __init nuc900_timer_init(void)
58b5369e 165{
1368c51c
LJ
166 nuc900_clocksource_init();
167 nuc900_clockevents_init();
7ec80ddf 168}