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9c92ab61 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b85a3ef4 JL |
2 | /* |
3 | * This file contains common code that is intended to be used across | |
4 | * boards so that it's not replicated. | |
5 | * | |
6 | * Copyright (C) 2011 Xilinx | |
b85a3ef4 JL |
7 | */ |
8 | ||
9 | #include <linux/init.h> | |
62e59c4e | 10 | #include <linux/io.h> |
b85a3ef4 JL |
11 | #include <linux/kernel.h> |
12 | #include <linux/cpumask.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/clk.h> | |
4a32c74e | 15 | #include <linux/clk-provider.h> |
0f586fbf | 16 | #include <linux/clk/zynq.h> |
e932900a | 17 | #include <linux/clocksource.h> |
0f586fbf | 18 | #include <linux/of_address.h> |
b85a3ef4 JL |
19 | #include <linux/of_irq.h> |
20 | #include <linux/of_platform.h> | |
3d64b449 | 21 | #include <linux/of.h> |
46f5b960 | 22 | #include <linux/memblock.h> |
9f4f5d26 SB |
23 | #include <linux/irqchip.h> |
24 | #include <linux/irqchip/arm-gic.h> | |
00f7dc63 MS |
25 | #include <linux/slab.h> |
26 | #include <linux/sys_soc.h> | |
b85a3ef4 | 27 | |
3d64b449 | 28 | #include <asm/mach/arch.h> |
b85a3ef4 | 29 | #include <asm/mach/map.h> |
03e07595 | 30 | #include <asm/mach/time.h> |
3d64b449 | 31 | #include <asm/mach-types.h> |
b85a3ef4 | 32 | #include <asm/page.h> |
9a45eb69 | 33 | #include <asm/pgtable.h> |
732078c3 | 34 | #include <asm/smp_scu.h> |
00f7dc63 | 35 | #include <asm/system_info.h> |
b85a3ef4 JL |
36 | #include <asm/hardware/cache-l2x0.h> |
37 | ||
b85a3ef4 JL |
38 | #include "common.h" |
39 | ||
00f7dc63 MS |
40 | #define ZYNQ_DEVCFG_MCTRL 0x80 |
41 | #define ZYNQ_DEVCFG_PS_VERSION_SHIFT 28 | |
42 | #define ZYNQ_DEVCFG_PS_VERSION_MASK 0xF | |
43 | ||
732078c3 MS |
44 | void __iomem *zynq_scu_base; |
45 | ||
46f5b960 MS |
46 | /** |
47 | * zynq_memory_init - Initialize special memory | |
48 | * | |
49 | * We need to stop things allocating the low memory as DMA can't work in | |
50 | * the 1st 512K of memory. | |
51 | */ | |
52 | static void __init zynq_memory_init(void) | |
53 | { | |
54 | if (!__pa(PAGE_OFFSET)) | |
7a3cc2a7 | 55 | memblock_reserve(__pa(PAGE_OFFSET), 0x80000); |
46f5b960 MS |
56 | } |
57 | ||
3e8ceca6 DL |
58 | static struct platform_device zynq_cpuidle_device = { |
59 | .name = "cpuidle-zynq", | |
60 | }; | |
61 | ||
00f7dc63 MS |
62 | /** |
63 | * zynq_get_revision - Get Zynq silicon revision | |
64 | * | |
65 | * Return: Silicon version or -1 otherwise | |
66 | */ | |
67 | static int __init zynq_get_revision(void) | |
68 | { | |
69 | struct device_node *np; | |
70 | void __iomem *zynq_devcfg_base; | |
71 | u32 revision; | |
72 | ||
73 | np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0"); | |
74 | if (!np) { | |
75 | pr_err("%s: no devcfg node found\n", __func__); | |
76 | return -1; | |
77 | } | |
78 | ||
79 | zynq_devcfg_base = of_iomap(np, 0); | |
80 | if (!zynq_devcfg_base) { | |
81 | pr_err("%s: Unable to map I/O memory\n", __func__); | |
82 | return -1; | |
83 | } | |
84 | ||
85 | revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL); | |
86 | revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT; | |
87 | revision &= ZYNQ_DEVCFG_PS_VERSION_MASK; | |
88 | ||
89 | iounmap(zynq_devcfg_base); | |
90 | ||
91 | return revision; | |
92 | } | |
93 | ||
ae88b85e SB |
94 | static void __init zynq_init_late(void) |
95 | { | |
96 | zynq_core_pm_init(); | |
0beb2bd3 | 97 | zynq_pm_late_init(); |
ae88b85e SB |
98 | } |
99 | ||
b85a3ef4 | 100 | /** |
889faa88 MS |
101 | * zynq_init_machine - System specific initialization, intended to be |
102 | * called from board specific initialization. | |
b85a3ef4 | 103 | */ |
889faa88 | 104 | static void __init zynq_init_machine(void) |
b85a3ef4 | 105 | { |
00f7dc63 MS |
106 | struct soc_device_attribute *soc_dev_attr; |
107 | struct soc_device *soc_dev; | |
108 | struct device *parent = NULL; | |
cd325295 | 109 | |
00f7dc63 MS |
110 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); |
111 | if (!soc_dev_attr) | |
112 | goto out; | |
113 | ||
114 | system_rev = zynq_get_revision(); | |
115 | ||
116 | soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq"); | |
117 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev); | |
118 | soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x", | |
119 | zynq_slcr_get_device_id()); | |
120 | ||
121 | soc_dev = soc_device_register(soc_dev_attr); | |
122 | if (IS_ERR(soc_dev)) { | |
123 | kfree(soc_dev_attr->family); | |
124 | kfree(soc_dev_attr->revision); | |
125 | kfree(soc_dev_attr->soc_id); | |
126 | kfree(soc_dev_attr); | |
127 | goto out; | |
128 | } | |
129 | ||
130 | parent = soc_device_to_device(soc_dev); | |
131 | ||
132 | out: | |
133 | /* | |
134 | * Finished with the static registrations now; fill in the missing | |
135 | * devices | |
136 | */ | |
435ebcbc | 137 | of_platform_default_populate(NULL, NULL, parent); |
3e8ceca6 DL |
138 | |
139 | platform_device_register(&zynq_cpuidle_device); | |
b85a3ef4 JL |
140 | } |
141 | ||
889faa88 | 142 | static void __init zynq_timer_init(void) |
03e07595 | 143 | { |
b0504e39 | 144 | zynq_clock_init(); |
4a32c74e | 145 | of_clk_init(NULL); |
ba5d08c0 | 146 | timer_probe(); |
03e07595 JC |
147 | } |
148 | ||
732078c3 MS |
149 | static struct map_desc zynq_cortex_a9_scu_map __initdata = { |
150 | .length = SZ_256, | |
151 | .type = MT_DEVICE, | |
152 | }; | |
153 | ||
154 | static void __init zynq_scu_map_io(void) | |
155 | { | |
156 | unsigned long base; | |
157 | ||
158 | base = scu_a9_get_base(); | |
159 | zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base); | |
160 | /* Expected address is in vmalloc area that's why simple assign here */ | |
161 | zynq_cortex_a9_scu_map.virtual = base; | |
162 | iotable_init(&zynq_cortex_a9_scu_map, 1); | |
163 | zynq_scu_base = (void __iomem *)base; | |
164 | BUG_ON(!zynq_scu_base); | |
165 | } | |
166 | ||
b85a3ef4 | 167 | /** |
889faa88 | 168 | * zynq_map_io - Create memory mappings needed for early I/O. |
b85a3ef4 | 169 | */ |
889faa88 | 170 | static void __init zynq_map_io(void) |
b85a3ef4 | 171 | { |
385f02b1 | 172 | debug_ll_io_init(); |
732078c3 | 173 | zynq_scu_map_io(); |
b85a3ef4 | 174 | } |
3d64b449 | 175 | |
9f4f5d26 SB |
176 | static void __init zynq_irq_init(void) |
177 | { | |
9388187f | 178 | zynq_early_slcr_init(); |
9f4f5d26 SB |
179 | irqchip_init(); |
180 | } | |
181 | ||
889faa88 | 182 | static const char * const zynq_dt_match[] = { |
e06f1a9e | 183 | "xlnx,zynq-7000", |
3d64b449 AB |
184 | NULL |
185 | }; | |
186 | ||
514a5908 | 187 | DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") |
dcf9c7f9 | 188 | /* 64KB way size, 8-way associativity, parity disabled */ |
6632d4fd TB |
189 | .l2c_aux_val = 0x00400000, |
190 | .l2c_aux_mask = 0xffbfffff, | |
aa7eb2bb | 191 | .smp = smp_ops(zynq_smp_ops), |
889faa88 | 192 | .map_io = zynq_map_io, |
9f4f5d26 | 193 | .init_irq = zynq_irq_init, |
889faa88 | 194 | .init_machine = zynq_init_machine, |
ae88b85e | 195 | .init_late = zynq_init_late, |
889faa88 MS |
196 | .init_time = zynq_timer_init, |
197 | .dt_compat = zynq_dt_match, | |
46f5b960 | 198 | .reserve = zynq_memory_init, |
3d64b449 | 199 | MACHINE_END |