[mirror_ubuntu-artful-kernel.git] / arch / arm / mm / cache-l2x0.c

/*
 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
 *
 * Copyright (C) 2007 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>

#define CACHE_LINE_SIZE		32

static void __iomem *l2x0_base;
static DEFINE_SPINLOCK(l2x0_lock);
static uint32_t l2x0_way_mask;	/* Bitmask of active ways */

static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
{
	/* wait for cache operation by line or way to complete */
	while (readl_relaxed(reg) & mask)
		;
}

#ifdef CONFIG_CACHE_PL310
static inline void cache_wait(void __iomem *reg, unsigned long mask)
{
	/* cache operations by line are atomic on PL310 */
}
#else
#define cache_wait	cache_wait_way
#endif

static inline void cache_sync(void)
{
	void __iomem *base = l2x0_base;
	writel_relaxed(0, base + L2X0_CACHE_SYNC);
	cache_wait(base + L2X0_CACHE_SYNC, 1);
}

static inline void l2x0_clean_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
}

static inline void l2x0_inv_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}

#ifdef CONFIG_PL310_ERRATA_588369
static void debug_writel(unsigned long val)
{
	extern void omap_smc1(u32 fn, u32 arg);

	/*
	 * Texas Instrument secure monitor api to modify the
	 * PL310 Debug Control Register.
	 */
	omap_smc1(0x100, val);
}

static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;

	/* Clean by PA followed by Invalidate by PA */
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}
#else

/* Optimised out for non-errata case */
static inline void debug_writel(unsigned long val)
{
}

static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
}
#endif

static void l2x0_cache_sync(void)
{
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_flush_all(void)
{
	unsigned long flags;

	/* clean all ways */
	spin_lock_irqsave(&l2x0_lock, flags);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_inv_all(void)
{
	unsigned long flags;

	/* invalidate all ways */
	spin_lock_irqsave(&l2x0_lock, flags);
	/* Invalidating when L2 is enabled is a nono */
	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_inv_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	if (start & (CACHE_LINE_SIZE - 1)) {
		start &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(start);
		debug_writel(0x00);
		start += CACHE_LINE_SIZE;
	}

	if (end & (CACHE_LINE_SIZE - 1)) {
		end &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(end);
		debug_writel(0x00);
	}

	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_inv_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			spin_unlock_irqrestore(&l2x0_lock, flags);
			spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_clean_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_clean_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			spin_unlock_irqrestore(&l2x0_lock, flags);
			spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_flush_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		debug_writel(0x03);
		while (start < blk_end) {
			l2x0_flush_line(start);
			start += CACHE_LINE_SIZE;
		}
		debug_writel(0x00);

		if (blk_end < end) {
			spin_unlock_irqrestore(&l2x0_lock, flags);
			spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_disable(void)
{
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	writel(0, l2x0_base + L2X0_CTRL);
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
	__u32 aux;
	__u32 cache_id;
	int ways;
	const char *type;

	l2x0_base = base;

	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);

	aux &= aux_mask;
	aux |= aux_val;

	/* Determine the number of ways */
	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	case L2X0_CACHE_ID_PART_L310:
		if (aux & (1 << 16))
			ways = 16;
		else
			ways = 8;
		type = "L310";
		break;
	case L2X0_CACHE_ID_PART_L210:
		ways = (aux >> 13) & 0xf;
		type = "L210";
		break;
	default:
		/* Assume unknown chips have 8 ways */
		ways = 8;
		type = "L2x0 series";
		break;
	}

	l2x0_way_mask = (1 << ways) - 1;

	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {

		/* l2x0 controller is disabled */
		writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);

		l2x0_inv_all();

		/* enable L2X0 */
		writel_relaxed(1, l2x0_base + L2X0_CTRL);
	}

	outer_cache.inv_range = l2x0_inv_range;
	outer_cache.clean_range = l2x0_clean_range;
	outer_cache.flush_range = l2x0_flush_range;
	outer_cache.sync = l2x0_cache_sync;
	outer_cache.flush_all = l2x0_flush_all;
	outer_cache.inv_all = l2x0_inv_all;
	outer_cache.disable = l2x0_disable;

	printk(KERN_INFO "%s cache controller enabled\n", type);
	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
			 ways, cache_id, aux);
}
Commit	Line	Data
382266ad CM	1	/*
	2	* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
	3	*
	4	* Copyright (C) 2007 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19	#include <linux/init.h>
07620976	20	#include <linux/spinlock.h>
fced80c7	21	#include <linux/io.h>
382266ad CM	22
382266ad CM	23	#include <asm/cacheflush.h>
382266ad CM	24	#include <asm/hardware/cache-l2x0.h>
	25
	26	#define CACHE_LINE_SIZE 32
	27
	28	static void __iomem *l2x0_base;
07620976	29	static DEFINE_SPINLOCK(l2x0_lock);
64039be8	30	static uint32_t l2x0_way_mask; /* Bitmask of active ways */
382266ad	31
9a6655e4	32	static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
382266ad	33	{
9a6655e4	34	/* wait for cache operation by line or way to complete */
6775a558	35	while (readl_relaxed(reg) & mask)
382266ad CM	36	;
	37	}
	38
9a6655e4 CM	39	#ifdef CONFIG_CACHE_PL310
	40	static inline void cache_wait(void __iomem *reg, unsigned long mask)
	41	{
	42	/* cache operations by line are atomic on PL310 */
	43	}
	44	#else
	45	#define cache_wait cache_wait_way
	46	#endif
	47
382266ad CM	48	static inline void cache_sync(void)
382266ad CM	49	{
3d107434	50	void __iomem *base = l2x0_base;
6775a558	51	writel_relaxed(0, base + L2X0_CACHE_SYNC);
3d107434	52	cache_wait(base + L2X0_CACHE_SYNC, 1);
382266ad CM	53	}
382266ad CM	54
424d6b14 SS	55	static inline void l2x0_clean_line(unsigned long addr)
	56	{
	57	void __iomem *base = l2x0_base;
	58	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
6775a558	59	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
424d6b14 SS	60	}
	61
	62	static inline void l2x0_inv_line(unsigned long addr)
	63	{
	64	void __iomem *base = l2x0_base;
	65	cache_wait(base + L2X0_INV_LINE_PA, 1);
6775a558	66	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
424d6b14 SS	67	}
424d6b14 SS	68
9e65582a SS	69	#ifdef CONFIG_PL310_ERRATA_588369
	70	static void debug_writel(unsigned long val)
	71	{
	72	extern void omap_smc1(u32 fn, u32 arg);
	73
	74	/*
	75	* Texas Instrument secure monitor api to modify the
	76	* PL310 Debug Control Register.
	77	*/
	78	omap_smc1(0x100, val);
	79	}
	80
	81	static inline void l2x0_flush_line(unsigned long addr)
	82	{
	83	void __iomem *base = l2x0_base;
	84
	85	/* Clean by PA followed by Invalidate by PA */
	86	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
6775a558	87	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
9e65582a	88	cache_wait(base + L2X0_INV_LINE_PA, 1);
6775a558	89	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
9e65582a SS	90	}
	91	#else
	92
	93	/* Optimised out for non-errata case */
	94	static inline void debug_writel(unsigned long val)
	95	{
	96	}
	97
424d6b14 SS	98	static inline void l2x0_flush_line(unsigned long addr)
	99	{
	100	void __iomem *base = l2x0_base;
	101	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
6775a558	102	writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
424d6b14	103	}
9e65582a	104	#endif
424d6b14	105
23107c54 CM	106	static void l2x0_cache_sync(void)
	107	{
	108	unsigned long flags;
	109
	110	spin_lock_irqsave(&l2x0_lock, flags);
	111	cache_sync();
	112	spin_unlock_irqrestore(&l2x0_lock, flags);
	113	}
	114
2fd86589 TG	115	static void l2x0_flush_all(void)
	116	{
	117	unsigned long flags;
	118
	119	/* clean all ways */
	120	spin_lock_irqsave(&l2x0_lock, flags);
	121	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
	122	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
	123	cache_sync();
	124	spin_unlock_irqrestore(&l2x0_lock, flags);
	125	}
	126
	127	static void l2x0_inv_all(void)
382266ad	128	{
0eb948dd RK	129	unsigned long flags;
0eb948dd RK	130
382266ad	131	/* invalidate all ways */
0eb948dd	132	spin_lock_irqsave(&l2x0_lock, flags);
2fd86589 TG	133	/* Invalidating when L2 is enabled is a nono */
2fd86589 TG	134	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
6775a558	135	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
9a6655e4	136	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
382266ad	137	cache_sync();
0eb948dd	138	spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	139	}
	140
	141	static void l2x0_inv_range(unsigned long start, unsigned long end)
	142	{
3d107434	143	void __iomem *base = l2x0_base;
0eb948dd	144	unsigned long flags;
382266ad	145
0eb948dd	146	spin_lock_irqsave(&l2x0_lock, flags);
4f6627ac RS	147	if (start & (CACHE_LINE_SIZE - 1)) {
4f6627ac RS	148	start &= ~(CACHE_LINE_SIZE - 1);
9e65582a	149	debug_writel(0x03);
424d6b14	150	l2x0_flush_line(start);
9e65582a	151	debug_writel(0x00);
4f6627ac RS	152	start += CACHE_LINE_SIZE;
	153	}
	154
	155	if (end & (CACHE_LINE_SIZE - 1)) {
	156	end &= ~(CACHE_LINE_SIZE - 1);
9e65582a	157	debug_writel(0x03);
424d6b14	158	l2x0_flush_line(end);
9e65582a	159	debug_writel(0x00);
4f6627ac RS	160	}
4f6627ac RS	161
0eb948dd RK	162	while (start < end) {
	163	unsigned long blk_end = start + min(end - start, 4096UL);
	164
	165	while (start < blk_end) {
424d6b14	166	l2x0_inv_line(start);
0eb948dd RK	167	start += CACHE_LINE_SIZE;
	168	}
	169
	170	if (blk_end < end) {
	171	spin_unlock_irqrestore(&l2x0_lock, flags);
	172	spin_lock_irqsave(&l2x0_lock, flags);
	173	}
	174	}
3d107434	175	cache_wait(base + L2X0_INV_LINE_PA, 1);
382266ad	176	cache_sync();
0eb948dd	177	spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	178	}
	179
	180	static void l2x0_clean_range(unsigned long start, unsigned long end)
	181	{
3d107434	182	void __iomem *base = l2x0_base;
0eb948dd	183	unsigned long flags;
382266ad	184
0eb948dd	185	spin_lock_irqsave(&l2x0_lock, flags);
382266ad	186	start &= ~(CACHE_LINE_SIZE - 1);
0eb948dd RK	187	while (start < end) {
	188	unsigned long blk_end = start + min(end - start, 4096UL);
	189
	190	while (start < blk_end) {
424d6b14	191	l2x0_clean_line(start);
0eb948dd RK	192	start += CACHE_LINE_SIZE;
	193	}
	194
	195	if (blk_end < end) {
	196	spin_unlock_irqrestore(&l2x0_lock, flags);
	197	spin_lock_irqsave(&l2x0_lock, flags);
	198	}
	199	}
3d107434	200	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
382266ad	201	cache_sync();
0eb948dd	202	spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	203	}
	204
	205	static void l2x0_flush_range(unsigned long start, unsigned long end)
	206	{
3d107434	207	void __iomem *base = l2x0_base;
0eb948dd	208	unsigned long flags;
382266ad	209
0eb948dd	210	spin_lock_irqsave(&l2x0_lock, flags);
382266ad	211	start &= ~(CACHE_LINE_SIZE - 1);
0eb948dd RK	212	while (start < end) {
	213	unsigned long blk_end = start + min(end - start, 4096UL);
	214
9e65582a	215	debug_writel(0x03);
0eb948dd	216	while (start < blk_end) {
424d6b14	217	l2x0_flush_line(start);
0eb948dd RK	218	start += CACHE_LINE_SIZE;
0eb948dd RK	219	}
9e65582a	220	debug_writel(0x00);
0eb948dd RK	221
	222	if (blk_end < end) {
	223	spin_unlock_irqrestore(&l2x0_lock, flags);
	224	spin_lock_irqsave(&l2x0_lock, flags);
	225	}
	226	}
3d107434	227	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
382266ad	228	cache_sync();
0eb948dd	229	spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	230	}
382266ad CM	231
2fd86589 TG	232	static void l2x0_disable(void)
	233	{
	234	unsigned long flags;
	235
	236	spin_lock_irqsave(&l2x0_lock, flags);
	237	writel(0, l2x0_base + L2X0_CTRL);
	238	spin_unlock_irqrestore(&l2x0_lock, flags);
	239	}
	240
382266ad CM	241	void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
	242	{
	243	__u32 aux;
64039be8 JM	244	__u32 cache_id;
	245	int ways;
	246	const char *type;
382266ad CM	247
	248	l2x0_base = base;
	249
6775a558 CM	250	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
6775a558 CM	251	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
64039be8	252
4082cfa7 SH	253	aux &= aux_mask;
	254	aux \|= aux_val;
	255
64039be8 JM	256	/* Determine the number of ways */
	257	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	258	case L2X0_CACHE_ID_PART_L310:
	259	if (aux & (1 << 16))
	260	ways = 16;
	261	else
	262	ways = 8;
	263	type = "L310";
	264	break;
	265	case L2X0_CACHE_ID_PART_L210:
	266	ways = (aux >> 13) & 0xf;
	267	type = "L210";
	268	break;
	269	default:
	270	/* Assume unknown chips have 8 ways */
	271	ways = 8;
	272	type = "L2x0 series";
	273	break;
	274	}
	275
	276	l2x0_way_mask = (1 << ways) - 1;
	277
48371cd3 SK	278	/*
	279	* Check if l2x0 controller is already enabled.
	280	* If you are booting from non-secure mode
	281	* accessing the below registers will fault.
	282	*/
6775a558	283	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
382266ad	284
48371cd3	285	/* l2x0 controller is disabled */
6775a558	286	writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
382266ad	287
48371cd3 SK	288	l2x0_inv_all();
	289
	290	/* enable L2X0 */
6775a558	291	writel_relaxed(1, l2x0_base + L2X0_CTRL);
48371cd3	292	}
382266ad CM	293
	294	outer_cache.inv_range = l2x0_inv_range;
	295	outer_cache.clean_range = l2x0_clean_range;
	296	outer_cache.flush_range = l2x0_flush_range;
23107c54	297	outer_cache.sync = l2x0_cache_sync;
2fd86589 TG	298	outer_cache.flush_all = l2x0_flush_all;
	299	outer_cache.inv_all = l2x0_inv_all;
	300	outer_cache.disable = l2x0_disable;
382266ad	301
64039be8 JM	302	printk(KERN_INFO "%s cache controller enabled\n", type);
	303	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
	304	ways, cache_id, aux);
382266ad	305	}