[mirror_ubuntu-artful-kernel.git] / arch / arm / mm / cache-l2x0.c

/*
 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
 *
 * Copyright (C) 2007 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>

#define CACHE_LINE_SIZE		32

static void __iomem *l2x0_base;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static u32 l2x0_way_mask;	/* Bitmask of active ways */
static u32 l2x0_size;
static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;

struct l2x0_regs l2x0_saved_regs;

struct l2x0_of_data {
	void (*setup)(const struct device_node *, u32 *, u32 *);
	void (*save)(void);
	struct outer_cache_fns outer_cache;
};

static bool of_init = false;

static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
{
	/* wait for cache operation by line or way to complete */
	while (readl_relaxed(reg) & mask)
		cpu_relax();
}

#ifdef CONFIG_CACHE_PL310
static inline void cache_wait(void __iomem *reg, unsigned long mask)
{
	/* cache operations by line are atomic on PL310 */
}
#else
#define cache_wait	cache_wait_way
#endif

static inline void cache_sync(void)
{
	void __iomem *base = l2x0_base;

	writel_relaxed(0, base + sync_reg_offset);
	cache_wait(base + L2X0_CACHE_SYNC, 1);
}

static inline void l2x0_clean_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
}

static inline void l2x0_inv_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}

#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
static inline void debug_writel(unsigned long val)
{
	if (outer_cache.set_debug)
		outer_cache.set_debug(val);
}

static void pl310_set_debug(unsigned long val)
{
	writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
}
#else
/* Optimised out for non-errata case */
static inline void debug_writel(unsigned long val)
{
}

#define pl310_set_debug	NULL
#endif

#ifdef CONFIG_PL310_ERRATA_588369
static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;

	/* Clean by PA followed by Invalidate by PA */
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}
#else

static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
}
#endif

static void l2x0_cache_sync(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void __l2x0_flush_all(void)
{
	debug_writel(0x03);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
	cache_sync();
	debug_writel(0x00);
}

static void l2x0_flush_all(void)
{
	unsigned long flags;

	/* clean all ways */
	raw_spin_lock_irqsave(&l2x0_lock, flags);
	__l2x0_flush_all();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_clean_all(void)
{
	unsigned long flags;

	/* clean all ways */
	raw_spin_lock_irqsave(&l2x0_lock, flags);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
	cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_inv_all(void)
{
	unsigned long flags;

	/* invalidate all ways */
	raw_spin_lock_irqsave(&l2x0_lock, flags);
	/* Invalidating when L2 is enabled is a nono */
	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_inv_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	if (start & (CACHE_LINE_SIZE - 1)) {
		start &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(start);
		debug_writel(0x00);
		start += CACHE_LINE_SIZE;
	}

	if (end & (CACHE_LINE_SIZE - 1)) {
		end &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(end);
		debug_writel(0x00);
	}

	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_inv_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			raw_spin_unlock_irqrestore(&l2x0_lock, flags);
			raw_spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_clean_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	if ((end - start) >= l2x0_size) {
		l2x0_clean_all();
		return;
	}

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_clean_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			raw_spin_unlock_irqrestore(&l2x0_lock, flags);
			raw_spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_flush_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	if ((end - start) >= l2x0_size) {
		l2x0_flush_all();
		return;
	}

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		debug_writel(0x03);
		while (start < blk_end) {
			l2x0_flush_line(start);
			start += CACHE_LINE_SIZE;
		}
		debug_writel(0x00);

		if (blk_end < end) {
			raw_spin_unlock_irqrestore(&l2x0_lock, flags);
			raw_spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_disable(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	__l2x0_flush_all();
	writel_relaxed(0, l2x0_base + L2X0_CTRL);
	dsb();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_unlock(u32 cache_id)
{
	int lockregs;
	int i;

	if (cache_id == L2X0_CACHE_ID_PART_L310)
		lockregs = 8;
	else
		/* L210 and unknown types */
		lockregs = 1;

	for (i = 0; i < lockregs; i++) {
		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
			       i * L2X0_LOCKDOWN_STRIDE);
		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
			       i * L2X0_LOCKDOWN_STRIDE);
	}
}

void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
{
	u32 aux;
	u32 cache_id;
	u32 way_size = 0;
	int ways;
	const char *type;

	l2x0_base = base;

	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);

	aux &= aux_mask;
	aux |= aux_val;

	/* Determine the number of ways */
	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	case L2X0_CACHE_ID_PART_L310:
		if (aux & (1 << 16))
			ways = 16;
		else
			ways = 8;
		type = "L310";
#ifdef CONFIG_PL310_ERRATA_753970
		/* Unmapped register. */
		sync_reg_offset = L2X0_DUMMY_REG;
#endif
		outer_cache.set_debug = pl310_set_debug;
		break;
	case L2X0_CACHE_ID_PART_L210:
		ways = (aux >> 13) & 0xf;
		type = "L210";
		break;
	default:
		/* Assume unknown chips have 8 ways */
		ways = 8;
		type = "L2x0 series";
		break;
	}

	l2x0_way_mask = (1 << ways) - 1;

	/*
	 * L2 cache Size =  Way size * Number of ways
	 */
	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
	way_size = 1 << (way_size + 3);
	l2x0_size = ways * way_size * SZ_1K;

	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
		/* Make sure that I&D is not locked down when starting */
		l2x0_unlock(cache_id);

		/* l2x0 controller is disabled */
		writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);

		l2x0_inv_all();

		/* enable L2X0 */
		writel_relaxed(1, l2x0_base + L2X0_CTRL);
	}

	/* Re-read it in case some bits are reserved. */
	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);

	/* Save the value for resuming. */
	l2x0_saved_regs.aux_ctrl = aux;

	if (!of_init) {
		outer_cache.inv_range = l2x0_inv_range;
		outer_cache.clean_range = l2x0_clean_range;
		outer_cache.flush_range = l2x0_flush_range;
		outer_cache.sync = l2x0_cache_sync;
		outer_cache.flush_all = l2x0_flush_all;
		outer_cache.inv_all = l2x0_inv_all;
		outer_cache.disable = l2x0_disable;
	}

	printk(KERN_INFO "%s cache controller enabled\n", type);
	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
			ways, cache_id, aux, l2x0_size);
}

#ifdef CONFIG_OF
static void __init l2x0_of_setup(const struct device_node *np,
				 u32 *aux_val, u32 *aux_mask)
{
	u32 data[2] = { 0, 0 };
	u32 tag = 0;
	u32 dirty = 0;
	u32 val = 0, mask = 0;

	of_property_read_u32(np, "arm,tag-latency", &tag);
	if (tag) {
		mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
		val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
	}

	of_property_read_u32_array(np, "arm,data-latency",
				   data, ARRAY_SIZE(data));
	if (data[0] && data[1]) {
		mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
			L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
		val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
		       ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
	}

	of_property_read_u32(np, "arm,dirty-latency", &dirty);
	if (dirty) {
		mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
		val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
	}

	*aux_val &= ~mask;
	*aux_val |= val;
	*aux_mask &= ~mask;
}

static void __init pl310_of_setup(const struct device_node *np,
				  u32 *aux_val, u32 *aux_mask)
{
	u32 data[3] = { 0, 0, 0 };
	u32 tag[3] = { 0, 0, 0 };
	u32 filter[2] = { 0, 0 };

	of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
	if (tag[0] && tag[1] && tag[2])
		writel_relaxed(
			((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
			((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
			((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
			l2x0_base + L2X0_TAG_LATENCY_CTRL);

	of_property_read_u32_array(np, "arm,data-latency",
				   data, ARRAY_SIZE(data));
	if (data[0] && data[1] && data[2])
		writel_relaxed(
			((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
			((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
			((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
			l2x0_base + L2X0_DATA_LATENCY_CTRL);

	of_property_read_u32_array(np, "arm,filter-ranges",
				   filter, ARRAY_SIZE(filter));
	if (filter[1]) {
		writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
			       l2x0_base + L2X0_ADDR_FILTER_END);
		writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
			       l2x0_base + L2X0_ADDR_FILTER_START);
	}
}

static void __init pl310_save(void)
{
	u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
		L2X0_CACHE_ID_RTL_MASK;

	l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
		L2X0_TAG_LATENCY_CTRL);
	l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
		L2X0_DATA_LATENCY_CTRL);
	l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
		L2X0_ADDR_FILTER_END);
	l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
		L2X0_ADDR_FILTER_START);

	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
		/*
		 * From r2p0, there is Prefetch offset/control register
		 */
		l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
			L2X0_PREFETCH_CTRL);
		/*
		 * From r3p0, there is Power control register
		 */
		if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
			l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
				L2X0_POWER_CTRL);
	}
}

static void l2x0_resume(void)
{
	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
		/* restore aux ctrl and enable l2 */
		l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));

		writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
			L2X0_AUX_CTRL);

		l2x0_inv_all();

		writel_relaxed(1, l2x0_base + L2X0_CTRL);
	}
}

static void pl310_resume(void)
{
	u32 l2x0_revision;

	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
		/* restore pl310 setup */
		writel_relaxed(l2x0_saved_regs.tag_latency,
			l2x0_base + L2X0_TAG_LATENCY_CTRL);
		writel_relaxed(l2x0_saved_regs.data_latency,
			l2x0_base + L2X0_DATA_LATENCY_CTRL);
		writel_relaxed(l2x0_saved_regs.filter_end,
			l2x0_base + L2X0_ADDR_FILTER_END);
		writel_relaxed(l2x0_saved_regs.filter_start,
			l2x0_base + L2X0_ADDR_FILTER_START);

		l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
			L2X0_CACHE_ID_RTL_MASK;

		if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
			writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
				l2x0_base + L2X0_PREFETCH_CTRL);
			if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
				writel_relaxed(l2x0_saved_regs.pwr_ctrl,
					l2x0_base + L2X0_POWER_CTRL);
		}
	}

	l2x0_resume();
}

static const struct l2x0_of_data pl310_data = {
	.setup = pl310_of_setup,
	.save  = pl310_save,
	.outer_cache = {
		.resume      = pl310_resume,
		.inv_range   = l2x0_inv_range,
		.clean_range = l2x0_clean_range,
		.flush_range = l2x0_flush_range,
		.sync        = l2x0_cache_sync,
		.flush_all   = l2x0_flush_all,
		.inv_all     = l2x0_inv_all,
		.disable     = l2x0_disable,
		.set_debug   = pl310_set_debug,
	},
};

static const struct l2x0_of_data l2x0_data = {
	.setup = l2x0_of_setup,
	.save  = NULL,
	.outer_cache = {
		.resume      = l2x0_resume,
		.inv_range   = l2x0_inv_range,
		.clean_range = l2x0_clean_range,
		.flush_range = l2x0_flush_range,
		.sync        = l2x0_cache_sync,
		.flush_all   = l2x0_flush_all,
		.inv_all     = l2x0_inv_all,
		.disable     = l2x0_disable,
	},
};

static const struct of_device_id l2x0_ids[] __initconst = {
	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
	{}
};

int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
{
	struct device_node *np;
	const struct l2x0_of_data *data;
	struct resource res;

	np = of_find_matching_node(NULL, l2x0_ids);
	if (!np)
		return -ENODEV;

	if (of_address_to_resource(np, 0, &res))
		return -ENODEV;

	l2x0_base = ioremap(res.start, resource_size(&res));
	if (!l2x0_base)
		return -ENOMEM;

	l2x0_saved_regs.phy_base = res.start;

	data = of_match_node(l2x0_ids, np)->data;

	/* L2 configuration can only be changed if the cache is disabled */
	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
		if (data->setup)
			data->setup(np, &aux_val, &aux_mask);
	}

	if (data->save)
		data->save();

	of_init = true;
	l2x0_init(l2x0_base, aux_val, aux_mask);

	memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));

	return 0;
}
#endif
Commit	Line	Data
382266ad CM	1	/*
	2	* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
	3	*
	4	* Copyright (C) 2007 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
8c369264	19	#include <linux/err.h>
382266ad	20	#include <linux/init.h>
07620976	21	#include <linux/spinlock.h>
fced80c7	22	#include <linux/io.h>
8c369264 RH	23	#include <linux/of.h>
8c369264 RH	24	#include <linux/of_address.h>
382266ad CM	25
382266ad CM	26	#include <asm/cacheflush.h>
382266ad CM	27	#include <asm/hardware/cache-l2x0.h>
	28
	29	#define CACHE_LINE_SIZE 32
	30
	31	static void __iomem *l2x0_base;
bd31b859	32	static DEFINE_RAW_SPINLOCK(l2x0_lock);
3e175ca4 RK	33	static u32 l2x0_way_mask; /* Bitmask of active ways */
3e175ca4 RK	34	static u32 l2x0_size;
f154fe9b	35	static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
382266ad	36
91c2ebb9 BS	37	struct l2x0_regs l2x0_saved_regs;
	38
	39	struct l2x0_of_data {
3e175ca4	40	void (setup)(const struct device_node , u32 , u32 );
91c2ebb9	41	void (*save)(void);
6248d060	42	struct outer_cache_fns outer_cache;
91c2ebb9 BS	43	};
91c2ebb9 BS	44
6248d060 GC	45	static bool of_init = false;
6248d060 GC	46
9a6655e4	47	static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
382266ad	48	{
9a6655e4	49	/* wait for cache operation by line or way to complete */
6775a558	50	while (readl_relaxed(reg) & mask)
1caf3092	51	cpu_relax();
382266ad CM	52	}
382266ad CM	53
9a6655e4 CM	54	#ifdef CONFIG_CACHE_PL310
	55	static inline void cache_wait(void __iomem *reg, unsigned long mask)
	56	{
	57	/* cache operations by line are atomic on PL310 */
	58	}
	59	#else
	60	#define cache_wait cache_wait_way
	61	#endif
	62
382266ad CM	63	static inline void cache_sync(void)
382266ad CM	64	{
3d107434	65	void __iomem *base = l2x0_base;
885028e4	66
f154fe9b	67	writel_relaxed(0, base + sync_reg_offset);
3d107434	68	cache_wait(base + L2X0_CACHE_SYNC, 1);
382266ad CM	69	}
382266ad CM	70
424d6b14 SS	71	static inline void l2x0_clean_line(unsigned long addr)
	72	{
	73	void __iomem *base = l2x0_base;
	74	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
6775a558	75	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
424d6b14 SS	76	}
	77
	78	static inline void l2x0_inv_line(unsigned long addr)
	79	{
	80	void __iomem *base = l2x0_base;
	81	cache_wait(base + L2X0_INV_LINE_PA, 1);
6775a558	82	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
424d6b14 SS	83	}
424d6b14 SS	84
2839e06c	85	#if defined(CONFIG_PL310_ERRATA_588369) \|\| defined(CONFIG_PL310_ERRATA_727915)
ab4d5368 WD	86	static inline void debug_writel(unsigned long val)
	87	{
	88	if (outer_cache.set_debug)
	89	outer_cache.set_debug(val);
	90	}
9e65582a	91
ab4d5368	92	static void pl310_set_debug(unsigned long val)
2839e06c SS	93	{
2839e06c SS	94	writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
9e65582a	95	}
2839e06c SS	96	#else
	97	/* Optimised out for non-errata case */
	98	static inline void debug_writel(unsigned long val)
	99	{
	100	}
	101
ab4d5368	102	#define pl310_set_debug NULL
2839e06c	103	#endif
9e65582a	104
2839e06c	105	#ifdef CONFIG_PL310_ERRATA_588369
9e65582a SS	106	static inline void l2x0_flush_line(unsigned long addr)
	107	{
	108	void __iomem *base = l2x0_base;
	109
	110	/* Clean by PA followed by Invalidate by PA */
	111	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
6775a558	112	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
9e65582a	113	cache_wait(base + L2X0_INV_LINE_PA, 1);
6775a558	114	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
9e65582a SS	115	}
	116	#else
	117
424d6b14 SS	118	static inline void l2x0_flush_line(unsigned long addr)
	119	{
	120	void __iomem *base = l2x0_base;
	121	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
6775a558	122	writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
424d6b14	123	}
9e65582a	124	#endif
424d6b14	125
23107c54 CM	126	static void l2x0_cache_sync(void)
	127	{
	128	unsigned long flags;
	129
bd31b859	130	raw_spin_lock_irqsave(&l2x0_lock, flags);
23107c54	131	cache_sync();
bd31b859	132	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
23107c54 CM	133	}
23107c54 CM	134
38a8914f	135	static void __l2x0_flush_all(void)
2fd86589	136	{
2839e06c	137	debug_writel(0x03);
2fd86589 TG	138	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
	139	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
	140	cache_sync();
2839e06c	141	debug_writel(0x00);
38a8914f WD	142	}
	143
	144	static void l2x0_flush_all(void)
	145	{
	146	unsigned long flags;
	147
	148	/* clean all ways */
bd31b859	149	raw_spin_lock_irqsave(&l2x0_lock, flags);
38a8914f	150	__l2x0_flush_all();
bd31b859	151	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
2fd86589 TG	152	}
2fd86589 TG	153
444457c1 SS	154	static void l2x0_clean_all(void)
	155	{
	156	unsigned long flags;
	157
	158	/* clean all ways */
bd31b859	159	raw_spin_lock_irqsave(&l2x0_lock, flags);
444457c1 SS	160	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
	161	cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
	162	cache_sync();
bd31b859	163	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
444457c1 SS	164	}
444457c1 SS	165
2fd86589	166	static void l2x0_inv_all(void)
382266ad	167	{
0eb948dd RK	168	unsigned long flags;
0eb948dd RK	169
382266ad	170	/* invalidate all ways */
bd31b859	171	raw_spin_lock_irqsave(&l2x0_lock, flags);
2fd86589 TG	172	/* Invalidating when L2 is enabled is a nono */
2fd86589 TG	173	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
6775a558	174	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
9a6655e4	175	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
382266ad	176	cache_sync();
bd31b859	177	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	178	}
	179
	180	static void l2x0_inv_range(unsigned long start, unsigned long end)
	181	{
3d107434	182	void __iomem *base = l2x0_base;
0eb948dd	183	unsigned long flags;
382266ad	184
bd31b859	185	raw_spin_lock_irqsave(&l2x0_lock, flags);
4f6627ac RS	186	if (start & (CACHE_LINE_SIZE - 1)) {
4f6627ac RS	187	start &= ~(CACHE_LINE_SIZE - 1);
9e65582a	188	debug_writel(0x03);
424d6b14	189	l2x0_flush_line(start);
9e65582a	190	debug_writel(0x00);
4f6627ac RS	191	start += CACHE_LINE_SIZE;
	192	}
	193
	194	if (end & (CACHE_LINE_SIZE - 1)) {
	195	end &= ~(CACHE_LINE_SIZE - 1);
9e65582a	196	debug_writel(0x03);
424d6b14	197	l2x0_flush_line(end);
9e65582a	198	debug_writel(0x00);
4f6627ac RS	199	}
4f6627ac RS	200
0eb948dd RK	201	while (start < end) {
	202	unsigned long blk_end = start + min(end - start, 4096UL);
	203
	204	while (start < blk_end) {
424d6b14	205	l2x0_inv_line(start);
0eb948dd RK	206	start += CACHE_LINE_SIZE;
	207	}
	208
	209	if (blk_end < end) {
bd31b859 TG	210	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
bd31b859 TG	211	raw_spin_lock_irqsave(&l2x0_lock, flags);
0eb948dd RK	212	}
0eb948dd RK	213	}
3d107434	214	cache_wait(base + L2X0_INV_LINE_PA, 1);
382266ad	215	cache_sync();
bd31b859	216	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	217	}
	218
	219	static void l2x0_clean_range(unsigned long start, unsigned long end)
	220	{
3d107434	221	void __iomem *base = l2x0_base;
0eb948dd	222	unsigned long flags;
382266ad	223
444457c1 SS	224	if ((end - start) >= l2x0_size) {
	225	l2x0_clean_all();
	226	return;
	227	}
	228
bd31b859	229	raw_spin_lock_irqsave(&l2x0_lock, flags);
382266ad	230	start &= ~(CACHE_LINE_SIZE - 1);
0eb948dd RK	231	while (start < end) {
	232	unsigned long blk_end = start + min(end - start, 4096UL);
	233
	234	while (start < blk_end) {
424d6b14	235	l2x0_clean_line(start);
0eb948dd RK	236	start += CACHE_LINE_SIZE;
	237	}
	238
	239	if (blk_end < end) {
bd31b859 TG	240	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
bd31b859 TG	241	raw_spin_lock_irqsave(&l2x0_lock, flags);
0eb948dd RK	242	}
0eb948dd RK	243	}
3d107434	244	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
382266ad	245	cache_sync();
bd31b859	246	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	247	}
	248
	249	static void l2x0_flush_range(unsigned long start, unsigned long end)
	250	{
3d107434	251	void __iomem *base = l2x0_base;
0eb948dd	252	unsigned long flags;
382266ad	253
444457c1 SS	254	if ((end - start) >= l2x0_size) {
	255	l2x0_flush_all();
	256	return;
	257	}
	258
bd31b859	259	raw_spin_lock_irqsave(&l2x0_lock, flags);
382266ad	260	start &= ~(CACHE_LINE_SIZE - 1);
0eb948dd RK	261	while (start < end) {
	262	unsigned long blk_end = start + min(end - start, 4096UL);
	263
9e65582a	264	debug_writel(0x03);
0eb948dd	265	while (start < blk_end) {
424d6b14	266	l2x0_flush_line(start);
0eb948dd RK	267	start += CACHE_LINE_SIZE;
0eb948dd RK	268	}
9e65582a	269	debug_writel(0x00);
0eb948dd RK	270
0eb948dd RK	271	if (blk_end < end) {
bd31b859 TG	272	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
bd31b859 TG	273	raw_spin_lock_irqsave(&l2x0_lock, flags);
0eb948dd RK	274	}
0eb948dd RK	275	}
3d107434	276	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
382266ad	277	cache_sync();
bd31b859	278	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	279	}
382266ad CM	280
2fd86589 TG	281	static void l2x0_disable(void)
	282	{
	283	unsigned long flags;
	284
bd31b859	285	raw_spin_lock_irqsave(&l2x0_lock, flags);
38a8914f WD	286	__l2x0_flush_all();
	287	writel_relaxed(0, l2x0_base + L2X0_CTRL);
	288	dsb();
bd31b859	289	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
2fd86589 TG	290	}
2fd86589 TG	291
3e175ca4	292	static void l2x0_unlock(u32 cache_id)
bac7e6ec LW	293	{
	294	int lockregs;
	295	int i;
	296
	297	if (cache_id == L2X0_CACHE_ID_PART_L310)
	298	lockregs = 8;
	299	else
	300	/* L210 and unknown types */
	301	lockregs = 1;
	302
	303	for (i = 0; i < lockregs; i++) {
	304	writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
	305	i * L2X0_LOCKDOWN_STRIDE);
	306	writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
	307	i * L2X0_LOCKDOWN_STRIDE);
	308	}
	309	}
	310
3e175ca4	311	void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
382266ad	312	{
3e175ca4 RK	313	u32 aux;
	314	u32 cache_id;
	315	u32 way_size = 0;
64039be8 JM	316	int ways;
64039be8 JM	317	const char *type;
382266ad CM	318
	319	l2x0_base = base;
	320
6775a558 CM	321	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
6775a558 CM	322	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
64039be8	323
4082cfa7 SH	324	aux &= aux_mask;
	325	aux \|= aux_val;
	326
64039be8 JM	327	/* Determine the number of ways */
	328	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	329	case L2X0_CACHE_ID_PART_L310:
	330	if (aux & (1 << 16))
	331	ways = 16;
	332	else
	333	ways = 8;
	334	type = "L310";
f154fe9b WD	335	#ifdef CONFIG_PL310_ERRATA_753970
	336	/* Unmapped register. */
	337	sync_reg_offset = L2X0_DUMMY_REG;
	338	#endif
ab4d5368	339	outer_cache.set_debug = pl310_set_debug;
64039be8 JM	340	break;
	341	case L2X0_CACHE_ID_PART_L210:
	342	ways = (aux >> 13) & 0xf;
	343	type = "L210";
	344	break;
	345	default:
	346	/* Assume unknown chips have 8 ways */
	347	ways = 8;
	348	type = "L2x0 series";
	349	break;
	350	}
	351
	352	l2x0_way_mask = (1 << ways) - 1;
	353
5ba70372 SS	354	/*
	355	* L2 cache Size = Way size * Number of ways
	356	*/
	357	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
	358	way_size = 1 << (way_size + 3);
	359	l2x0_size = ways * way_size * SZ_1K;
	360
48371cd3 SK	361	/*
	362	* Check if l2x0 controller is already enabled.
	363	* If you are booting from non-secure mode
	364	* accessing the below registers will fault.
	365	*/
6775a558	366	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
bac7e6ec LW	367	/* Make sure that I&D is not locked down when starting */
bac7e6ec LW	368	l2x0_unlock(cache_id);
382266ad	369
48371cd3	370	/* l2x0 controller is disabled */
6775a558	371	writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
382266ad	372
48371cd3 SK	373	l2x0_inv_all();
	374
	375	/* enable L2X0 */
6775a558	376	writel_relaxed(1, l2x0_base + L2X0_CTRL);
48371cd3	377	}
382266ad	378
9d4876f0 YM	379	/* Re-read it in case some bits are reserved. */
	380	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
	381
	382	/* Save the value for resuming. */
	383	l2x0_saved_regs.aux_ctrl = aux;
	384
6248d060 GC	385	if (!of_init) {
	386	outer_cache.inv_range = l2x0_inv_range;
	387	outer_cache.clean_range = l2x0_clean_range;
	388	outer_cache.flush_range = l2x0_flush_range;
	389	outer_cache.sync = l2x0_cache_sync;
	390	outer_cache.flush_all = l2x0_flush_all;
	391	outer_cache.inv_all = l2x0_inv_all;
	392	outer_cache.disable = l2x0_disable;
	393	}
382266ad	394
64039be8	395	printk(KERN_INFO "%s cache controller enabled\n", type);
5ba70372 SS	396	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
5ba70372 SS	397	ways, cache_id, aux, l2x0_size);
382266ad	398	}
8c369264 RH	399
	400	#ifdef CONFIG_OF
	401	static void __init l2x0_of_setup(const struct device_node *np,
3e175ca4	402	u32 aux_val, u32 aux_mask)
8c369264 RH	403	{
	404	u32 data[2] = { 0, 0 };
	405	u32 tag = 0;
	406	u32 dirty = 0;
	407	u32 val = 0, mask = 0;
	408
	409	of_property_read_u32(np, "arm,tag-latency", &tag);
	410	if (tag) {
	411	mask \|= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
	412	val \|= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
	413	}
	414
	415	of_property_read_u32_array(np, "arm,data-latency",
	416	data, ARRAY_SIZE(data));
	417	if (data[0] && data[1]) {
	418	mask \|= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK \|
	419	L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
	420	val \|= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) \|
	421	((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
	422	}
	423
	424	of_property_read_u32(np, "arm,dirty-latency", &dirty);
	425	if (dirty) {
	426	mask \|= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
	427	val \|= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
	428	}
	429
	430	*aux_val &= ~mask;
	431	*aux_val \|= val;
	432	*aux_mask &= ~mask;
	433	}
	434
	435	static void __init pl310_of_setup(const struct device_node *np,
3e175ca4	436	u32 aux_val, u32 aux_mask)
8c369264 RH	437	{
	438	u32 data[3] = { 0, 0, 0 };
	439	u32 tag[3] = { 0, 0, 0 };
	440	u32 filter[2] = { 0, 0 };
	441
	442	of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
	443	if (tag[0] && tag[1] && tag[2])
	444	writel_relaxed(
	445	((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) \|
	446	((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) \|
	447	((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
	448	l2x0_base + L2X0_TAG_LATENCY_CTRL);
	449
	450	of_property_read_u32_array(np, "arm,data-latency",
	451	data, ARRAY_SIZE(data));
	452	if (data[0] && data[1] && data[2])
	453	writel_relaxed(
	454	((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) \|
	455	((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) \|
	456	((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
	457	l2x0_base + L2X0_DATA_LATENCY_CTRL);
	458
	459	of_property_read_u32_array(np, "arm,filter-ranges",
	460	filter, ARRAY_SIZE(filter));
74d41f39	461	if (filter[1]) {
8c369264 RH	462	writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
	463	l2x0_base + L2X0_ADDR_FILTER_END);
	464	writel_relaxed((filter[0] & ~(SZ_1M - 1)) \| L2X0_ADDR_FILTER_EN,
	465	l2x0_base + L2X0_ADDR_FILTER_START);
	466	}
	467	}
	468
91c2ebb9 BS	469	static void __init pl310_save(void)
	470	{
	471	u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
	472	L2X0_CACHE_ID_RTL_MASK;
	473
	474	l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
	475	L2X0_TAG_LATENCY_CTRL);
	476	l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
	477	L2X0_DATA_LATENCY_CTRL);
	478	l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
	479	L2X0_ADDR_FILTER_END);
	480	l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
	481	L2X0_ADDR_FILTER_START);
	482
	483	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
	484	/*
	485	* From r2p0, there is Prefetch offset/control register
	486	*/
	487	l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
	488	L2X0_PREFETCH_CTRL);
	489	/*
	490	* From r3p0, there is Power control register
	491	*/
	492	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
	493	l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
	494	L2X0_POWER_CTRL);
	495	}
	496	}
	497
	498	static void l2x0_resume(void)
	499	{
	500	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
	501	/* restore aux ctrl and enable l2 */
	502	l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
	503
	504	writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
	505	L2X0_AUX_CTRL);
	506
	507	l2x0_inv_all();
	508
	509	writel_relaxed(1, l2x0_base + L2X0_CTRL);
	510	}
	511	}
	512
	513	static void pl310_resume(void)
	514	{
	515	u32 l2x0_revision;
	516
	517	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
	518	/* restore pl310 setup */
	519	writel_relaxed(l2x0_saved_regs.tag_latency,
	520	l2x0_base + L2X0_TAG_LATENCY_CTRL);
	521	writel_relaxed(l2x0_saved_regs.data_latency,
	522	l2x0_base + L2X0_DATA_LATENCY_CTRL);
	523	writel_relaxed(l2x0_saved_regs.filter_end,
	524	l2x0_base + L2X0_ADDR_FILTER_END);
	525	writel_relaxed(l2x0_saved_regs.filter_start,
	526	l2x0_base + L2X0_ADDR_FILTER_START);
	527
	528	l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
	529	L2X0_CACHE_ID_RTL_MASK;
	530
	531	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
	532	writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
533	l2x0_base + L2X0_PREFETCH_CTRL);
534	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
535	writel_relaxed(l2x0_saved_regs.pwr_ctrl,
536	l2x0_base + L2X0_POWER_CTRL);
537	}
538	}
539
540	l2x0_resume();
541	}
542
543	static const struct l2x0_of_data pl310_data = {
6248d060 GC	544	.setup = pl310_of_setup,
	545	.save = pl310_save,
	546	.outer_cache = {
	547	.resume = pl310_resume,
	548	.inv_range = l2x0_inv_range,
	549	.clean_range = l2x0_clean_range,
	550	.flush_range = l2x0_flush_range,
	551	.sync = l2x0_cache_sync,
	552	.flush_all = l2x0_flush_all,
	553	.inv_all = l2x0_inv_all,
	554	.disable = l2x0_disable,
	555	.set_debug = pl310_set_debug,
	556	},
91c2ebb9 BS	557	};
	558
	559	static const struct l2x0_of_data l2x0_data = {
6248d060 GC	560	.setup = l2x0_of_setup,
	561	.save = NULL,
	562	.outer_cache = {
	563	.resume = l2x0_resume,
	564	.inv_range = l2x0_inv_range,
	565	.clean_range = l2x0_clean_range,
	566	.flush_range = l2x0_flush_range,
	567	.sync = l2x0_cache_sync,
	568	.flush_all = l2x0_flush_all,
	569	.inv_all = l2x0_inv_all,
	570	.disable = l2x0_disable,
	571	},
91c2ebb9 BS	572	};
91c2ebb9 BS	573
8c369264	574	static const struct of_device_id l2x0_ids[] __initconst = {
91c2ebb9 BS	575	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
	576	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
	577	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
8c369264 RH	578	{}
	579	};
	580
3e175ca4	581	int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
8c369264 RH	582	{
8c369264 RH	583	struct device_node *np;
e5b5d020	584	const struct l2x0_of_data *data;
91c2ebb9	585	struct resource res;
8c369264 RH	586
	587	np = of_find_matching_node(NULL, l2x0_ids);
	588	if (!np)
	589	return -ENODEV;
91c2ebb9 BS	590
	591	if (of_address_to_resource(np, 0, &res))
	592	return -ENODEV;
	593
	594	l2x0_base = ioremap(res.start, resource_size(&res));
8c369264 RH	595	if (!l2x0_base)
	596	return -ENOMEM;
	597
91c2ebb9 BS	598	l2x0_saved_regs.phy_base = res.start;
	599
	600	data = of_match_node(l2x0_ids, np)->data;
	601
8c369264 RH	602	/* L2 configuration can only be changed if the cache is disabled */
8c369264 RH	603	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
91c2ebb9 BS	604	if (data->setup)
91c2ebb9 BS	605	data->setup(np, &aux_val, &aux_mask);
8c369264	606	}
91c2ebb9 BS	607
	608	if (data->save)
	609	data->save();
	610
6248d060	611	of_init = true;
8c369264	612	l2x0_init(l2x0_base, aux_val, aux_mask);
91c2ebb9	613
6248d060 GC	614	memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
6248d060 GC	615
8c369264 RH	616	return 0;
	617	}
	618	#endif