[mirror_ubuntu-artful-kernel.git] / arch / arm / mm / cache-l2x0.c

/*
 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
 *
 * Copyright (C) 2007 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>

#define CACHE_LINE_SIZE		32

static void __iomem *l2x0_base;
static DEFINE_SPINLOCK(l2x0_lock);
static uint32_t l2x0_way_mask;	/* Bitmask of active ways */

static inline void cache_wait(void __iomem *reg, unsigned long mask)
{
	/* wait for the operation to complete */
	while (readl(reg) & mask)
		;
}

static inline void cache_sync(void)
{
	void __iomem *base = l2x0_base;
	writel(0, base + L2X0_CACHE_SYNC);
	cache_wait(base + L2X0_CACHE_SYNC, 1);
}

static inline void l2x0_clean_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel(addr, base + L2X0_CLEAN_LINE_PA);
}

static inline void l2x0_inv_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel(addr, base + L2X0_INV_LINE_PA);
}

#ifdef CONFIG_PL310_ERRATA_588369
static void debug_writel(unsigned long val)
{
	extern void omap_smc1(u32 fn, u32 arg);

	/*
	 * Texas Instrument secure monitor api to modify the
	 * PL310 Debug Control Register.
	 */
	omap_smc1(0x100, val);
}

static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;

	/* Clean by PA followed by Invalidate by PA */
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel(addr, base + L2X0_CLEAN_LINE_PA);
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel(addr, base + L2X0_INV_LINE_PA);
}
#else

/* Optimised out for non-errata case */
static inline void debug_writel(unsigned long val)
{
}

static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
}
#endif

static void l2x0_cache_sync(void)
{
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static inline void l2x0_inv_all(void)
{
	unsigned long flags;

	/* invalidate all ways */
	spin_lock_irqsave(&l2x0_lock, flags);
	writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
	cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_inv_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	if (start & (CACHE_LINE_SIZE - 1)) {
		start &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(start);
		debug_writel(0x00);
		start += CACHE_LINE_SIZE;
	}

	if (end & (CACHE_LINE_SIZE - 1)) {
		end &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(end);
		debug_writel(0x00);
	}

	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_inv_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			spin_unlock_irqrestore(&l2x0_lock, flags);
			spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_clean_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_clean_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			spin_unlock_irqrestore(&l2x0_lock, flags);
			spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_flush_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		debug_writel(0x03);
		while (start < blk_end) {
			l2x0_flush_line(start);
			start += CACHE_LINE_SIZE;
		}
		debug_writel(0x00);

		if (blk_end < end) {
			spin_unlock_irqrestore(&l2x0_lock, flags);
			spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
	__u32 aux;
	__u32 cache_id;
	int ways;
	const char *type;

	l2x0_base = base;

	cache_id = readl(l2x0_base + L2X0_CACHE_ID);
	aux = readl(l2x0_base + L2X0_AUX_CTRL);

	aux &= aux_mask;
	aux |= aux_val;

	/* Determine the number of ways */
	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	case L2X0_CACHE_ID_PART_L310:
		if (aux & (1 << 16))
			ways = 16;
		else
			ways = 8;
		type = "L310";
		break;
	case L2X0_CACHE_ID_PART_L210:
		ways = (aux >> 13) & 0xf;
		type = "L210";
		break;
	default:
		/* Assume unknown chips have 8 ways */
		ways = 8;
		type = "L2x0 series";
		break;
	}

	l2x0_way_mask = (1 << ways) - 1;

	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {

		/* l2x0 controller is disabled */
		writel(aux, l2x0_base + L2X0_AUX_CTRL);

		l2x0_inv_all();

		/* enable L2X0 */
		writel(1, l2x0_base + L2X0_CTRL);
	}

	outer_cache.inv_range = l2x0_inv_range;
	outer_cache.clean_range = l2x0_clean_range;
	outer_cache.flush_range = l2x0_flush_range;
	outer_cache.sync = l2x0_cache_sync;

	printk(KERN_INFO "%s cache controller enabled\n", type);
	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
			 ways, cache_id, aux);
}
Commit	Line	Data
382266ad CM	1	/*
	2	* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
	3	*
	4	* Copyright (C) 2007 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19	#include <linux/init.h>
07620976	20	#include <linux/spinlock.h>
fced80c7	21	#include <linux/io.h>
382266ad CM	22
382266ad CM	23	#include <asm/cacheflush.h>
382266ad CM	24	#include <asm/hardware/cache-l2x0.h>
	25
	26	#define CACHE_LINE_SIZE 32
	27
	28	static void __iomem *l2x0_base;
07620976	29	static DEFINE_SPINLOCK(l2x0_lock);
64039be8	30	static uint32_t l2x0_way_mask; /* Bitmask of active ways */
382266ad	31
3d107434	32	static inline void cache_wait(void __iomem *reg, unsigned long mask)
382266ad	33	{
382266ad	34	/* wait for the operation to complete */
3d107434	35	while (readl(reg) & mask)
382266ad CM	36	;
	37	}
	38
	39	static inline void cache_sync(void)
	40	{
3d107434 RK	41	void __iomem *base = l2x0_base;
	42	writel(0, base + L2X0_CACHE_SYNC);
	43	cache_wait(base + L2X0_CACHE_SYNC, 1);
382266ad CM	44	}
382266ad CM	45
424d6b14 SS	46	static inline void l2x0_clean_line(unsigned long addr)
	47	{
	48	void __iomem *base = l2x0_base;
	49	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	50	writel(addr, base + L2X0_CLEAN_LINE_PA);
	51	}
	52
	53	static inline void l2x0_inv_line(unsigned long addr)
	54	{
	55	void __iomem *base = l2x0_base;
	56	cache_wait(base + L2X0_INV_LINE_PA, 1);
	57	writel(addr, base + L2X0_INV_LINE_PA);
	58	}
	59
9e65582a SS	60	#ifdef CONFIG_PL310_ERRATA_588369
	61	static void debug_writel(unsigned long val)
	62	{
	63	extern void omap_smc1(u32 fn, u32 arg);
	64
	65	/*
	66	* Texas Instrument secure monitor api to modify the
	67	* PL310 Debug Control Register.
	68	*/
	69	omap_smc1(0x100, val);
	70	}
	71
	72	static inline void l2x0_flush_line(unsigned long addr)
	73	{
	74	void __iomem *base = l2x0_base;
	75
	76	/* Clean by PA followed by Invalidate by PA */
	77	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	78	writel(addr, base + L2X0_CLEAN_LINE_PA);
	79	cache_wait(base + L2X0_INV_LINE_PA, 1);
	80	writel(addr, base + L2X0_INV_LINE_PA);
	81	}
	82	#else
	83
	84	/* Optimised out for non-errata case */
	85	static inline void debug_writel(unsigned long val)
	86	{
	87	}
	88
424d6b14 SS	89	static inline void l2x0_flush_line(unsigned long addr)
	90	{
	91	void __iomem *base = l2x0_base;
	92	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	93	writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
	94	}
9e65582a	95	#endif
424d6b14	96
23107c54 CM	97	static void l2x0_cache_sync(void)
	98	{
	99	unsigned long flags;
	100
	101	spin_lock_irqsave(&l2x0_lock, flags);
	102	cache_sync();
	103	spin_unlock_irqrestore(&l2x0_lock, flags);
	104	}
	105
382266ad CM	106	static inline void l2x0_inv_all(void)
382266ad CM	107	{
0eb948dd RK	108	unsigned long flags;
0eb948dd RK	109
382266ad	110	/* invalidate all ways */
0eb948dd	111	spin_lock_irqsave(&l2x0_lock, flags);
64039be8 JM	112	writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
64039be8 JM	113	cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
382266ad	114	cache_sync();
0eb948dd	115	spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	116	}
	117
	118	static void l2x0_inv_range(unsigned long start, unsigned long end)
	119	{
3d107434	120	void __iomem *base = l2x0_base;
0eb948dd	121	unsigned long flags;
382266ad	122
0eb948dd	123	spin_lock_irqsave(&l2x0_lock, flags);
4f6627ac RS	124	if (start & (CACHE_LINE_SIZE - 1)) {
4f6627ac RS	125	start &= ~(CACHE_LINE_SIZE - 1);
9e65582a	126	debug_writel(0x03);
424d6b14	127	l2x0_flush_line(start);
9e65582a	128	debug_writel(0x00);
4f6627ac RS	129	start += CACHE_LINE_SIZE;
	130	}
	131
	132	if (end & (CACHE_LINE_SIZE - 1)) {
	133	end &= ~(CACHE_LINE_SIZE - 1);
9e65582a	134	debug_writel(0x03);
424d6b14	135	l2x0_flush_line(end);
9e65582a	136	debug_writel(0x00);
4f6627ac RS	137	}
4f6627ac RS	138
0eb948dd RK	139	while (start < end) {
	140	unsigned long blk_end = start + min(end - start, 4096UL);
	141
	142	while (start < blk_end) {
424d6b14	143	l2x0_inv_line(start);
0eb948dd RK	144	start += CACHE_LINE_SIZE;
	145	}
	146
	147	if (blk_end < end) {
	148	spin_unlock_irqrestore(&l2x0_lock, flags);
	149	spin_lock_irqsave(&l2x0_lock, flags);
	150	}
	151	}
3d107434	152	cache_wait(base + L2X0_INV_LINE_PA, 1);
382266ad	153	cache_sync();
0eb948dd	154	spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	155	}
	156
	157	static void l2x0_clean_range(unsigned long start, unsigned long end)
	158	{
3d107434	159	void __iomem *base = l2x0_base;
0eb948dd	160	unsigned long flags;
382266ad	161
0eb948dd	162	spin_lock_irqsave(&l2x0_lock, flags);
382266ad	163	start &= ~(CACHE_LINE_SIZE - 1);
0eb948dd RK	164	while (start < end) {
	165	unsigned long blk_end = start + min(end - start, 4096UL);
	166
	167	while (start < blk_end) {
424d6b14	168	l2x0_clean_line(start);
0eb948dd RK	169	start += CACHE_LINE_SIZE;
	170	}
	171
	172	if (blk_end < end) {
	173	spin_unlock_irqrestore(&l2x0_lock, flags);
	174	spin_lock_irqsave(&l2x0_lock, flags);
	175	}
	176	}
3d107434	177	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
382266ad	178	cache_sync();
0eb948dd	179	spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	180	}
	181
	182	static void l2x0_flush_range(unsigned long start, unsigned long end)
	183	{
3d107434	184	void __iomem *base = l2x0_base;
0eb948dd	185	unsigned long flags;
382266ad	186
0eb948dd	187	spin_lock_irqsave(&l2x0_lock, flags);
382266ad	188	start &= ~(CACHE_LINE_SIZE - 1);
0eb948dd RK	189	while (start < end) {
	190	unsigned long blk_end = start + min(end - start, 4096UL);
	191
9e65582a	192	debug_writel(0x03);
0eb948dd	193	while (start < blk_end) {
424d6b14	194	l2x0_flush_line(start);
0eb948dd RK	195	start += CACHE_LINE_SIZE;
0eb948dd RK	196	}
9e65582a	197	debug_writel(0x00);
0eb948dd RK	198
	199	if (blk_end < end) {
	200	spin_unlock_irqrestore(&l2x0_lock, flags);
	201	spin_lock_irqsave(&l2x0_lock, flags);
	202	}
	203	}
3d107434	204	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
382266ad	205	cache_sync();
0eb948dd	206	spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	207	}
	208
	209	void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
	210	{
	211	__u32 aux;
64039be8 JM	212	__u32 cache_id;
	213	int ways;
	214	const char *type;
382266ad CM	215
	216	l2x0_base = base;
	217
64039be8 JM	218	cache_id = readl(l2x0_base + L2X0_CACHE_ID);
	219	aux = readl(l2x0_base + L2X0_AUX_CTRL);
	220
4082cfa7 SH	221	aux &= aux_mask;
	222	aux \|= aux_val;
	223
64039be8 JM	224	/* Determine the number of ways */
	225	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	226	case L2X0_CACHE_ID_PART_L310:
	227	if (aux & (1 << 16))
	228	ways = 16;
	229	else
	230	ways = 8;
	231	type = "L310";
	232	break;
	233	case L2X0_CACHE_ID_PART_L210:
	234	ways = (aux >> 13) & 0xf;
	235	type = "L210";
	236	break;
	237	default:
	238	/* Assume unknown chips have 8 ways */
	239	ways = 8;
	240	type = "L2x0 series";
	241	break;
	242	}
	243
	244	l2x0_way_mask = (1 << ways) - 1;
	245
48371cd3 SK	246	/*
	247	* Check if l2x0 controller is already enabled.
	248	* If you are booting from non-secure mode
	249	* accessing the below registers will fault.
	250	*/
	251	if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
382266ad	252
48371cd3	253	/* l2x0 controller is disabled */
48371cd3	254	writel(aux, l2x0_base + L2X0_AUX_CTRL);
382266ad	255
48371cd3 SK	256	l2x0_inv_all();
	257
	258	/* enable L2X0 */
	259	writel(1, l2x0_base + L2X0_CTRL);
	260	}
382266ad CM	261
	262	outer_cache.inv_range = l2x0_inv_range;
	263	outer_cache.clean_range = l2x0_clean_range;
	264	outer_cache.flush_range = l2x0_flush_range;
23107c54	265	outer_cache.sync = l2x0_cache_sync;
382266ad	266
64039be8 JM	267	printk(KERN_INFO "%s cache controller enabled\n", type);
	268	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
	269	ways, cache_id, aux);
382266ad	270	}