[mirror_ubuntu-artful-kernel.git] / arch / arm / mm / cache-l2x0.c

/*
 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
 *
 * Copyright (C) 2007 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>

#define CACHE_LINE_SIZE		32

static void __iomem *l2x0_base;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static u32 l2x0_way_mask;	/* Bitmask of active ways */
static u32 l2x0_size;
static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;

struct l2x0_regs l2x0_saved_regs;

struct l2x0_of_data {
	void (*setup)(const struct device_node *, u32 *, u32 *);
	void (*save)(void);
	void (*resume)(void);
};

static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
{
	/* wait for cache operation by line or way to complete */
	while (readl_relaxed(reg) & mask)
		cpu_relax();
}

#ifdef CONFIG_CACHE_PL310
static inline void cache_wait(void __iomem *reg, unsigned long mask)
{
	/* cache operations by line are atomic on PL310 */
}
#else
#define cache_wait	cache_wait_way
#endif

static inline void cache_sync(void)
{
	void __iomem *base = l2x0_base;

	writel_relaxed(0, base + sync_reg_offset);
	cache_wait(base + L2X0_CACHE_SYNC, 1);
}

static inline void l2x0_clean_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
}

static inline void l2x0_inv_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}

#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)

#define debug_writel(val)	outer_cache.set_debug(val)

static void l2x0_set_debug(unsigned long val)
{
	writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
}
#else
/* Optimised out for non-errata case */
static inline void debug_writel(unsigned long val)
{
}

#define l2x0_set_debug	NULL
#endif

#ifdef CONFIG_PL310_ERRATA_588369
static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;

	/* Clean by PA followed by Invalidate by PA */
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}
#else

static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
}
#endif

static void l2x0_cache_sync(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void __l2x0_flush_all(void)
{
	debug_writel(0x03);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
	cache_sync();
	debug_writel(0x00);
}

static void l2x0_flush_all(void)
{
	unsigned long flags;

	/* clean all ways */
	raw_spin_lock_irqsave(&l2x0_lock, flags);
	__l2x0_flush_all();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_clean_all(void)
{
	unsigned long flags;

	/* clean all ways */
	raw_spin_lock_irqsave(&l2x0_lock, flags);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
	cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_inv_all(void)
{
	unsigned long flags;

	/* invalidate all ways */
	raw_spin_lock_irqsave(&l2x0_lock, flags);
	/* Invalidating when L2 is enabled is a nono */
	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_inv_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	if (start & (CACHE_LINE_SIZE - 1)) {
		start &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(start);
		debug_writel(0x00);
		start += CACHE_LINE_SIZE;
	}

	if (end & (CACHE_LINE_SIZE - 1)) {
		end &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(end);
		debug_writel(0x00);
	}

	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_inv_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			raw_spin_unlock_irqrestore(&l2x0_lock, flags);
			raw_spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_clean_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	if ((end - start) >= l2x0_size) {
		l2x0_clean_all();
		return;
	}

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_clean_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			raw_spin_unlock_irqrestore(&l2x0_lock, flags);
			raw_spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_flush_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	if ((end - start) >= l2x0_size) {
		l2x0_flush_all();
		return;
	}

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		debug_writel(0x03);
		while (start < blk_end) {
			l2x0_flush_line(start);
			start += CACHE_LINE_SIZE;
		}
		debug_writel(0x00);

		if (blk_end < end) {
			raw_spin_unlock_irqrestore(&l2x0_lock, flags);
			raw_spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	cache_sync();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_disable(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&l2x0_lock, flags);
	__l2x0_flush_all();
	writel_relaxed(0, l2x0_base + L2X0_CTRL);
	dsb();
	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_unlock(u32 cache_id)
{
	int lockregs;
	int i;

	if (cache_id == L2X0_CACHE_ID_PART_L310)
		lockregs = 8;
	else
		/* L210 and unknown types */
		lockregs = 1;

	for (i = 0; i < lockregs; i++) {
		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
			       i * L2X0_LOCKDOWN_STRIDE);
		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
			       i * L2X0_LOCKDOWN_STRIDE);
	}
}

void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
{
	u32 aux;
	u32 cache_id;
	u32 way_size = 0;
	int ways;
	const char *type;

	l2x0_base = base;

	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);

	aux &= aux_mask;
	aux |= aux_val;

	/* Determine the number of ways */
	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	case L2X0_CACHE_ID_PART_L310:
		if (aux & (1 << 16))
			ways = 16;
		else
			ways = 8;
		type = "L310";
#ifdef CONFIG_PL310_ERRATA_753970
		/* Unmapped register. */
		sync_reg_offset = L2X0_DUMMY_REG;
#endif
		break;
	case L2X0_CACHE_ID_PART_L210:
		ways = (aux >> 13) & 0xf;
		type = "L210";
		break;
	default:
		/* Assume unknown chips have 8 ways */
		ways = 8;
		type = "L2x0 series";
		break;
	}

	l2x0_way_mask = (1 << ways) - 1;

	/*
	 * L2 cache Size =  Way size * Number of ways
	 */
	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
	way_size = 1 << (way_size + 3);
	l2x0_size = ways * way_size * SZ_1K;

	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
		/* Make sure that I&D is not locked down when starting */
		l2x0_unlock(cache_id);

		/* l2x0 controller is disabled */
		writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);

		l2x0_saved_regs.aux_ctrl = aux;

		l2x0_inv_all();

		/* enable L2X0 */
		writel_relaxed(1, l2x0_base + L2X0_CTRL);
	}

	outer_cache.inv_range = l2x0_inv_range;
	outer_cache.clean_range = l2x0_clean_range;
	outer_cache.flush_range = l2x0_flush_range;
	outer_cache.sync = l2x0_cache_sync;
	outer_cache.flush_all = l2x0_flush_all;
	outer_cache.inv_all = l2x0_inv_all;
	outer_cache.disable = l2x0_disable;
	outer_cache.set_debug = l2x0_set_debug;

	printk(KERN_INFO "%s cache controller enabled\n", type);
	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
			ways, cache_id, aux, l2x0_size);
}

#ifdef CONFIG_OF
static void __init l2x0_of_setup(const struct device_node *np,
				 u32 *aux_val, u32 *aux_mask)
{
	u32 data[2] = { 0, 0 };
	u32 tag = 0;
	u32 dirty = 0;
	u32 val = 0, mask = 0;

	of_property_read_u32(np, "arm,tag-latency", &tag);
	if (tag) {
		mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
		val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
	}

	of_property_read_u32_array(np, "arm,data-latency",
				   data, ARRAY_SIZE(data));
	if (data[0] && data[1]) {
		mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
			L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
		val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
		       ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
	}

	of_property_read_u32(np, "arm,dirty-latency", &dirty);
	if (dirty) {
		mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
		val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
	}

	*aux_val &= ~mask;
	*aux_val |= val;
	*aux_mask &= ~mask;
}

static void __init pl310_of_setup(const struct device_node *np,
				  u32 *aux_val, u32 *aux_mask)
{
	u32 data[3] = { 0, 0, 0 };
	u32 tag[3] = { 0, 0, 0 };
	u32 filter[2] = { 0, 0 };

	of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
	if (tag[0] && tag[1] && tag[2])
		writel_relaxed(
			((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
			((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
			((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
			l2x0_base + L2X0_TAG_LATENCY_CTRL);

	of_property_read_u32_array(np, "arm,data-latency",
				   data, ARRAY_SIZE(data));
	if (data[0] && data[1] && data[2])
		writel_relaxed(
			((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
			((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
			((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
			l2x0_base + L2X0_DATA_LATENCY_CTRL);

	of_property_read_u32_array(np, "arm,filter-ranges",
				   filter, ARRAY_SIZE(filter));
	if (filter[1]) {
		writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
			       l2x0_base + L2X0_ADDR_FILTER_END);
		writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
			       l2x0_base + L2X0_ADDR_FILTER_START);
	}
}

static void __init pl310_save(void)
{
	u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
		L2X0_CACHE_ID_RTL_MASK;

	l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
		L2X0_TAG_LATENCY_CTRL);
	l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
		L2X0_DATA_LATENCY_CTRL);
	l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
		L2X0_ADDR_FILTER_END);
	l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
		L2X0_ADDR_FILTER_START);

	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
		/*
		 * From r2p0, there is Prefetch offset/control register
		 */
		l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
			L2X0_PREFETCH_CTRL);
		/*
		 * From r3p0, there is Power control register
		 */
		if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
			l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
				L2X0_POWER_CTRL);
	}
}

static void l2x0_resume(void)
{
	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
		/* restore aux ctrl and enable l2 */
		l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));

		writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
			L2X0_AUX_CTRL);

		l2x0_inv_all();

		writel_relaxed(1, l2x0_base + L2X0_CTRL);
	}
}

static void pl310_resume(void)
{
	u32 l2x0_revision;

	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
		/* restore pl310 setup */
		writel_relaxed(l2x0_saved_regs.tag_latency,
			l2x0_base + L2X0_TAG_LATENCY_CTRL);
		writel_relaxed(l2x0_saved_regs.data_latency,
			l2x0_base + L2X0_DATA_LATENCY_CTRL);
		writel_relaxed(l2x0_saved_regs.filter_end,
			l2x0_base + L2X0_ADDR_FILTER_END);
		writel_relaxed(l2x0_saved_regs.filter_start,
			l2x0_base + L2X0_ADDR_FILTER_START);

		l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
			L2X0_CACHE_ID_RTL_MASK;

		if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
			writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
				l2x0_base + L2X0_PREFETCH_CTRL);
			if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
				writel_relaxed(l2x0_saved_regs.pwr_ctrl,
					l2x0_base + L2X0_POWER_CTRL);
		}
	}

	l2x0_resume();
}

static const struct l2x0_of_data pl310_data = {
	pl310_of_setup,
	pl310_save,
	pl310_resume,
};

static const struct l2x0_of_data l2x0_data = {
	l2x0_of_setup,
	NULL,
	l2x0_resume,
};

static const struct of_device_id l2x0_ids[] __initconst = {
	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
	{}
};

int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
{
	struct device_node *np;
	struct l2x0_of_data *data;
	struct resource res;

	np = of_find_matching_node(NULL, l2x0_ids);
	if (!np)
		return -ENODEV;

	if (of_address_to_resource(np, 0, &res))
		return -ENODEV;

	l2x0_base = ioremap(res.start, resource_size(&res));
	if (!l2x0_base)
		return -ENOMEM;

	l2x0_saved_regs.phy_base = res.start;

	data = of_match_node(l2x0_ids, np)->data;

	/* L2 configuration can only be changed if the cache is disabled */
	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
		if (data->setup)
			data->setup(np, &aux_val, &aux_mask);
	}

	if (data->save)
		data->save();

	l2x0_init(l2x0_base, aux_val, aux_mask);

	outer_cache.resume = data->resume;
	return 0;
}
#endif
Commit	Line	Data
382266ad CM	1	/*
	2	* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
	3	*
	4	* Copyright (C) 2007 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
8c369264	19	#include <linux/err.h>
382266ad	20	#include <linux/init.h>
07620976	21	#include <linux/spinlock.h>
fced80c7	22	#include <linux/io.h>
8c369264 RH	23	#include <linux/of.h>
8c369264 RH	24	#include <linux/of_address.h>
382266ad CM	25
382266ad CM	26	#include <asm/cacheflush.h>
382266ad CM	27	#include <asm/hardware/cache-l2x0.h>
	28
	29	#define CACHE_LINE_SIZE 32
	30
	31	static void __iomem *l2x0_base;
bd31b859	32	static DEFINE_RAW_SPINLOCK(l2x0_lock);
3e175ca4 RK	33	static u32 l2x0_way_mask; /* Bitmask of active ways */
3e175ca4 RK	34	static u32 l2x0_size;
f154fe9b	35	static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
382266ad	36
91c2ebb9 BS	37	struct l2x0_regs l2x0_saved_regs;
	38
	39	struct l2x0_of_data {
3e175ca4	40	void (setup)(const struct device_node , u32 , u32 );
91c2ebb9 BS	41	void (*save)(void);
	42	void (*resume)(void);
	43	};
	44
9a6655e4	45	static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
382266ad	46	{
9a6655e4	47	/* wait for cache operation by line or way to complete */
6775a558	48	while (readl_relaxed(reg) & mask)
1caf3092	49	cpu_relax();
382266ad CM	50	}
382266ad CM	51
9a6655e4 CM	52	#ifdef CONFIG_CACHE_PL310
	53	static inline void cache_wait(void __iomem *reg, unsigned long mask)
	54	{
	55	/* cache operations by line are atomic on PL310 */
	56	}
	57	#else
	58	#define cache_wait cache_wait_way
	59	#endif
	60
382266ad CM	61	static inline void cache_sync(void)
382266ad CM	62	{
3d107434	63	void __iomem *base = l2x0_base;
885028e4	64
f154fe9b	65	writel_relaxed(0, base + sync_reg_offset);
3d107434	66	cache_wait(base + L2X0_CACHE_SYNC, 1);
382266ad CM	67	}
382266ad CM	68
424d6b14 SS	69	static inline void l2x0_clean_line(unsigned long addr)
	70	{
	71	void __iomem *base = l2x0_base;
	72	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
6775a558	73	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
424d6b14 SS	74	}
	75
	76	static inline void l2x0_inv_line(unsigned long addr)
	77	{
	78	void __iomem *base = l2x0_base;
	79	cache_wait(base + L2X0_INV_LINE_PA, 1);
6775a558	80	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
424d6b14 SS	81	}
424d6b14 SS	82
2839e06c	83	#if defined(CONFIG_PL310_ERRATA_588369) \|\| defined(CONFIG_PL310_ERRATA_727915)
9e65582a	84
2839e06c SS	85	#define debug_writel(val) outer_cache.set_debug(val)
	86
	87	static void l2x0_set_debug(unsigned long val)
	88	{
	89	writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
9e65582a	90	}
2839e06c SS	91	#else
	92	/* Optimised out for non-errata case */
	93	static inline void debug_writel(unsigned long val)
	94	{
	95	}
	96
	97	#define l2x0_set_debug NULL
	98	#endif
9e65582a	99
2839e06c	100	#ifdef CONFIG_PL310_ERRATA_588369
9e65582a SS	101	static inline void l2x0_flush_line(unsigned long addr)
	102	{
	103	void __iomem *base = l2x0_base;
	104
	105	/* Clean by PA followed by Invalidate by PA */
	106	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
6775a558	107	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
9e65582a	108	cache_wait(base + L2X0_INV_LINE_PA, 1);
6775a558	109	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
9e65582a SS	110	}
	111	#else
	112
424d6b14 SS	113	static inline void l2x0_flush_line(unsigned long addr)
	114	{
	115	void __iomem *base = l2x0_base;
	116	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
6775a558	117	writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
424d6b14	118	}
9e65582a	119	#endif
424d6b14	120
23107c54 CM	121	static void l2x0_cache_sync(void)
	122	{
	123	unsigned long flags;
	124
bd31b859	125	raw_spin_lock_irqsave(&l2x0_lock, flags);
23107c54	126	cache_sync();
bd31b859	127	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
23107c54 CM	128	}
23107c54 CM	129
38a8914f	130	static void __l2x0_flush_all(void)
2fd86589	131	{
2839e06c	132	debug_writel(0x03);
2fd86589 TG	133	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
	134	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
	135	cache_sync();
2839e06c	136	debug_writel(0x00);
38a8914f WD	137	}
	138
	139	static void l2x0_flush_all(void)
	140	{
	141	unsigned long flags;
	142
	143	/* clean all ways */
bd31b859	144	raw_spin_lock_irqsave(&l2x0_lock, flags);
38a8914f	145	__l2x0_flush_all();
bd31b859	146	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
2fd86589 TG	147	}
2fd86589 TG	148
444457c1 SS	149	static void l2x0_clean_all(void)
	150	{
	151	unsigned long flags;
	152
	153	/* clean all ways */
bd31b859	154	raw_spin_lock_irqsave(&l2x0_lock, flags);
444457c1 SS	155	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
	156	cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
	157	cache_sync();
bd31b859	158	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
444457c1 SS	159	}
444457c1 SS	160
2fd86589	161	static void l2x0_inv_all(void)
382266ad	162	{
0eb948dd RK	163	unsigned long flags;
0eb948dd RK	164
382266ad	165	/* invalidate all ways */
bd31b859	166	raw_spin_lock_irqsave(&l2x0_lock, flags);
2fd86589 TG	167	/* Invalidating when L2 is enabled is a nono */
2fd86589 TG	168	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
6775a558	169	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
9a6655e4	170	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
382266ad	171	cache_sync();
bd31b859	172	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	173	}
	174
	175	static void l2x0_inv_range(unsigned long start, unsigned long end)
	176	{
3d107434	177	void __iomem *base = l2x0_base;
0eb948dd	178	unsigned long flags;
382266ad	179
bd31b859	180	raw_spin_lock_irqsave(&l2x0_lock, flags);
4f6627ac RS	181	if (start & (CACHE_LINE_SIZE - 1)) {
4f6627ac RS	182	start &= ~(CACHE_LINE_SIZE - 1);
9e65582a	183	debug_writel(0x03);
424d6b14	184	l2x0_flush_line(start);
9e65582a	185	debug_writel(0x00);
4f6627ac RS	186	start += CACHE_LINE_SIZE;
	187	}
	188
	189	if (end & (CACHE_LINE_SIZE - 1)) {
	190	end &= ~(CACHE_LINE_SIZE - 1);
9e65582a	191	debug_writel(0x03);
424d6b14	192	l2x0_flush_line(end);
9e65582a	193	debug_writel(0x00);
4f6627ac RS	194	}
4f6627ac RS	195
0eb948dd RK	196	while (start < end) {
	197	unsigned long blk_end = start + min(end - start, 4096UL);
	198
	199	while (start < blk_end) {
424d6b14	200	l2x0_inv_line(start);
0eb948dd RK	201	start += CACHE_LINE_SIZE;
	202	}
	203
	204	if (blk_end < end) {
bd31b859 TG	205	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
bd31b859 TG	206	raw_spin_lock_irqsave(&l2x0_lock, flags);
0eb948dd RK	207	}
0eb948dd RK	208	}
3d107434	209	cache_wait(base + L2X0_INV_LINE_PA, 1);
382266ad	210	cache_sync();
bd31b859	211	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	212	}
	213
	214	static void l2x0_clean_range(unsigned long start, unsigned long end)
	215	{
3d107434	216	void __iomem *base = l2x0_base;
0eb948dd	217	unsigned long flags;
382266ad	218
444457c1 SS	219	if ((end - start) >= l2x0_size) {
	220	l2x0_clean_all();
	221	return;
	222	}
	223
bd31b859	224	raw_spin_lock_irqsave(&l2x0_lock, flags);
382266ad	225	start &= ~(CACHE_LINE_SIZE - 1);
0eb948dd RK	226	while (start < end) {
	227	unsigned long blk_end = start + min(end - start, 4096UL);
	228
	229	while (start < blk_end) {
424d6b14	230	l2x0_clean_line(start);
0eb948dd RK	231	start += CACHE_LINE_SIZE;
	232	}
	233
	234	if (blk_end < end) {
bd31b859 TG	235	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
bd31b859 TG	236	raw_spin_lock_irqsave(&l2x0_lock, flags);
0eb948dd RK	237	}
0eb948dd RK	238	}
3d107434	239	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
382266ad	240	cache_sync();
bd31b859	241	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	242	}
	243
	244	static void l2x0_flush_range(unsigned long start, unsigned long end)
	245	{
3d107434	246	void __iomem *base = l2x0_base;
0eb948dd	247	unsigned long flags;
382266ad	248
444457c1 SS	249	if ((end - start) >= l2x0_size) {
	250	l2x0_flush_all();
	251	return;
	252	}
	253
bd31b859	254	raw_spin_lock_irqsave(&l2x0_lock, flags);
382266ad	255	start &= ~(CACHE_LINE_SIZE - 1);
0eb948dd RK	256	while (start < end) {
	257	unsigned long blk_end = start + min(end - start, 4096UL);
	258
9e65582a	259	debug_writel(0x03);
0eb948dd	260	while (start < blk_end) {
424d6b14	261	l2x0_flush_line(start);
0eb948dd RK	262	start += CACHE_LINE_SIZE;
0eb948dd RK	263	}
9e65582a	264	debug_writel(0x00);
0eb948dd RK	265
0eb948dd RK	266	if (blk_end < end) {
bd31b859 TG	267	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
bd31b859 TG	268	raw_spin_lock_irqsave(&l2x0_lock, flags);
0eb948dd RK	269	}
0eb948dd RK	270	}
3d107434	271	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
382266ad	272	cache_sync();
bd31b859	273	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
382266ad CM	274	}
382266ad CM	275
2fd86589 TG	276	static void l2x0_disable(void)
	277	{
	278	unsigned long flags;
	279
bd31b859	280	raw_spin_lock_irqsave(&l2x0_lock, flags);
38a8914f WD	281	__l2x0_flush_all();
	282	writel_relaxed(0, l2x0_base + L2X0_CTRL);
	283	dsb();
bd31b859	284	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
2fd86589 TG	285	}
2fd86589 TG	286
3e175ca4	287	static void l2x0_unlock(u32 cache_id)
bac7e6ec LW	288	{
	289	int lockregs;
	290	int i;
	291
	292	if (cache_id == L2X0_CACHE_ID_PART_L310)
	293	lockregs = 8;
	294	else
	295	/* L210 and unknown types */
	296	lockregs = 1;
	297
	298	for (i = 0; i < lockregs; i++) {
	299	writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
	300	i * L2X0_LOCKDOWN_STRIDE);
	301	writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
	302	i * L2X0_LOCKDOWN_STRIDE);
	303	}
	304	}
	305
3e175ca4	306	void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
382266ad	307	{
3e175ca4 RK	308	u32 aux;
	309	u32 cache_id;
	310	u32 way_size = 0;
64039be8 JM	311	int ways;
64039be8 JM	312	const char *type;
382266ad CM	313
	314	l2x0_base = base;
	315
6775a558 CM	316	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
6775a558 CM	317	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
64039be8	318
4082cfa7 SH	319	aux &= aux_mask;
	320	aux \|= aux_val;
	321
64039be8 JM	322	/* Determine the number of ways */
	323	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	324	case L2X0_CACHE_ID_PART_L310:
	325	if (aux & (1 << 16))
	326	ways = 16;
	327	else
	328	ways = 8;
	329	type = "L310";
f154fe9b WD	330	#ifdef CONFIG_PL310_ERRATA_753970
	331	/* Unmapped register. */
	332	sync_reg_offset = L2X0_DUMMY_REG;
	333	#endif
64039be8 JM	334	break;
	335	case L2X0_CACHE_ID_PART_L210:
	336	ways = (aux >> 13) & 0xf;
	337	type = "L210";
	338	break;
	339	default:
	340	/* Assume unknown chips have 8 ways */
	341	ways = 8;
	342	type = "L2x0 series";
	343	break;
	344	}
	345
	346	l2x0_way_mask = (1 << ways) - 1;
	347
5ba70372 SS	348	/*
	349	* L2 cache Size = Way size * Number of ways
	350	*/
	351	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
	352	way_size = 1 << (way_size + 3);
	353	l2x0_size = ways * way_size * SZ_1K;
	354
48371cd3 SK	355	/*
	356	* Check if l2x0 controller is already enabled.
	357	* If you are booting from non-secure mode
	358	* accessing the below registers will fault.
	359	*/
6775a558	360	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
bac7e6ec LW	361	/* Make sure that I&D is not locked down when starting */
bac7e6ec LW	362	l2x0_unlock(cache_id);
382266ad	363
48371cd3	364	/* l2x0 controller is disabled */
6775a558	365	writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
382266ad	366
91c2ebb9 BS	367	l2x0_saved_regs.aux_ctrl = aux;
91c2ebb9 BS	368
48371cd3 SK	369	l2x0_inv_all();
	370
	371	/* enable L2X0 */
6775a558	372	writel_relaxed(1, l2x0_base + L2X0_CTRL);
48371cd3	373	}
382266ad CM	374
	375	outer_cache.inv_range = l2x0_inv_range;
	376	outer_cache.clean_range = l2x0_clean_range;
	377	outer_cache.flush_range = l2x0_flush_range;
23107c54	378	outer_cache.sync = l2x0_cache_sync;
2fd86589 TG	379	outer_cache.flush_all = l2x0_flush_all;
	380	outer_cache.inv_all = l2x0_inv_all;
	381	outer_cache.disable = l2x0_disable;
2839e06c	382	outer_cache.set_debug = l2x0_set_debug;
382266ad	383
64039be8	384	printk(KERN_INFO "%s cache controller enabled\n", type);
5ba70372 SS	385	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
5ba70372 SS	386	ways, cache_id, aux, l2x0_size);
382266ad	387	}
8c369264 RH	388
	389	#ifdef CONFIG_OF
	390	static void __init l2x0_of_setup(const struct device_node *np,
3e175ca4	391	u32 aux_val, u32 aux_mask)
8c369264 RH	392	{
	393	u32 data[2] = { 0, 0 };
	394	u32 tag = 0;
	395	u32 dirty = 0;
	396	u32 val = 0, mask = 0;
	397
	398	of_property_read_u32(np, "arm,tag-latency", &tag);
	399	if (tag) {
	400	mask \|= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
	401	val \|= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
	402	}
	403
	404	of_property_read_u32_array(np, "arm,data-latency",
	405	data, ARRAY_SIZE(data));
	406	if (data[0] && data[1]) {
	407	mask \|= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK \|
	408	L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
	409	val \|= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) \|
	410	((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
	411	}
	412
	413	of_property_read_u32(np, "arm,dirty-latency", &dirty);
	414	if (dirty) {
	415	mask \|= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
	416	val \|= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
	417	}
	418
	419	*aux_val &= ~mask;
	420	*aux_val \|= val;
	421	*aux_mask &= ~mask;
	422	}
	423
	424	static void __init pl310_of_setup(const struct device_node *np,
3e175ca4	425	u32 aux_val, u32 aux_mask)
8c369264 RH	426	{
	427	u32 data[3] = { 0, 0, 0 };
	428	u32 tag[3] = { 0, 0, 0 };
	429	u32 filter[2] = { 0, 0 };
	430
	431	of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
	432	if (tag[0] && tag[1] && tag[2])
	433	writel_relaxed(
	434	((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) \|
	435	((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) \|
	436	((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
	437	l2x0_base + L2X0_TAG_LATENCY_CTRL);
	438
	439	of_property_read_u32_array(np, "arm,data-latency",
	440	data, ARRAY_SIZE(data));
	441	if (data[0] && data[1] && data[2])
	442	writel_relaxed(
	443	((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) \|
	444	((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) \|
	445	((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
	446	l2x0_base + L2X0_DATA_LATENCY_CTRL);
	447
	448	of_property_read_u32_array(np, "arm,filter-ranges",
	449	filter, ARRAY_SIZE(filter));
74d41f39	450	if (filter[1]) {
8c369264 RH	451	writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
	452	l2x0_base + L2X0_ADDR_FILTER_END);
	453	writel_relaxed((filter[0] & ~(SZ_1M - 1)) \| L2X0_ADDR_FILTER_EN,
	454	l2x0_base + L2X0_ADDR_FILTER_START);
	455	}
	456	}
	457
91c2ebb9 BS	458	static void __init pl310_save(void)
	459	{
	460	u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
	461	L2X0_CACHE_ID_RTL_MASK;
	462
	463	l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
	464	L2X0_TAG_LATENCY_CTRL);
	465	l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
	466	L2X0_DATA_LATENCY_CTRL);
	467	l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
	468	L2X0_ADDR_FILTER_END);
	469	l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
	470	L2X0_ADDR_FILTER_START);
	471
	472	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
	473	/*
	474	* From r2p0, there is Prefetch offset/control register
	475	*/
	476	l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
	477	L2X0_PREFETCH_CTRL);
	478	/*
	479	* From r3p0, there is Power control register
	480	*/
	481	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
	482	l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
	483	L2X0_POWER_CTRL);
	484	}
	485	}
	486
	487	static void l2x0_resume(void)
	488	{
	489	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
	490	/* restore aux ctrl and enable l2 */
	491	l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
	492
	493	writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
	494	L2X0_AUX_CTRL);
	495
	496	l2x0_inv_all();
	497
	498	writel_relaxed(1, l2x0_base + L2X0_CTRL);
	499	}
	500	}
	501
	502	static void pl310_resume(void)
	503	{
	504	u32 l2x0_revision;
	505
	506	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
	507	/* restore pl310 setup */
	508	writel_relaxed(l2x0_saved_regs.tag_latency,
	509	l2x0_base + L2X0_TAG_LATENCY_CTRL);
	510	writel_relaxed(l2x0_saved_regs.data_latency,
	511	l2x0_base + L2X0_DATA_LATENCY_CTRL);
	512	writel_relaxed(l2x0_saved_regs.filter_end,
	513	l2x0_base + L2X0_ADDR_FILTER_END);
	514	writel_relaxed(l2x0_saved_regs.filter_start,
	515	l2x0_base + L2X0_ADDR_FILTER_START);
	516
	517	l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
	518	L2X0_CACHE_ID_RTL_MASK;
	519
	520	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
	521	writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
522	l2x0_base + L2X0_PREFETCH_CTRL);
523	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
524	writel_relaxed(l2x0_saved_regs.pwr_ctrl,
525	l2x0_base + L2X0_POWER_CTRL);
526	}
527	}
528
529	l2x0_resume();
530	}
531
532	static const struct l2x0_of_data pl310_data = {
533	pl310_of_setup,
534	pl310_save,
535	pl310_resume,
536	};
537
538	static const struct l2x0_of_data l2x0_data = {
539	l2x0_of_setup,
540	NULL,
541	l2x0_resume,
542	};
543
8c369264	544	static const struct of_device_id l2x0_ids[] __initconst = {
91c2ebb9 BS	545	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
	546	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
	547	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
8c369264 RH	548	{}
	549	};
	550
3e175ca4	551	int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
8c369264 RH	552	{
8c369264 RH	553	struct device_node *np;
91c2ebb9 BS	554	struct l2x0_of_data *data;
91c2ebb9 BS	555	struct resource res;
8c369264 RH	556
	557	np = of_find_matching_node(NULL, l2x0_ids);
	558	if (!np)
	559	return -ENODEV;
91c2ebb9 BS	560
	561	if (of_address_to_resource(np, 0, &res))
	562	return -ENODEV;
	563
	564	l2x0_base = ioremap(res.start, resource_size(&res));
8c369264 RH	565	if (!l2x0_base)
	566	return -ENOMEM;
	567
91c2ebb9 BS	568	l2x0_saved_regs.phy_base = res.start;
	569
	570	data = of_match_node(l2x0_ids, np)->data;
	571
8c369264 RH	572	/* L2 configuration can only be changed if the cache is disabled */
8c369264 RH	573	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
91c2ebb9 BS	574	if (data->setup)
91c2ebb9 BS	575	data->setup(np, &aux_val, &aux_mask);
8c369264	576	}
91c2ebb9 BS	577
	578	if (data->save)
	579	data->save();
	580
8c369264	581	l2x0_init(l2x0_base, aux_val, aux_mask);
91c2ebb9 BS	582
91c2ebb9 BS	583	outer_cache.resume = data->resume;
8c369264 RH	584	return 0;
	585	}
	586	#endif