]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/cache-v4.S | |
3 | * | |
4 | * Copyright (C) 1997-2002 Russell king | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/linkage.h> | |
11 | #include <linux/init.h> | |
a09e64fb | 12 | #include <mach/hardware.h> |
1da177e4 LT |
13 | #include <asm/page.h> |
14 | #include "proc-macros.S" | |
15 | ||
16 | /* | |
17 | * flush_user_cache_all() | |
18 | * | |
19 | * Invalidate all cache entries in a particular address | |
20 | * space. | |
21 | * | |
22 | * - mm - mm_struct describing address space | |
23 | */ | |
24 | ENTRY(v4_flush_user_cache_all) | |
25 | /* FALLTHROUGH */ | |
26 | /* | |
27 | * flush_kern_cache_all() | |
28 | * | |
29 | * Clean and invalidate the entire cache. | |
30 | */ | |
31 | ENTRY(v4_flush_kern_cache_all) | |
f12d0d7c | 32 | #ifdef CPU_CP15 |
1da177e4 LT |
33 | mov r0, #0 |
34 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache | |
35 | mov pc, lr | |
f12d0d7c HC |
36 | #else |
37 | /* FALLTHROUGH */ | |
38 | #endif | |
1da177e4 LT |
39 | |
40 | /* | |
41 | * flush_user_cache_range(start, end, flags) | |
42 | * | |
43 | * Invalidate a range of cache entries in the specified | |
44 | * address space. | |
45 | * | |
46 | * - start - start address (may not be aligned) | |
47 | * - end - end address (exclusive, may not be aligned) | |
48 | * - flags - vma_area_struct flags describing address space | |
49 | */ | |
50 | ENTRY(v4_flush_user_cache_range) | |
f12d0d7c | 51 | #ifdef CPU_CP15 |
1da177e4 LT |
52 | mov ip, #0 |
53 | mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache | |
54 | mov pc, lr | |
f12d0d7c HC |
55 | #else |
56 | /* FALLTHROUGH */ | |
57 | #endif | |
1da177e4 LT |
58 | |
59 | /* | |
60 | * coherent_kern_range(start, end) | |
61 | * | |
62 | * Ensure coherency between the Icache and the Dcache in the | |
63 | * region described by start. If you have non-snooping | |
64 | * Harvard caches, you need to implement this function. | |
65 | * | |
66 | * - start - virtual start address | |
67 | * - end - virtual end address | |
68 | */ | |
69 | ENTRY(v4_coherent_kern_range) | |
70 | /* FALLTHROUGH */ | |
71 | ||
72 | /* | |
73 | * coherent_user_range(start, end) | |
74 | * | |
75 | * Ensure coherency between the Icache and the Dcache in the | |
76 | * region described by start. If you have non-snooping | |
77 | * Harvard caches, you need to implement this function. | |
78 | * | |
79 | * - start - virtual start address | |
80 | * - end - virtual end address | |
81 | */ | |
82 | ENTRY(v4_coherent_user_range) | |
83 | mov pc, lr | |
84 | ||
85 | /* | |
86 | * flush_kern_dcache_page(void *page) | |
87 | * | |
88 | * Ensure no D cache aliasing occurs, either with itself or | |
89 | * the I cache | |
90 | * | |
91 | * - addr - page aligned address | |
92 | */ | |
93 | ENTRY(v4_flush_kern_dcache_page) | |
94 | /* FALLTHROUGH */ | |
95 | ||
96 | /* | |
97 | * dma_inv_range(start, end) | |
98 | * | |
99 | * Invalidate (discard) the specified virtual address range. | |
100 | * May not write back any entries. If 'start' or 'end' | |
101 | * are not cache line aligned, those lines must be written | |
102 | * back. | |
103 | * | |
104 | * - start - virtual start address | |
105 | * - end - virtual end address | |
106 | */ | |
107 | ENTRY(v4_dma_inv_range) | |
108 | /* FALLTHROUGH */ | |
109 | ||
110 | /* | |
111 | * dma_flush_range(start, end) | |
112 | * | |
113 | * Clean and invalidate the specified virtual address range. | |
114 | * | |
115 | * - start - virtual start address | |
116 | * - end - virtual end address | |
117 | */ | |
118 | ENTRY(v4_dma_flush_range) | |
f12d0d7c | 119 | #ifdef CPU_CP15 |
1da177e4 LT |
120 | mov r0, #0 |
121 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache | |
f12d0d7c | 122 | #endif |
1da177e4 LT |
123 | /* FALLTHROUGH */ |
124 | ||
125 | /* | |
126 | * dma_clean_range(start, end) | |
127 | * | |
128 | * Clean (write back) the specified virtual address range. | |
129 | * | |
130 | * - start - virtual start address | |
131 | * - end - virtual end address | |
132 | */ | |
133 | ENTRY(v4_dma_clean_range) | |
134 | mov pc, lr | |
135 | ||
136 | __INITDATA | |
137 | ||
138 | .type v4_cache_fns, #object | |
139 | ENTRY(v4_cache_fns) | |
140 | .long v4_flush_kern_cache_all | |
141 | .long v4_flush_user_cache_all | |
142 | .long v4_flush_user_cache_range | |
143 | .long v4_coherent_kern_range | |
144 | .long v4_coherent_user_range | |
145 | .long v4_flush_kern_dcache_page | |
146 | .long v4_dma_inv_range | |
147 | .long v4_dma_clean_range | |
148 | .long v4_dma_flush_range | |
149 | .size v4_cache_fns, . - v4_cache_fns |