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bbe88886 CM |
1 | /* |
2 | * linux/arch/arm/mm/cache-v7.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * Copyright (C) 2005 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This is the "shell" of the ARMv7 processor support. | |
12 | */ | |
13 | #include <linux/linkage.h> | |
14 | #include <linux/init.h> | |
15 | #include <asm/assembler.h> | |
32cfb1b1 | 16 | #include <asm/unwind.h> |
bbe88886 CM |
17 | |
18 | #include "proc-macros.S" | |
19 | ||
81d11955 TL |
20 | /* |
21 | * v7_flush_icache_all() | |
22 | * | |
23 | * Flush the whole I-cache. | |
24 | * | |
25 | * Registers: | |
26 | * r0 - set to 0 | |
27 | */ | |
28 | ENTRY(v7_flush_icache_all) | |
29 | mov r0, #0 | |
30 | ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable | |
31 | ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate | |
32 | mov pc, lr | |
33 | ENDPROC(v7_flush_icache_all) | |
34 | ||
bbe88886 CM |
35 | /* |
36 | * v7_flush_dcache_all() | |
37 | * | |
38 | * Flush the whole D-cache. | |
39 | * | |
347c8b70 | 40 | * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) |
bbe88886 CM |
41 | * |
42 | * - mm - mm_struct describing address space | |
43 | */ | |
44 | ENTRY(v7_flush_dcache_all) | |
c30c2f99 | 45 | dmb @ ensure ordering with previous memory accesses |
bbe88886 CM |
46 | mrc p15, 1, r0, c0, c0, 1 @ read clidr |
47 | ands r3, r0, #0x7000000 @ extract loc from clidr | |
48 | mov r3, r3, lsr #23 @ left align loc bit field | |
49 | beq finished @ if loc is 0, then no need to clean | |
50 | mov r10, #0 @ start clean at cache level 0 | |
51 | loop1: | |
52 | add r2, r10, r10, lsr #1 @ work out 3x current cache level | |
53 | mov r1, r0, lsr r2 @ extract cache type bits from clidr | |
54 | and r1, r1, #7 @ mask of the bits for current cache only | |
55 | cmp r1, #2 @ see what cache we have at this level | |
56 | blt skip @ skip if no cache, or just i-cache | |
57 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
58 | isb @ isb to sych the new cssr&csidr | |
59 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | |
60 | and r2, r1, #7 @ extract the length of the cache lines | |
61 | add r2, r2, #4 @ add 4 (line length offset) | |
62 | ldr r4, =0x3ff | |
63 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size | |
64 | clz r5, r4 @ find bit position of way size increment | |
65 | ldr r7, =0x7fff | |
66 | ands r7, r7, r1, lsr #13 @ extract max number of the index size | |
67 | loop2: | |
68 | mov r9, r4 @ create working copy of max way size | |
69 | loop3: | |
347c8b70 CM |
70 | ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 |
71 | THUMB( lsl r6, r9, r5 ) | |
72 | THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 | |
73 | ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 | |
74 | THUMB( lsl r6, r7, r2 ) | |
75 | THUMB( orr r11, r11, r6 ) @ factor index number into r11 | |
bbe88886 CM |
76 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way |
77 | subs r9, r9, #1 @ decrement the way | |
78 | bge loop3 | |
79 | subs r7, r7, #1 @ decrement the index | |
80 | bge loop2 | |
81 | skip: | |
82 | add r10, r10, #2 @ increment cache number | |
83 | cmp r3, r10 | |
84 | bgt loop1 | |
85 | finished: | |
86 | mov r10, #0 @ swith back to cache level 0 | |
87 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
c30c2f99 | 88 | dsb |
bbe88886 CM |
89 | isb |
90 | mov pc, lr | |
93ed3970 | 91 | ENDPROC(v7_flush_dcache_all) |
bbe88886 CM |
92 | |
93 | /* | |
94 | * v7_flush_cache_all() | |
95 | * | |
96 | * Flush the entire cache system. | |
97 | * The data cache flush is now achieved using atomic clean / invalidates | |
98 | * working outwards from L1 cache. This is done using Set/Way based cache | |
25985edc | 99 | * maintenance instructions. |
bbe88886 CM |
100 | * The instruction cache can still be invalidated back to the point of |
101 | * unification in a single instruction. | |
102 | * | |
103 | */ | |
104 | ENTRY(v7_flush_kern_cache_all) | |
347c8b70 CM |
105 | ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) |
106 | THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) | |
bbe88886 CM |
107 | bl v7_flush_dcache_all |
108 | mov r0, #0 | |
f00ec48f RK |
109 | ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable |
110 | ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate | |
347c8b70 CM |
111 | ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) |
112 | THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) | |
bbe88886 | 113 | mov pc, lr |
93ed3970 | 114 | ENDPROC(v7_flush_kern_cache_all) |
bbe88886 CM |
115 | |
116 | /* | |
117 | * v7_flush_cache_all() | |
118 | * | |
119 | * Flush all TLB entries in a particular address space | |
120 | * | |
121 | * - mm - mm_struct describing address space | |
122 | */ | |
123 | ENTRY(v7_flush_user_cache_all) | |
124 | /*FALLTHROUGH*/ | |
125 | ||
126 | /* | |
127 | * v7_flush_cache_range(start, end, flags) | |
128 | * | |
129 | * Flush a range of TLB entries in the specified address space. | |
130 | * | |
131 | * - start - start address (may not be aligned) | |
132 | * - end - end address (exclusive, may not be aligned) | |
133 | * - flags - vm_area_struct flags describing address space | |
134 | * | |
135 | * It is assumed that: | |
136 | * - we have a VIPT cache. | |
137 | */ | |
138 | ENTRY(v7_flush_user_cache_range) | |
139 | mov pc, lr | |
93ed3970 CM |
140 | ENDPROC(v7_flush_user_cache_all) |
141 | ENDPROC(v7_flush_user_cache_range) | |
bbe88886 CM |
142 | |
143 | /* | |
144 | * v7_coherent_kern_range(start,end) | |
145 | * | |
146 | * Ensure that the I and D caches are coherent within specified | |
147 | * region. This is typically used when code has been written to | |
148 | * a memory region, and will be executed. | |
149 | * | |
150 | * - start - virtual start address of region | |
151 | * - end - virtual end address of region | |
152 | * | |
153 | * It is assumed that: | |
154 | * - the Icache does not read data from the write buffer | |
155 | */ | |
156 | ENTRY(v7_coherent_kern_range) | |
157 | /* FALLTHROUGH */ | |
158 | ||
159 | /* | |
160 | * v7_coherent_user_range(start,end) | |
161 | * | |
162 | * Ensure that the I and D caches are coherent within specified | |
163 | * region. This is typically used when code has been written to | |
164 | * a memory region, and will be executed. | |
165 | * | |
166 | * - start - virtual start address of region | |
167 | * - end - virtual end address of region | |
168 | * | |
169 | * It is assumed that: | |
170 | * - the Icache does not read data from the write buffer | |
171 | */ | |
172 | ENTRY(v7_coherent_user_range) | |
32cfb1b1 | 173 | UNWIND(.fnstart ) |
bbe88886 CM |
174 | dcache_line_size r2, r3 |
175 | sub r3, r2, #1 | |
da30e0ac | 176 | bic r12, r0, r3 |
32cfb1b1 | 177 | 1: |
da30e0ac CM |
178 | USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification |
179 | add r12, r12, r2 | |
180 | cmp r12, r1 | |
181 | blo 1b | |
bbe88886 | 182 | dsb |
da30e0ac CM |
183 | icache_line_size r2, r3 |
184 | sub r3, r2, #1 | |
185 | bic r12, r0, r3 | |
32cfb1b1 | 186 | 2: |
da30e0ac CM |
187 | USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line |
188 | add r12, r12, r2 | |
189 | cmp r12, r1 | |
190 | blo 2b | |
191 | 3: | |
bbe88886 | 192 | mov r0, #0 |
f00ec48f RK |
193 | ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable |
194 | ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB | |
bbe88886 CM |
195 | dsb |
196 | isb | |
197 | mov pc, lr | |
32cfb1b1 CM |
198 | |
199 | /* | |
200 | * Fault handling for the cache operation above. If the virtual address in r0 | |
201 | * isn't mapped, just try the next page. | |
202 | */ | |
203 | 9001: | |
da30e0ac CM |
204 | mov r12, r12, lsr #12 |
205 | mov r12, r12, lsl #12 | |
206 | add r12, r12, #4096 | |
207 | b 3b | |
32cfb1b1 | 208 | UNWIND(.fnend ) |
93ed3970 CM |
209 | ENDPROC(v7_coherent_kern_range) |
210 | ENDPROC(v7_coherent_user_range) | |
bbe88886 CM |
211 | |
212 | /* | |
2c9b9c84 | 213 | * v7_flush_kern_dcache_area(void *addr, size_t size) |
bbe88886 CM |
214 | * |
215 | * Ensure that the data held in the page kaddr is written back | |
216 | * to the page in question. | |
217 | * | |
2c9b9c84 RK |
218 | * - addr - kernel address |
219 | * - size - region size | |
bbe88886 | 220 | */ |
2c9b9c84 | 221 | ENTRY(v7_flush_kern_dcache_area) |
bbe88886 | 222 | dcache_line_size r2, r3 |
2c9b9c84 | 223 | add r1, r0, r1 |
bbe88886 CM |
224 | 1: |
225 | mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line | |
226 | add r0, r0, r2 | |
227 | cmp r0, r1 | |
228 | blo 1b | |
229 | dsb | |
230 | mov pc, lr | |
2c9b9c84 | 231 | ENDPROC(v7_flush_kern_dcache_area) |
bbe88886 CM |
232 | |
233 | /* | |
234 | * v7_dma_inv_range(start,end) | |
235 | * | |
236 | * Invalidate the data cache within the specified region; we will | |
237 | * be performing a DMA operation in this region and we want to | |
238 | * purge old data in the cache. | |
239 | * | |
240 | * - start - virtual start address of region | |
241 | * - end - virtual end address of region | |
242 | */ | |
702b94bf | 243 | v7_dma_inv_range: |
bbe88886 CM |
244 | dcache_line_size r2, r3 |
245 | sub r3, r2, #1 | |
246 | tst r0, r3 | |
247 | bic r0, r0, r3 | |
248 | mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line | |
249 | ||
250 | tst r1, r3 | |
251 | bic r1, r1, r3 | |
252 | mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line | |
253 | 1: | |
254 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line | |
255 | add r0, r0, r2 | |
256 | cmp r0, r1 | |
257 | blo 1b | |
258 | dsb | |
259 | mov pc, lr | |
93ed3970 | 260 | ENDPROC(v7_dma_inv_range) |
bbe88886 CM |
261 | |
262 | /* | |
263 | * v7_dma_clean_range(start,end) | |
264 | * - start - virtual start address of region | |
265 | * - end - virtual end address of region | |
266 | */ | |
702b94bf | 267 | v7_dma_clean_range: |
bbe88886 CM |
268 | dcache_line_size r2, r3 |
269 | sub r3, r2, #1 | |
270 | bic r0, r0, r3 | |
271 | 1: | |
272 | mcr p15, 0, r0, c7, c10, 1 @ clean D / U line | |
273 | add r0, r0, r2 | |
274 | cmp r0, r1 | |
275 | blo 1b | |
276 | dsb | |
277 | mov pc, lr | |
93ed3970 | 278 | ENDPROC(v7_dma_clean_range) |
bbe88886 CM |
279 | |
280 | /* | |
281 | * v7_dma_flush_range(start,end) | |
282 | * - start - virtual start address of region | |
283 | * - end - virtual end address of region | |
284 | */ | |
285 | ENTRY(v7_dma_flush_range) | |
286 | dcache_line_size r2, r3 | |
287 | sub r3, r2, #1 | |
288 | bic r0, r0, r3 | |
289 | 1: | |
290 | mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line | |
291 | add r0, r0, r2 | |
292 | cmp r0, r1 | |
293 | blo 1b | |
294 | dsb | |
295 | mov pc, lr | |
93ed3970 | 296 | ENDPROC(v7_dma_flush_range) |
bbe88886 | 297 | |
a9c9147e RK |
298 | /* |
299 | * dma_map_area(start, size, dir) | |
300 | * - start - kernel virtual start address | |
301 | * - size - size of region | |
302 | * - dir - DMA direction | |
303 | */ | |
304 | ENTRY(v7_dma_map_area) | |
305 | add r1, r1, r0 | |
2ffe2da3 RK |
306 | teq r2, #DMA_FROM_DEVICE |
307 | beq v7_dma_inv_range | |
308 | b v7_dma_clean_range | |
a9c9147e RK |
309 | ENDPROC(v7_dma_map_area) |
310 | ||
311 | /* | |
312 | * dma_unmap_area(start, size, dir) | |
313 | * - start - kernel virtual start address | |
314 | * - size - size of region | |
315 | * - dir - DMA direction | |
316 | */ | |
317 | ENTRY(v7_dma_unmap_area) | |
2ffe2da3 RK |
318 | add r1, r1, r0 |
319 | teq r2, #DMA_TO_DEVICE | |
320 | bne v7_dma_inv_range | |
a9c9147e RK |
321 | mov pc, lr |
322 | ENDPROC(v7_dma_unmap_area) | |
323 | ||
bbe88886 CM |
324 | __INITDATA |
325 | ||
326 | .type v7_cache_fns, #object | |
327 | ENTRY(v7_cache_fns) | |
81d11955 | 328 | .long v7_flush_icache_all |
bbe88886 CM |
329 | .long v7_flush_kern_cache_all |
330 | .long v7_flush_user_cache_all | |
331 | .long v7_flush_user_cache_range | |
332 | .long v7_coherent_kern_range | |
333 | .long v7_coherent_user_range | |
2c9b9c84 | 334 | .long v7_flush_kern_dcache_area |
a9c9147e RK |
335 | .long v7_dma_map_area |
336 | .long v7_dma_unmap_area | |
bbe88886 CM |
337 | .long v7_dma_flush_range |
338 | .size v7_cache_fns, . - v7_cache_fns |