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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d73e60b7 RK |
2 | /* |
3 | * linux/arch/arm/mm/copypage-v4wt.S | |
4 | * | |
5 | * Copyright (C) 1995-1999 Russell King | |
6 | * | |
d73e60b7 RK |
7 | * This is for CPUs with a writethrough cache and 'flush ID cache' is |
8 | * the only supported cache operation. | |
9 | */ | |
10 | #include <linux/init.h> | |
063b0a42 | 11 | #include <linux/highmem.h> |
d73e60b7 RK |
12 | |
13 | /* | |
063b0a42 | 14 | * ARMv4 optimised copy_user_highpage |
d73e60b7 RK |
15 | * |
16 | * Since we have writethrough caches, we don't have to worry about | |
17 | * dirty data in the cache. However, we do have to ensure that | |
18 | * subsequent reads are up to date. | |
19 | */ | |
b99afae1 | 20 | static void v4wt_copy_user_page(void *kto, const void *kfrom) |
d73e60b7 | 21 | { |
b99afae1 NP |
22 | int tmp; |
23 | ||
24 | asm volatile ("\ | |
b7e8c939 | 25 | .syntax unified\n\ |
b99afae1 NP |
26 | ldmia %1!, {r3, r4, ip, lr} @ 4\n\ |
27 | 1: stmia %0!, {r3, r4, ip, lr} @ 4\n\ | |
28 | ldmia %1!, {r3, r4, ip, lr} @ 4+1\n\ | |
29 | stmia %0!, {r3, r4, ip, lr} @ 4\n\ | |
30 | ldmia %1!, {r3, r4, ip, lr} @ 4\n\ | |
31 | stmia %0!, {r3, r4, ip, lr} @ 4\n\ | |
32 | ldmia %1!, {r3, r4, ip, lr} @ 4\n\ | |
33 | subs %2, %2, #1 @ 1\n\ | |
34 | stmia %0!, {r3, r4, ip, lr} @ 4\n\ | |
b7e8c939 | 35 | ldmiane %1!, {r3, r4, ip, lr} @ 4\n\ |
d73e60b7 | 36 | bne 1b @ 1\n\ |
b99afae1 NP |
37 | mcr p15, 0, %2, c7, c7, 0 @ flush ID cache" |
38 | : "+&r" (kto), "+&r" (kfrom), "=&r" (tmp) | |
39 | : "2" (PAGE_SIZE / 64) | |
40 | : "r3", "r4", "ip", "lr"); | |
d73e60b7 RK |
41 | } |
42 | ||
063b0a42 | 43 | void v4wt_copy_user_highpage(struct page *to, struct page *from, |
f00a75c0 | 44 | unsigned long vaddr, struct vm_area_struct *vma) |
063b0a42 RK |
45 | { |
46 | void *kto, *kfrom; | |
47 | ||
5472e862 CW |
48 | kto = kmap_atomic(to); |
49 | kfrom = kmap_atomic(from); | |
063b0a42 | 50 | v4wt_copy_user_page(kto, kfrom); |
5472e862 CW |
51 | kunmap_atomic(kfrom); |
52 | kunmap_atomic(kto); | |
063b0a42 RK |
53 | } |
54 | ||
d73e60b7 RK |
55 | /* |
56 | * ARMv4 optimised clear_user_page | |
57 | * | |
58 | * Same story as above. | |
59 | */ | |
303c6443 | 60 | void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr) |
d73e60b7 | 61 | { |
5472e862 | 62 | void *ptr, *kaddr = kmap_atomic(page); |
43ae286b NP |
63 | asm volatile("\ |
64 | mov r1, %2 @ 1\n\ | |
d73e60b7 RK |
65 | mov r2, #0 @ 1\n\ |
66 | mov r3, #0 @ 1\n\ | |
67 | mov ip, #0 @ 1\n\ | |
68 | mov lr, #0 @ 1\n\ | |
303c6443 RK |
69 | 1: stmia %0!, {r2, r3, ip, lr} @ 4\n\ |
70 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ | |
71 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ | |
72 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ | |
d73e60b7 RK |
73 | subs r1, r1, #1 @ 1\n\ |
74 | bne 1b @ 1\n\ | |
303c6443 | 75 | mcr p15, 0, r2, c7, c7, 0 @ flush ID cache" |
43ae286b NP |
76 | : "=r" (ptr) |
77 | : "0" (kaddr), "I" (PAGE_SIZE / 64) | |
303c6443 | 78 | : "r1", "r2", "r3", "ip", "lr"); |
5472e862 | 79 | kunmap_atomic(kaddr); |
d73e60b7 RK |
80 | } |
81 | ||
82 | struct cpu_user_fns v4wt_user_fns __initdata = { | |
303c6443 | 83 | .cpu_clear_user_highpage = v4wt_clear_user_highpage, |
063b0a42 | 84 | .cpu_copy_user_highpage = v4wt_copy_user_highpage, |
d73e60b7 | 85 | }; |